KR20040050630A - Method for forming the semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to improve capacitance by forming a storage node electrode like a convexoconcave structure. CONSTITUTION: A pad oxide and a nitride layer are sequentially deposited on a silicon substrate(100). A photoresist pattern is formed on the pad nitride layer. The pad nitride and the oxide layer are sequentially removed for defining a storage node electrode forming region by carrying out an etching process using the photoresist pattern as an etching mask. The storage node electrode forming region is filled with a polysilicon pattern(160). The pad nitride layer is removed from the resultant structure. A silicon oxide layer(170) is formed on the upper surface of the resultant structure by carrying out an oxidation. A storage node electrode(180) is formed by depositing a polysilicon layer on the entire surface of the resultant structure.

Description

Method for manufacturing a semiconductor device {Method for forming the semiconductor device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, in a capacitor forming method of increasing capacitance of a memory device during a system-on-chip device forming process of manufacturing a logic device and a memory device on the same chip. The present invention relates to a method for fabricating a semiconductor device in which an uneven capacitor storage electrode is formed to increase the surface area of the storage electrode within the same area, thereby improving capacitance.

In general, logic devices and memory devices, which are semiconductor devices, are configured separately, but as the integration degree of semiconductor devices increases, logic devices and memory devices are the same in order to increase computational speed and increase efficiency. The importance of the system-on-chip element manufactured on a chip is increasing.

However, the process of forming the logic element and the process of forming the memory element is due to the process differences, that is, the memory element forms a capacitor which is not formed in the logic element, and thus a stacked structure for forming a conventional memory element. In particular, capacitor formation processes such as a fin type formed in a pin shape and a cylinder type formed in a cylindrical shape, such as a cylinder, are complicated and have a high step. Type capacitor formation process is used.

Accordingly, in forming a system-on-chip device for manufacturing a logic device and a memory device on the same chip, the memory cell array unit is formed by laminating a gate oxide film and a doped polysilicon and performing a photo and etching process using a gate mask. While forming a gate electrode in the active region of the substrate, the bottom electrode of the analog capacitor having the shape of a plate is simultaneously formed on the field oxide film of the logic circuit unit, and then a polysilicon for forming an insulating film and the upper electrode is sequentially stacked to form a capacitor.

However, since the lower electrode of the capacitor formed at the same time as the gate electrode is formed of a flat plate like the gate electrode, there is a limit to increasing the capacitance of the capacitor within the same area, and thus, it is difficult to manufacture a capacitor requiring a large capacity. There was a problem.

Hereinafter, with reference to the accompanying drawings, in the capacitor manufacturing method for increasing the correction capacity of the memory element during the process of forming a system-on-chip element for manufacturing the logic element and the memory element according to the prior art on the same chip as described above The problem that appears will be described in more detail.

1A to 1D are cross-sectional views sequentially illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.

According to the capacitor manufacturing method according to the prior art, first, as shown in FIG. 1A, the field oxide film 12 as a device isolation region for distinguishing the active region and the isolation region between devices on the silicon substrate 10 as a semiconductor substrate. ).

Subsequently, after the gate oxide layer and the doped polysilicon are stacked on the silicon substrate 10, the gate electrode 14a is formed in the active region of the silicon substrate 10 of the memory cell array unit 200 by a photolithography and etching process using a gate mask. ) And at the same time the lower electrode 14b of the analog capacitor is formed on the field oxide film 12 of the logic circuit unit 100. At this time, since the lower electrode 14b of the analog capacitor is formed in the same plane as the gate electrode 14a, the area of the lower electrode 14b should be increased to improve the capacitance of the capacitor. If the area is increased, the chip size is increased, resulting in difficulty in high integration of the semiconductor device.

In addition, sidewall spacers 16 formed of an insulating material are formed on sidewalls of the gate electrode 14a and the lower electrode 14b, and conductive impurities are disposed between the gate electrode 14a in an active region of the memory cell array. This ion implanted source / drain region 18 is formed.

After the process of forming the gate electrode 14a and the lower electrode 14b of the analog capacitor, an insulator 20 to be used as a dielectric of the analog capacitor is deposited on the resultant, as shown in FIG.

Next, as illustrated in FIGS. 1C and 1D, the doped polysilicon 22 is deposited on the insulator 20, and then the stacked doped polysilicon 22 is patterned by performing a photo and etching process. As a result, the upper electrode 22 'of the analog capacitor is formed.

That is, according to the capacitor manufacturing method of the semiconductor device according to the prior art, while forming the gate electrode 14a in the active region of the silicon substrate 10 of the memory cell array unit 200, at the same time the field of the logic circuit unit 100 By forming the lower electrode 14b of the analog capacitor on the oxide film 12 as a flat plate, and then laminating the insulator 20 and the doped polysilicon 22 as the upper electrode forming material thereon to form an analog capacitor, When a large capacity capacitor is required, the area of the lower electrode should be increased to improve the capacitance of the capacitor. However, when the area of the planar lower electrode is increased, the chip size becomes large. The problem of high integration becomes difficult.

In order to solve the above problems, the present invention provides a capacitor forming method for increasing the capacitance of a memory device during a system-on-chip device forming process of manufacturing a logic device and a memory device on the same chip. The purpose of the present invention is to provide a method of manufacturing a semiconductor device, by increasing the surface area of the lower electrode in the same area, thereby improving capacitance, thereby enabling high integration of the semiconductor device.

1A to 1D are cross-sectional views sequentially illustrating a method of manufacturing a capacitor of a conventional composite semiconductor device.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

-Explanation of symbols for the main parts of the drawing-

100: silicon substrate 110: pad oxide film

120: pad nitride film 130: device isolation film

140: photoresist pattern 150: capacitor storage electrode formation region

160: polysilicon pattern 170: silicon oxide film

180: capacitor storage electrode

In order to achieve the above object, the present invention comprises the steps of defining a device isolation region and an active region by forming a field oxide film in a silicon substrate on which a pad oxide film and a pad nitride film are sequentially deposited; Forming a photoresist pattern so that the remaining region except the capacitor storage electrode forming region of the active region is blocked; Sequentially removing the pad nitride film and the pad oxide film deposited on the silicon substrate of the capacitor storage electrode formation region using the photoresist pattern as an etch mask; Forming a polysilicon pattern on the capacitor storage electrode formation region from which the pad nitride film and the pad oxide film are removed; Removing the pad nitride layer over the active region; Forming a silicon oxide film by performing an oxidation process on the entire product from which the pad nitride film is removed; It provides a method of manufacturing a semiconductor device comprising the step of forming a storage electrode of the capacitor by depositing a polysilicon film on the entire product formed silicon oxide film.

That is, according to the method of manufacturing a semiconductor device according to the present invention, a concave-convex product made of a polysilicon pattern is formed on an active region, which is the capacitor storage electrode forming region, and then an oxidation process is performed on the entire product. A silicon oxide film as a gate insulating film is formed along the concave-convex shape, and polysilicon is deposited thereon to form a capacitor storage electrode, whereby the capacitor storage electrode is formed into a concave-convex shape. It is possible to increase the surface area, thereby improving the capacitance of the capacitor.

In the method of manufacturing a semiconductor device according to the present invention, the forming of the polysilicon pattern in the capacitor storage electrode forming region from which the pad nitride film and the pad oxide film are removed may be performed. Depositing polysilicon to cover the pad nitride film; Forming the polysilicon by a chemical mechanical polishing process to the upper part of the pad nitride layer, or SiH ₄ gas on the silicon substrate of the capacitor storage electrode forming region from which the pad nitride layer and the pad oxide layer are removed. It is preferable to form silicon by growing a selective epitaxial growth process using HCl gas.

Hereinafter, with reference to the accompanying drawings, it will be described in detail an embodiment of a method for manufacturing a semiconductor device according to the present invention. However, the scope of the present invention is not limited thereto, but is presented as an example.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to the present invention.

According to the manufacturing method according to the present invention, as shown in FIG. 2A, first, a pad oxide film 110 and a pad nitride film 120 are deposited on a silicon substrate 100, and then shallow trench isolation. A trench (not shown) is formed in the silicon substrate 100 by a process called " STI ", and then a high-density plasma oxide film is embedded in the trench to form a field oxide film 130 to form a silicon substrate 100. The isolation region (B) and the active region (A) are defined and defined on the upper side. In this case, the pad nitride film 120 is used as a polishing stop film in a subsequent chemical mechanical polishing process. In addition, the pad nitride film 120 is deposited to a thickness of about 2500 kW using nitride, so that a predetermined thickness remains to ensure a certain amount of capacitance of the capacitor even when over-polishing in the chemical mechanical polishing process. . Accordingly, when the polysilicon pattern having the concave-convex shape is formed, the concave-convex frame is formed so that the polysilicon is formed into the concave-convex shape.

Subsequently, the photoresist is applied to the entire product on which the field oxide film 130 is formed, and then an exposure and development process is performed such that the remaining region except for the capacitor storage electrode formation region 150 of the active region A is blocked by the photoresist. The photoresist pattern 140 having a line / spacer shape is formed.

After the process of forming the line / spacer photosensitive film pattern 140 is performed, as shown in FIG. 2B, the pad nitride film 120 and the pad are formed using the line / spacer photosensitive film pattern 140 as an etch mask. The oxide film 110 is sequentially etched, and when the pad nitride film 120 is etched, the lower pad oxide film 110 is etched by using a mixed gas of CHF ₃ and Ar and O ₂ gas having a high etching selectivity as an etching gas. The pad oxide film 110 is etched by performing a wet etching process using HF or BOE solution. Accordingly, the silicon substrate 100 of the capacitor storage electrode forming region 150 is exposed, and other regions are blocked by the pad oxide film 110 and the pad nitride film 120.

Thereafter, the photoresist pattern 140 having the line / spacer shape is removed, and then, as illustrated in FIG. 2C, the polysilicon pattern is formed on the capacitor storage electrode formation region from which the pad nitride layer 120 and the pad oxide layer 110 are removed. To form 160. In this case, the polysilicon pattern 160 formed in the capacitor storage electrode forming region is first formed so that the pad nitride film 120 is sufficiently covered with the line / spacer type photoresist pattern (not shown). Since the pad nitride film 120 is formed to a thickness of about 2500 kPa, the same polysilicon as the silicon substrate 100 of about 3000 kPa is deposited by chemical vapor deposition, and then the pad nitride film 120 is used as a polishing stop film. Polysilicon (not shown) is formed by chemical mechanical polishing to the top of the pad nitride film 120.

In addition, selective epitaxial growth (SEG) is formed on the resultant line / spacer photoresist pattern (not shown) to form a single crystal having the same orientation as that of the silicon substrate 100 by SiH ₄ gas and HCl gas. Selective Epitaxial Growth) process is used to grow silicon to form polysilicon patterns. Accordingly, since the polysilicon pattern is processed by a selective epitaxial growth process without a chemical mechanical polishing process, it is not necessary to proceed with the chemical mechanical polishing process, and the thickness of about 2500 mm in consideration of the overpolishing during the chemical polishing process As a result, a thin pad nitride film deposited at a thickness of about 2000 μs can be formed.

Meanwhile, after the process of forming the polysilicon pattern 160, as shown in FIG. 2D, the pad nitride film 120 remaining on the resultant is wet-etched and removed by a phosphate solution. The polysilicon pattern 160 forms a concave-convex pattern, which serves as a substrate for forming a storage electrode of the capacitor, that is, a concave-convex lower capacitor electrode.

Thereafter, as shown in FIG. 2E, an oxidization process is performed on the entire product from which the pad nitride layer 120 is removed to form a silicon oxide layer 170 as a gate insulating layer along the uneven polysilicon pattern 160. do. In addition, polysilicon (not shown), which is a capacitor storage electrode forming material, is deposited on the entire upper portion of the silicon oxide layer 170, and thus, polysilicon (not shown) is formed along the shape of the polysilicon pattern 160 having a lower uneven shape. ), The storage electrode 180, that is, the lower electrode of the capacitor is formed into an uneven shape. Accordingly, the surface area of the capacitor storage electrode 180 is increased in the same area as that of the conventional plate-shaped capacitor storage electrode, thereby improving the capacitance of the capacitor.

Therefore, as described above, when the semiconductor device manufacturing method according to the present invention is used, the capacitance of the memory device is increased during the system-on-chip device forming process of manufacturing the logic device and the memory device on the same chip. In the method of forming a capacitor, by forming a capacitor storage electrode having a concave-convex shape, the surface area of the lower electrode can be increased in the same area to improve the capacitance, thereby enabling the high integration of the semiconductor device. .

Claims (3)

Defining a device isolation region and an active region by forming a field oxide film in a silicon substrate on which a pad oxide film and a pad nitride film are sequentially deposited; Forming a photoresist pattern so that the remaining region except the capacitor storage electrode forming region of the active region is blocked; Sequentially removing the pad nitride film and the pad oxide film deposited on the silicon substrate of the capacitor storage electrode formation region using the photoresist pattern as an etch mask; Forming a polysilicon pattern on the capacitor storage electrode formation region from which the pad nitride film and the pad oxide film are removed; Removing the pad nitride layer over the active region; Forming a silicon oxide film by performing an oxidization process on the entire product from which the pad nitride film is removed; And depositing a polysilicon film on the entire product formed with the silicon oxide film to form a storage electrode of the capacitor. The method of claim 1, wherein the forming of the polysilicon pattern on the capacitor storage electrode forming region from which the pad nitride layer and the pad oxide layer are removed is performed. Depositing polysilicon to cover the pad nitride layer on the resultant product from which the pad nitride layer and the pad oxide layer have been removed; And performing a chemical mechanical polishing process so that the polysilicon has an upper portion of the pad nitride layer. The method of claim 1, wherein the forming of the polysilicon pattern on the capacitor storage electrode forming region from which the pad nitride layer and the pad oxide layer are removed is performed. Fabrication of a semiconductor device characterized in that to form a polysilicon by a selective epitaxial growth process by the SiH ₄ gas and HCl gas on the silicon substrate of the capacitor storage electrode formation region from which the pad nitride film and the pad oxide film is removed Way.