KR20040045801A - Manufacturing method for metal line of semiconductor device - Google Patents
Manufacturing method for metal line of semiconductor device Download PDFInfo
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- KR20040045801A KR20040045801A KR1020020073660A KR20020073660A KR20040045801A KR 20040045801 A KR20040045801 A KR 20040045801A KR 1020020073660 A KR1020020073660 A KR 1020020073660A KR 20020073660 A KR20020073660 A KR 20020073660A KR 20040045801 A KR20040045801 A KR 20040045801A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
Abstract
Description
본 발명은 알루미늄 금속배선 형성 공정에서 발생하는 디펙트를 제거하기 위한 방법에 관한 것으로, 보다 상세하게는 반도체 소자의 알루미늄 금속배선 형성과정에서, 알루미늄 금속배선 전면에 보호막을 형성하기 전에 세정을 수행했던 종래의 기술과 달리, 보호막 형성 후에 세정을 수행함으로써 알루미늄 금속배선 형성 공정에서 발생하는 디펙트를 효과적으로 제거할 수 있다.The present invention relates to a method for removing defects occurring in an aluminum metal wiring forming process. More particularly, in the aluminum metal wiring forming process of a semiconductor device, cleaning is performed before forming a protective film on the entire surface of the aluminum metal wiring. Unlike the prior art, by performing the cleaning after the protective film is formed, it is possible to effectively remove the defects generated in the aluminum metal wiring forming process.
현재 반도체 소자 제조공정 중에, Al 금속 배선을 형성하기 위하여 Al 층을 식각한 후에 잔류하는 PR, 유기물질 및 무기성 잔류물 등을 제거하기 위해서는 일반 RCA 세정액을 사용한다. 과산화수소를 근간으로 한 RCA 세정은 세정 화학액 내에서 과산화수소가 산화제의 역할을 하여 오염물뿐만 아니라 금속층의 표면도 산화시키기 때문에 금속층을 보호하기 위한 유기성 세정제를 함께 사용하게 된다. 이러한 유기성 세정액은 아민 계열의 PR 용해제와 금속 보호층을 형성하기 위한 억제제 (inhibitor)가 포함되어 있다. 그러나 금속층에 이러한 유기성 세정제를 사용하게 되면 세정 장비의 공정 순서상 유기성 물질을 완전히 제거하기가 어렵다. 이러한 문제로 인하여 웨이퍼 상의 잔류 아민 성분은 초순수와 반응하여 수산화이온 (OH-)이 생성되고, 이 수산화이온은 Al과 반응하여 Al(OH)4 -가 되어 Al 부식으로 이어진다. Al 층의 부식 부위는 후속 공정인 보호막 (SiON) 증착후에 디펙트 (defect)가 생성되게 하는데 이러한 디펙트가 성장하면 금속 브리지 (metal bridge) 및 단락 (short fail)을 유발하여 소자의 전기적 특성을 악화시킨다 (도 1a 및 도 1b 참조). 이러한 디펙트는 특히 400℃ O2/N2공정 분위기에서 성장하게된다.In the current semiconductor device manufacturing process, a general RCA cleaning solution is used to remove the PR, organic substances and inorganic residues remaining after etching the Al layer to form the Al metal wiring. RCA cleaning based on hydrogen peroxide is used together with an organic detergent to protect the metal layer because hydrogen peroxide acts as an oxidant in the cleaning chemical to oxidize not only contaminants but also the surface of the metal layer. The organic cleaning solution includes an amine-based PR solubilizer and an inhibitor for forming a metal protective layer. However, the use of such an organic cleaner in the metal layer makes it difficult to completely remove the organic material in the process sequence of the cleaning equipment. Due to this problem, the residual amine component on the wafer reacts with ultrapure water to produce hydroxide ions (OH − ), which react with Al to form Al (OH) 4 − , leading to Al corrosion. Corrosion of the Al layer causes defects to be produced after the subsequent deposition of a protective film (SiON), which can lead to metal bridges and short fail, resulting in electrical properties of the device. Worsen (see FIGS. 1A and 1B). These defects are especially grown in a 400 ° C. O 2 / N 2 process atmosphere.
이러한 디펙트를 제거하기 위하여 지금까지는 주로 세정 장비의 부분 조정 (parts tuning)과 공정 순서 등을 조절하여 디펙트 발생을 최소화시키고 있다. 그러나 이러한 조치에 의하여 디펙트의 발생을 저감시키는데는 한계가 있고, 초순수 접촉으로 인한 금속층 어택 (attack)과 디펙트의 발생을 완벽하게 제거할 수 없는 상황으로서 이러한 디펙트 발생은 반도체 공정에서 가장 중요한 수율 저하의 원인 중의 하나이다.To eliminate such defects, until now, the occurrence of defects has been minimized mainly by adjusting parts tuning and process sequence of cleaning equipment. However, there is a limit in reducing the occurrence of defects due to such measures, and it is impossible to completely eliminate the occurrence of metal layer attack and defects due to ultrapure water contact. It is one of the causes of the yield decline.
이러한 디펙트 발생을 제거하기 위하여, 금속 세정 후에 BOE 식각액 (etchant)에 의해 추가 세정을 함으로써 금속 표면을 약하게 식각 (slightly etching)하여 디펙트의 원인 (defect source)을 제거하는 방법이 사용되었으나, 이 방법은 Al 등의 금속에 어택이 가해져서 프로파일 (profile)이 손상될 수 있다. 따라서, 이 방법을 사용하기 위해서는 희석 BOE 용액에 따른 금속의 식각 속도 테스트를 충분히 수행한 후에 실시하여야 하는 번거로움이 있다.In order to eliminate the occurrence of such defects, a method of removing the defect source by lightly etching the metal surface by further cleaning with a BOE etchant after metal cleaning has been used. The method can attack the metals such as Al and damage the profile. Therefore, this method is cumbersome to be performed after a sufficient test of the etching rate of the metal according to the diluted BOE solution.
본 발명의 목적은 알루미늄 금속배선 형성 공정에서 발생하는 디펙트를 제거하기 위한 방법을 제공하는 것이다.It is an object of the present invention to provide a method for removing defects occurring in an aluminum metallization forming process.
도 1a는 종래의 알루미늄 금속배선 형성공정에서 디펙트가 발생한 형태를 나타내는 단면도.1A is a cross-sectional view showing a form in which defects occur in a conventional aluminum metal wiring forming process.
도 1b는 상기 도 1a에서 발생한 디펙트의 SEM 사진.Figure 1b is a SEM image of the defect occurred in Figure 1a.
도 2a는 본 발명의 공정에서 BOE 세정공정 전에 디펙트가 발생한 형태를 나타내는 단면도.Figure 2a is a cross-sectional view showing a form in which defects occurred before the BOE cleaning step in the process of the present invention.
도 2b는 상기 도 2a의 디펙트를 BOE 세정공정으로 제거한 상태를 나타낸 단면도.Figure 2b is a cross-sectional view showing a state in which the defect of Figure 2a removed by a BOE cleaning process.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
100 : 반도체 기판102 : 절연막100 semiconductor substrate 102 insulating film
104 : Ti 막106 : Al 막104: Ti film 106: Al film
108 : Ti/TiN 막110, 111, 112 : 보호막108: Ti / TiN film 110, 111, 112: protective film
116 : 디펙트116: Defect
상기 목적을 달성하기 위하여 본 발명에서는 반도체 소자의 알루미늄 금속배선 형성과정에서, 알루미늄 금속배선 전면에 보호막을 형성하기 전에 세정을 수행했던 종래의 기술과 달리, 보호막 형성 후에 세정을 수행하는 것에 특징이 있는 반도체 소자의 금속배선 형성방법을 제공한다.In order to achieve the above object, in the present invention, in the process of forming the aluminum metal wiring of the semiconductor device, unlike the conventional technique in which the cleaning is performed before forming the protective film on the entire surface of the aluminum metal wiring, the cleaning is performed after the protective film is formed. Provided is a method of forming metal wirings in a semiconductor device.
본 발명에서는 우선, 하기와 같은 단계를 포함하는 반도체 소자의 금속배선 형성방법을 제공한다:First, the present invention provides a method for forming a metal wiring of a semiconductor device comprising the following steps:
(a) 반도체 기판 상부에 절연막을 증착하는 단계와,(a) depositing an insulating film on the semiconductor substrate;
(b) 상기 절연막 상에 알루미늄 금속 배선을 형성하는 단계와,(b) forming an aluminum metal wiring on the insulating film;
(c) 상기 구조 전표면에 보호막을 형성하는 단계와,(c) forming a protective film on the entire surface of the structure;
(d) 상기 결과물을 BOE 용액으로 세정하는 단계와,(d) washing the resultant with BOE solution,
(e) 상기 결과물 상에 절연막을 형성하는 단계.(e) forming an insulating film on the resultant product.
상기 알루미늄 금속 배선은 알루미늄과 기타 배리어 메탈 (barrier metal)의 적층구조이고, Ti, Al 및 Ti/TiN의 적층구조로 이루어진 것이 바람직하다.The aluminum metal wiring is a laminate structure of aluminum and other barrier metals, and preferably, a laminate structure of Ti, Al, and Ti / TiN.
상기 (a) 단계의 절연막은 LP-TEOS 막인 것이 바람직하고, 상기 (c) 단계의 보호막은 N2/O2, 350∼450℃ 분위기에서 증착 가능한 막이면 무엇이든 가능하며, SiON 막인 것이 바람직하다. 이때 보호막은 900∼1100Å 두께로 도포되는 것이 바람직하다.Preferably, the insulating film of step (a) is an LP-TEOS film, and the protective film of step (c) may be any film capable of being deposited in an atmosphere of N 2 / O 2 , 350 to 450 ° C., and preferably a SiON film. . At this time, the protective film is preferably applied to a thickness of 900 ~ 1100Å.
상기 BOE 용액은 NH4F : HF의 부피비가 250∼350 : 1, 바람직하게는 300 : 1인 것을 사용할 수 있다.As the BOE solution, a volume ratio of NH 4 F: HF is 250 to 350: 1, preferably 300: 1 can be used.
상기 세정 단계는 스핀 타입 챔버 (spin type chamber) 또는 침지 타입 배스 (dip type bath)에서 수행될 수 있으며, 상온에서 1∼4분 동안, 바람직하게는 80초∼120초 동안 수행하는 것이 바람직하다.The cleaning step may be performed in a spin type chamber or a dip type bath, and is preferably performed at room temperature for 1 to 4 minutes, preferably 80 seconds to 120 seconds.
또한, 상기 (e) 단계의 절연막은 HSQ (hydrogen silsesquioxane) 막인 것이 바람직하다.In addition, the insulating film of the step (e) is preferably a HSQ (hydrogen silsesquioxane) film.
상기 공정에서 SiON과 같은 보호막은, 후속 공정 즉, HSQ와 같은 절연막 증착후에 HSQ로부터 발생된 수분이 금속 배선으로 흘러 들어가 영향을 미치는 것을 방지하는 역할을 하는 것으로, 실질적으로 디펙트 (116)가 발생하고 성장하는 것은 보호막 (111) 증착 후이다 (도 2a 참조). 본 발명에서는 도 2a와 같은 구조를 BOE 용액으로 세정하여, 보호막 (111) 두께의 20% 정도를 에칭함으로써 디펙트 시드 (defect seed)를 제거하는 것이다. 따라서 본 발명의 세정단계를 거치면, 디펙트 (116)는 제거되고, 보호막 (112)의 두께가 도 2a의 보호막 (111) 보다 20% 정도 감소된다 (도 2b 참조).In the above process, the protective film such as SiON serves to prevent the moisture generated from the HSQ from flowing into and affecting the metal wiring after the subsequent process, that is, the deposition of the insulating film such as HSQ, so that the defect 116 is substantially generated. And growing are after deposition of the protective film 111 (see FIG. 2A). In the present invention, the structure as shown in FIG. 2A is cleaned with a BOE solution to remove defect seeds by etching about 20% of the thickness of the protective film 111. Therefore, through the cleaning step of the present invention, the defect 116 is removed, the thickness of the protective film 112 is reduced by about 20% than the protective film 111 of Figure 2a (see Figure 2b).
[실시예]EXAMPLE
반도체 기판 상부에 LPTEOS 막, Ti 막, Al 막, Ti/TiN 막을 차례로 적층시키고, 상기 구조 전표면에 보호막으로 SiON을 1000Å의 두께로 도포하였다. SiON 도포는 250 sccm 유량의 SiH4/ 3500 sccm 유량의 NH3/ 3000 sccm 유량의 N2O / 1500 sccm 유량의 N2가스들을 혼합하여 400℃ 온도에서 상기 웨이퍼에 분사하여 행해졌다.An LPTEOS film, a Ti film, an Al film, and a Ti / TiN film were sequentially stacked on the semiconductor substrate, and SiON was applied to the entire surface of the structure as a protective film at a thickness of 1000 mW. SiON coating was performed by spraying the wafer at 400 ℃ temperature by mixing the N 2 gas of N 2 O / 1500 sccm flow rate of the NH 3/3000 sccm flow rate of the SiH 4/3500 sccm flow rate of 250 sccm flow rate.
상기 SiON이 도포된 결과물을 NH4F : HF의 부피비가 300 : 1 인 BOE 용액을 사용하여 80초 동안 침지시키면 약 133Å이 에칭되어 100Å/min의 에칭 속도를 가짐을 확인하였다.When the resultant coated with SiON was immersed for 80 seconds using a BOE solution having a volume ratio of NH 4 F: HF of 300: 1, about 133 Pa was etched to have an etching rate of 100 Pa / min.
에칭 속도를 확인한 후, SiON 증착 두께인 1000Å중 200Å을 제거하기 위하여, 상기 300 : 1의 BOE 용액을 사용하여 스핀 타입 챔버 (스핀 속도 800 rpm)에서 120초 동안 세정하였다. 그런 다음, 스핀 속도 1000 rpm으로 탈이온수를 이용하여 30초 동안 헹구고, N2가스를 스핀 속도 2000 rpm에서 45초 동안 흘려주어 디펙트 시드를 완전히 제거할 수 있었다.After confirming the etching rate, in order to remove 200 kPa in the SiON deposition thickness of 1000 kPa, the BOE solution of 300: 1 was used for 120 seconds in a spin type chamber (spin speed 800 rpm). Then, rinse for 30 seconds with deionized water at a spin speed of 1000 rpm, and N 2 gas was flowed at a spin speed of 2000 rpm for 45 seconds to completely remove the defect seed.
이상에서 살펴본 바와 같이, 본 발명에서는 알루미늄 금속 배선 형성 공정에서, 보호막을 증착한 다음 세정공정을 수행하여 디펙트의 원인을 근본적으로 제거함으로써 알루미늄 금속배선 형성 공정에서 발생하는 디펙트를 효과적으로 제거할 수 있었다.As described above, in the present invention, in the aluminum metal wiring forming process, the protective film is deposited and then the cleaning process is performed to fundamentally eliminate the cause of the defect, thereby effectively removing the defects generated in the aluminum metal wiring forming process. there was.
Claims (11)
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| KR1020020073660A KR20040045801A (en) | 2002-11-25 | 2002-11-25 | Manufacturing method for metal line of semiconductor device |
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| KR20040045801A true KR20040045801A (en) | 2004-06-02 |
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| KR1020020073660A KR20040045801A (en) | 2002-11-25 | 2002-11-25 | Manufacturing method for metal line of semiconductor device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05308074A (en) * | 1991-02-15 | 1993-11-19 | Matsushita Electric Ind Co Ltd | Formation of metal wiring |
| JPH09213703A (en) * | 1996-02-05 | 1997-08-15 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JP2000232096A (en) * | 1999-02-12 | 2000-08-22 | Yamaha Corp | Method for forming wiring |
| KR20010056992A (en) * | 1999-12-17 | 2001-07-04 | 박종섭 | Method for manufacturing inter-dielectric layer in semiconductor device |
-
2002
- 2002-11-25 KR KR1020020073660A patent/KR20040045801A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05308074A (en) * | 1991-02-15 | 1993-11-19 | Matsushita Electric Ind Co Ltd | Formation of metal wiring |
| JPH09213703A (en) * | 1996-02-05 | 1997-08-15 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JP2000232096A (en) * | 1999-02-12 | 2000-08-22 | Yamaha Corp | Method for forming wiring |
| KR20010056992A (en) * | 1999-12-17 | 2001-07-04 | 박종섭 | Method for manufacturing inter-dielectric layer in semiconductor device |
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