KR20040045697A - Chip stack package using insulation wire - Google Patents

Abstract

PURPOSE: A chip stack package using an insulation wire is provided to be capable of improving working efficiency and preventing the electrical contact between wires, or the wire and a semiconductor chip. CONSTITUTION: A chip stack package is provided with a board(31) having a circuit pattern(32), a bottom chip(34) attached on the board by using the first adhesive(33), the first insulation wire(37) for electrically connecting the bonding pad(34a) of the bottom chip with the circuit pattern of the board, and a top chip(36) attached on the bottom chip by using the second adhesive(35). The chip stack package further includes the second insulation wire for electrically connecting the bonding pad(36a) of the top chip with the circuit pattern of the board, an encapsulating part(38) for selectively enclosing the resultant structure, and a plurality of solder balls(39) attached on the lower surface of the board for being electrically connected with the outer circuit.

Description

Chip stack package using insulation wire}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip stack package, and more particularly, to a chip stack package which prevents short circuits between wires or wires and chips due to wire sweeping during a molding process while increasing work efficiency.

As the performance of electrical / electronic products is advanced, many technologies for mounting a larger number of packages on a limited size substrate have been proposed and studied. However, since the package is based on one chip mounted, there is a limit to capacity increase.

Here, as a method of increasing the capacity of the memory chip, that is, high integration, a technique of manufacturing a larger number of cells in a limited space is generally known. However, such a method requires a high level of process technology and a lot of development time, such as requiring a precise fine line width. Therefore, a stacking technology has been developed as a method of achieving high integration more easily, and researches on this are being actively conducted.

Stacking as used in the semiconductor industry is a technique of stacking at least two or more semiconductor chips to double the memory capacity. According to such a stacking technology, two 64M DRAM chips can be stacked to form a 128M DRAM class, and two 128M DRAM chips can be stacked to be 256M DRAM class. In addition, the stacking technique has advantages in terms of mounting density and efficiency of mounting area use.

The stacking method of the two semiconductor chips includes a method of embedding two stacked chips in one package and a method of stacking two packaged packages. In terms of efficiency, two chips are embedded in one package. The chip stack package is better.

1 is a cross-sectional view showing an example of the chip stack package described above.

As shown, the center pad type bottom chip 4 includes a circuit pattern 2 in a face down type in which a pad formation surface faces downward, and a substrate having holes corresponding to the pad formation portion. The top chip 6 of the center pad type, which is attached to the top surface 1 by an adhesive 3 on the bottom surface, is a face up type in which a pad forming surface faces upwards, and a lower surface of the bottom chip 4. It is attached by the adhesive agent 5 on it.

In addition, the bonding pad 4a of the bottom chip 4 and the circuit pattern 2 of the substrate 1 are electrically connected to each other by a metal wire 7 through a hole. The bonding pad 6a and the circuit pattern 2 of the substrate 1 are also electrically connected by the metal wire 7.

The top surface of the substrate 1 including the bottom chip 4, the top chip 6, and the metal wire 7 and the holes of the substrate 1 are sealed with an encapsulant 8, and the substrate ( The lower surface of 1) has a solder ball 9 electrically connected to an external circuit.

However, the above-mentioned conventional stack chip package is inferior in workability at the time of its manufacture because the bottom chip and the top chip are disposed in the face down type and the face up type, respectively, and therefore, the equipment investment cost is high. That is, different equipment must be used when attaching each chip, and additionally, one heater block and one clamp are required for wire bonding, thereby increasing the equipment investment cost.

In addition, in the above-described conventional stack chip package, wire sweeping may occur during the molding process, so that contact between wires or between wires and chips may occur, which leads to electrical leakage, resulting in deterioration of product quality. This phenomenon is expected to be more serious as the pitch between bonding pads in each chip becomes finer.

2 is a photograph showing a state in which contact between the chip and the wire occurs by the wire sweeping during molding.

As can be seen, it can be seen that the wire 12 is in contact with the edge of the chip 11, and therefore electrical leakage is expected to occur.

Accordingly, the present invention has been made to solve the above problems, to provide a chip stack package to prevent electrical contact between the wires or the wire and the chip due to the wire sweeping during molding while improving the work efficiency. There is a purpose.

1 is a cross-sectional view showing a conventional chip stack package.

2 is a photograph showing a state in which contact between the chip and the wire occurs.

3 is a cross-sectional view illustrating a chip stack package according to an embodiment of the present invention.

4 shows an insulated wire according to the invention.

5a to 5e are manufacturing process diagrams of the chip stack package according to the present invention.

6 and 7 are cross-sectional views illustrating chip stack packages according to other embodiments of the present invention.

Explanation of symbols on the main parts of the drawings

31 substrate 32 circuit pattern

33,35: adhesive 34: bottom chip

34a, 36a: bonding pad 36: top chip

37: insulated wire 37a: conductive metal

37b: insulator 38: encapsulant

39: solder ball 40: mount stage

50: mount head 60: anisotropic conductive film

In order to achieve the above object, the present invention is a substrate having a circuit pattern; A bottom chip attached to the substrate in a face up type by a first adhesive; A first insulating wire electrically connecting the bonding pad of the bottom chip and the circuit pattern of the substrate; A top chip attached to the bottom chip including the first insulating wire in a face up type by a second adhesive; A second insulating wire electrically connecting between the bonding pad of the top chip and the circuit pattern of the substrate; An encapsulant for sealing an upper surface of the substrate including the bottom chip, the top chip, and the first and second insulating wires; And a solder ball attached to a lower surface of the substrate and electrically connected to an external circuit.

Here, the bottom chip and the top chip may be applicable to both a center pad type or an edge pad type chip.

The first and second insulating wires have a structure in which a conductive metal is wrapped with an insulator, and the conductive metal is any one of gold, copper, or nickel, and the insulator is polyimide or polyurethane.

According to the present invention, by making the electrical connection between the chip and the substrate with an insulated wire, the bottom chip can be arranged in a face-up type, thereby improving work efficiency, and furthermore, the electrical contact between the wire or the wire and the chip during molding. It can prevent occurrence.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a chip stack package according to an exemplary embodiment of the present invention.

As shown, the chip stack package of the present invention has a structure in which the center chip type bottom chip 34 and the top chip 36 are stacked on the substrate 31 in a face up type as compared with the conventional one.

In addition, the bonding pads 34a and 36a of each chip 24 and 26 and the circuit pattern 32 of the substrate 21 are connected by an insulated wire 37. That is, the electrical connection between the bonding pads 34a and 36a and the circuit pattern 32 is not made of a typical metal wire, but as shown in FIG. 4, the conductive metal 37a such as gold, copper, nickel, and the like is polyimide. And an insulated wire 37 wrapped with an insulator 37b such as polyurethane.

More specifically, in the chip stack package of the present invention, the bottom chip 24 is attached by the adhesive 33 on the substrate 31 having the circuit pattern 32 in the face up type with the pad formation surface facing upward. The top chip 36 is also attached on the bottom chip 34 by the adhesive 35 in a face up type with a pad forming surface facing upward. In addition, the bonding pads 34a and 36a of the bottom chip 34 and the top chip 36 are electrically connected to the circuit pattern 32 of the substrate 31 by the insulating wire 37. In addition, the top surface of the substrate 31 including the bottom chip 34, the top chip 36, and the insulating wire 37 is sealed with the encapsulant 38 through a molding process. In addition, a solder ball 39 is attached to the lower surface of the substrate 31, which is electrically connected to an external circuit, that is, functions as a mounting means.

In the chip stack package of the present invention, since the electrical connection between the bonding pads of each chip and the substrate circuit pattern is made on the insulated wire, even during wire sweeping, even if wire sweeping occurs, the electrical contact between the wires or between the wires and the chips is performed. Does not occur.

In addition, in relation to the electrical connection between the bonding pad and the circuit pattern made by the insulated wire, even if the bottom chip is attached in the face up type, the thickness of the electrically insulated adhesive adhered to the pad forming surface of the bottom chip is sufficient. In the case of thickening, attachment of the top chip onto such a bottom chip can be easily achieved.

As a result, the chip stack package of the present invention has an advantage over the conventional one in terms of work efficiency because both the bottom chip and the top chip are disposed in the face-up type, and due to the wire sweeping during molding according to the use of the insulated wire. The occurrence of electrical leakage can also be effectively prevented.

Meanwhile, although not described in detail, the insulation wire may be manufactured in a form in which the conductive metal is covered by the insulator, and may also be manufactured by dispersing the insulator after formation of the conductive metal wire.

Hereinafter, a brief description of a manufacturing process of the chip stack package according to an embodiment of the present invention described above.

5A through 5E are cross-sectional views illustrating a chip stack package manufacturing process according to an exemplary embodiment of the present invention. Here, the whole processes are preferably carried out in strip units, not individual chips, but are not shown.

First, as shown in FIG. 5A, the electrically insulated adhesive 33 is applied onto the substrate 31 in a state where the substrate 31 having the circuit pattern 32 is placed on the mount stage 40. Then, a center pad-shaped bottom chip 34 is disposed on the adhesive 33 so that the pad forming surface faces upward, and then the heat and pressure of the mount head 40 are used on the substrate 31. The bottom chip 34 is attached.

Next, as shown in FIG. 5B, an insulating wire 37 having a structure in which a conductive metal is wrapped with an insulator is disposed between the circuit pattern 32 of the substrate 31 and the bonding pad 34a of the bottom chip 34. Electrically connected

Subsequently, as shown in FIG. 5C, again on the bottom chip 34 including the insulation wire 37, the insulation wire 37 is electrically insulated again to a sufficient thickness such that the insulation wire 37 is not pressed by the top chip. Apply the adhesive (35).

Subsequently, as shown in FIG. 5D, the center pad type top chip 36 is disposed on the adhesive 35 so that the pad forming surface faces upward, and then the heat and pressure of the mount head (not shown) are removed. The top chip 36 is attached onto the bottom chip 34 by using the same. Then, the bonding pads 36a of the top chip 36 and the circuit pattern 32 of the substrate 31 are interconnected using the insulating wire 37.

Then, as shown in FIG. 5E, the top surface of the substrate 31 including the bottom chip 34 and the top chip 36 and the insulating wire 37 is sealed with the encapsulant 38 through a molding process. . At this time, as described above, even if wire sweeping occurs with respect to the application of the insulating wire, electrical contact between the wires or the wire and the chip does not occur. A post molding cure process is then performed that heats at high temperatures to aid in stress relief and further chemical reaction to the molding material.

Subsequently, although not shown, the solder balls are attached to the lower surface of the substrate, followed by a reflow and flux cleaning process, and then the chip stack packages manufactured in strip units are individually By cutting, the chip stack package of the present invention as shown in FIG. 3 is completed.

6 to 8 are cross-sectional views illustrating chip stack packages according to other embodiments of the present invention. Here, only the parts different from the chip stack package according to the embodiment of the present invention will be described.

6 is a cross-sectional view of an example in which an edge pad type chip is used as a bottom chip and not a center pad type type.

FIG. 7 is a cross-sectional view of an example in which a bottom chip is bonded in a face-down type on a substrate by an anisotropic conductive film (hereinafter referred to as an ACF) and electrically connected to a circuit pattern of the substrate.

According to this embodiment, although the bottom chip 34 is disposed in the face down type while the top chip 36 is disposed in the face up type, the equipment investment cost may be increased, but the attachment of the bottom chip 34 is performed. And since the electrical connection is made by the ACF 60, the equipment investment costs are not substantially increased.

On the other hand, although not shown, the insulated wire can be applied in the manufacture of a typical thin small outline package (TSOP), even in this case, no electrical contact between wires or wires and chips by wire sweeping during molding.

As described above, according to the present invention, the bottom pad and the top chip can be disposed in a face-up type by forming an insulating wire between the bonding pads of the chip and the circuit pattern of the substrate by an insulated wire wrapped by an insulator. As a result, the efficiency of the work can be improved and the cost of equipment investment can be prevented.

In addition, the present invention can prevent the electrical contact between the wires or the wire and the chip by the wire sweeping in the subsequent molding process by applying the insulated wire, so that the electrical leakage can be prevented to obtain the production yield and the quality improvement Can be.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (4)

A substrate having a circuit pattern; A bottom chip attached to the substrate in a face up type by a first adhesive; A first insulating wire electrically connecting the bonding pad of the bottom chip and the circuit pattern of the substrate; A top chip attached to the bottom chip including the first insulating wire in a face up type by a second adhesive; A second insulating wire electrically connecting the bonding pad of the top chip to a circuit pattern of the substrate; An encapsulant for sealing an upper surface of the substrate including the bottom chip, the top chip, and the first and second insulating wires; And And a solder ball attached to the lower surface of the substrate and electrically connected to an external circuit. The chip stack package of claim 1, wherein the bottom chip and the top chip are center pad type or edge pad type chips. The chip stack package of claim 1, wherein the first and second insulating wires have a structure in which a conductive metal is surrounded by an insulator. The chip stack package of claim 1, wherein the conductive metal is any one selected from the group consisting of gold, copper, and nickel, and the insulator is polyimide or polyurethane.