KR20040043737A - Method for measuring thickness of insulator using edge of wafer - Google Patents
Method for measuring thickness of insulator using edge of wafer Download PDFInfo
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- KR20040043737A KR20040043737A KR1020020072028A KR20020072028A KR20040043737A KR 20040043737 A KR20040043737 A KR 20040043737A KR 1020020072028 A KR1020020072028 A KR 1020020072028A KR 20020072028 A KR20020072028 A KR 20020072028A KR 20040043737 A KR20040043737 A KR 20040043737A
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- wafer
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- insulating film
- thickness measurement
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000012212 insulator Substances 0.000 title 1
- 239000002184 metal Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 238000005259 measurement Methods 0.000 claims description 12
- 238000011065 in-situ storage Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 53
- 239000010410 layer Substances 0.000 description 21
- 238000005498 polishing Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
본 발명은 반도체웨이퍼의 가장자리를 이용한 절연막두께의 측정방법에 관한 것으로, 보다 상세하게는 절연막 CMP공정시 웨이퍼에서 이용되지 않는 에지부분을 이용하여 인-시튜(in-situ)로 CMP공정 전후의 절연막 두께를 측정하는 반도체웨이퍼의 가장자리를 이용한 절연막두께의 측정방법에 관한 것이다.The present invention relates to a method for measuring the thickness of an insulating film using an edge of a semiconductor wafer, and more particularly, an insulating film before and after a CMP process in-situ using an edge portion not used in a wafer during the insulating film CMP process. A method of measuring the thickness of an insulating film using the edge of a semiconductor wafer for measuring the thickness.
종래의 반도체소자의 제조방법에 대해 도 1a 내지 도 1d를 참조하여 설명하면 다음과 같다.A method of manufacturing a conventional semiconductor device will be described below with reference to FIGS. 1A to 1D.
도 1a 내지 도 1d는 일반적인 다이 크기에 따른 웨이퍼상 칩 개수 및 오픈면적을 도시한 도면으로서, 도 1a는 다이크기가 20×20mm인 경우 칩갯수가 52개이고 오픈면적이 27.9%인 것을 도시한 것이고, 도 1b는 다이크기가 20×10mm인 경우 칩갯수가 114개이고 오픈면적이 20.9%인 것을 도시한 것이고, 도 1c는 다이크기가 10×20mm인 경우 칩갯수가 116개이고 오픈면적이 19.5%인 것을 도시한 것이며, 도 1d는 다이크기가 10×10mm인 경우 칩갯수가 250개이고 오픈면적이 13.3%인 것을 도시한 것이다.1A to 1D show the number of chips on a wafer and the open area according to a typical die size, and FIG. 1A shows that the number of chips is 52 and the open area is 27.9% when the die size is 20 × 20 mm. 1B shows that the number of chips is 114 and the open area is 20.9% when the die size is 20 × 10 mm, and FIG. 1C is the number of chips is 116 and the open area is 19.5% when the die size is 10 × 20mm. Figure 1d shows that when the die size is 10 × 10mm the number of chips is 250 and the open area is 13.3%.
도 1a 내지 도 1d에 도시된 바와 같이, 웨이퍼상에서 이용되지 않는 부분(즉, 에지부분)의 면적(5)에서는, 웨이퍼를 플랫존이 없는 원형 평판으로 가정하여 포토리소그래피 공정 가운데 웨이퍼 에지부분의 포토레지스트가 제거된 EBR (Edge Bead Removal)영역은 제외하였다.As shown in Figs. 1A-1D, in the area 5 of the portion (i.e., the edge portion) not used on the wafer, the photo of the wafer edge portion in the photolithography process is assumed assuming that the wafer is a circular flat plate without a flat zone. The EBR (Edge Bead Removal) region from which the resist was removed was excluded.
이러한 계산 결과 다이 크기가 감소함에 따라 웨이퍼 에지부분(5)의 면적이 급격히 감소하지만, 10×10 mm 내지 20×20 mm의 다이 크기에서 13∼28% 이상의 웨이퍼가 웨이퍼상에서 이용되지 않고 있음을 알 수 있다.These calculations show that as the die size decreases, the area of the wafer edge portion 5 decreases drastically, but at least 13 to 28% of the wafers are not used on the wafer at die sizes of 10 × 10 mm to 20 × 20 mm. Can be.
또한, 실제 공정에서는 금속배선 식각공정 및 화학기계적 연마공정 (CMP : Chemical Mechanical Polishing)을 위해 더미패턴을 다이내에 포함시키고 있으므로 오픈면적(5)은 최소한 15%이상이 된다.In addition, since the dummy pattern is included in the die for the metallization etching process and the chemical mechanical polishing (CMP) process, the open area 5 is at least 15%.
일반적으로 웨이퍼 패턴의 절연막 CMP공정에서는, CMP공정 전에 두께 측정기로 금속층 위의 절연막 두께를 측정하고 CMP공정의 예상 연마시간을 CMP장비에 입력한 후 웨이퍼샘플 1매의 CMP공정을 진행한다.In general, in the insulating film CMP process of the wafer pattern, the thickness of the insulating film on the metal layer is measured by the thickness measuring device before the CMP process, the expected polishing time of the CMP process is input to the CMP apparatus, and the wafer sample is subjected to the CMP process.
상기 웨이퍼샘플 1매의 CMP공정 완료후 다시 두께측정기로 금속층 위의 절연막 두께를 측정하고 CMP공정의 최종 연마시간을 결정하여 이를 기초로 나머지 웨이퍼에도 CMP공정을 진행한다.After the CMP process of one wafer sample is completed, the thickness of the insulating layer on the metal layer is measured by a thickness gauge again, and the final polishing time of the CMP process is determined. Based on this, the CMP process is performed on the remaining wafers.
이러한 종래기술에 따른 웨이퍼의 절연막 두께 측정방식은 매 층마다 두께측정기에 웨이퍼패턴을 인식시키고 웨이퍼패턴의 측정위치를 명시해야 하는 문제가 있었다.The insulation film thickness measurement method of the wafer according to the related art has a problem in that the wafer pattern is recognized by the thickness meter for each layer and the measurement position of the wafer pattern is specified.
또한, 익스-시튜(ex-situ)로 웨이퍼 샘플의 절연막 두께를 측정한 후 상기웨이퍼 샘플의 연마시간을 나머지 웨이퍼에도 피드백해줘야 하기 때문에 CMP공정 시간이 많이 걸린다는 문제점이 있었다.In addition, since the thickness of the insulating film of the wafer sample is measured ex-situ, the polishing time of the wafer sample should be fed back to the remaining wafers.
따라서, 본 발명은 상기 종래기술의 제반문제점을 해결하기 위하여 안출한 것으로서, 매 층마다 웨이퍼패턴을 측정장비에 인식시키지 않고도 다이맵을 이용하여 측정위치를 명시할 수 있으므로 CMP공정 시간을 줄일 수 있 반도체웨이퍼의 가장자리를 이용한 절연막두께의 측정방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, it is possible to reduce the CMP process time because it is possible to specify the measurement position by using a die map without recognizing the wafer pattern in each measuring device. It is an object of the present invention to provide a method for measuring the thickness of an insulating film using an edge of a semiconductor wafer.
또한, 본 발명의 또 다른 목적은 웨이퍼에서 이용되지 않는 웨이퍼 에지부분에서 인-시튜(in-situ)로 절연막 두께를 측정하고, 곧 바로 연마시간을 피드백할 수 있어 공정상의 불편함을 해소할 수 있는 반도체웨이퍼의 가장자리를 이용한 절연막두께의 측정방법을 제공하는 것이다.In addition, another object of the present invention is to measure the thickness of the insulating film in-situ in the wafer edge portion that is not used in the wafer, and can immediately feed back the polishing time to solve the process inconvenience. The present invention provides a method for measuring the thickness of an insulating film using the edge of a semiconductor wafer.
도 1a 내지 도 1d는 종래기술에 따른 다이 크기에 따른 웨이퍼상 칩 개수 및 오픈면적을 도시한 도면.1A-1D show the number of chips on a wafer and the open area according to die size according to the prior art;
도 2a는 본 발명에 따른 금속배선식각 전 웨이퍼상의 감광막상태를 도시한 도면.Figure 2a is a view showing a state of the photosensitive film on the wafer before etching the metal wiring in accordance with the present invention.
도 2b은 본 발명에 따른 금속배선식각 후 웨이퍼 상태를 도시한 도면.Figure 2b is a view showing a wafer state after etching the metal wiring in accordance with the present invention.
도 2c는 본 발명에 따른 웨이퍼상의 금속패턴 위에 절연막을 덮은 상태를 도시한 도면.2C is a view showing a state where an insulating film is covered on a metal pattern on a wafer according to the present invention.
도 3은 본 발명에 따른 CMP장비의 플래튼을 도시한 평면도.Figure 3 is a plan view showing a platen of the CMP apparatus according to the present invention.
도 4는 본 발명에 따른 두께측정기 및 플랫 존 센서를 구비한 플래튼을 도시한 단면도.4 is a cross-sectional view of a platen having a thickness gauge and a flat zone sensor according to the present invention;
(도면의 주요부분에 대한 부호설명)(Code description of main parts of drawing)
100 : 웨이퍼120 : 금속층100 wafer 120 metal layer
120a : 중심부분의 금속패턴120b : 에지부분의 금속패턴120a: metal pattern of the center portion 120b: metal pattern of the edge portion
160 : 에지부분180 : 절연막160: edge portion 180: insulating film
300 : 플래튼320 : 두께측정기용 윈도우300: platen 320: window for thickness measurement
340 : 플랫존센서용 윈도우400 : 두께측정기340: Window for flat zone sensor 400: Thickness gauge
420 : 플랫존 센서440 : 헤드420: flat zone sensor 440: head
상기 목적을 달성하기 위한 본 발명은, 웨이퍼상에 금속층을 형성하고 감광막을 도포한 후, 상기 웨이퍼의 칩 형성부분에 있는 감광막부분만 현상하고 상기 웨이퍼의 가장자리부에 있는 감광막부분은 현상하지 않도록 하는 단계; 상기 금속층을 선택적으로 식각하여 상기 칩 형성부분에 금속배선을 형성하고 상기 가장자리부에 더미 금속배선을 형성하는 단계; 상기 결과물의 상부에 절연막을 형성하는 단계; 상기 절연막에 평탄화공정을 진행함과 동시에 상기 웨이퍼의 가장자리부에 있는 더미 금속배선상에 위치한 절연막두께를 측정하는 단계; 및 상기 평탄화공정의 소요시간을 평탄화 장비에 피드백하는 단계를 포함하여 구성됨을 특징으로 한다.According to the present invention for achieving the above object, after forming a metal layer on the wafer and applying a photoresist film, only the photoresist film portion in the chip forming portion of the wafer is developed and the photoresist portion at the edge of the wafer is not developed. step; Selectively etching the metal layer to form metal wiring on the chip forming portion and forming dummy metal wiring on the edge portion; Forming an insulating film on top of the resultant product; Performing a planarization process on the insulating film and measuring an insulating film thickness on a dummy metal wiring at an edge of the wafer; And feeding back the time required for the planarization process to the planarization equipment.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a는 본 발명에 따른 금속배선식각 전 웨이퍼상의 감광막도포상태를 도시한 도면으로서, 도 2a에 도시된 바와 같이 웨이퍼(100)상에 금속층(120)을 형성한 후 감광막을 도포한다.FIG. 2A is a view illustrating a photoresist coating state on a wafer before etching a metal wire according to the present invention. As shown in FIG. 2A, a photoresist film is coated after the metal layer 120 is formed on the wafer 100.
그 다음, 현상공정을 수행하면서 웨이퍼 에지부분의 감광막(160)은 현상하지 않고, 웨이퍼 중심부분의 감광막(140)만을 현상한다.Then, the photosensitive film 160 of the wafer edge portion is not developed while the developing process is performed, and only the photosensitive film 140 of the center portion of the wafer is developed.
즉, 종래의 방법과는 달리, 감광막을 형성한 후 웨이퍼의 에지부분(160)은 현상을 하지 않은 채로 방치하고 웨이퍼에서 직접적으로 이용되는 부분(140)만을 현상한다.That is, unlike the conventional method, after forming the photosensitive film, the edge portion 160 of the wafer is left undeveloped and only the portion 140 directly used in the wafer is developed.
도 2b는 금속배선식각 후의 웨이퍼 상태를 도시한 도면으로서, 도 2b에 도시된 바와 같이 상기 감광막 패턴대로 웨이퍼(100)상의 금속층(120)을 식각하여 웨이퍼 중심부분에서는 금속패턴(120a)을 그리고 그 에지부분에서는 더미 금속패턴(120b)을 형성한다.FIG. 2B is a view showing a wafer state after etching the metal wiring. As shown in FIG. 2B, the metal layer 120 on the wafer 100 is etched according to the photoresist pattern, and the metal pattern 120a is drawn at the center of the wafer. In the edge portion, a dummy metal pattern 120b is formed.
즉, 웨이퍼의 에지부분(160)은 식각되지 않아 와이드한 금속층(120b)이 그대로 남게 되고 그 이외의 패터닝된 부분(140)은 정상적으로 식각되어 금속배선(120a)을 형성하게 된다.That is, the edge portion 160 of the wafer is not etched so that the wide metal layer 120b is left as it is, and the other patterned portion 140 is normally etched to form the metal wiring 120a.
도 2c는 웨이퍼상의 금속패턴 위에 절연막을 덮은 상태를 도시한 도면으로서, 도 2c에 도시된 바와 같이 금속배선 식각공정 후 웨이퍼상의 금속패턴(120a) 및 더미 금속패턴(120b) 위에 절연막(180)을 형성한다.FIG. 2C is a diagram illustrating a state where an insulating film is covered on a metal pattern on a wafer. As shown in FIG. 2C, an insulating film 180 is formed on the metal pattern 120a and the dummy metal pattern 120b on the wafer after the metallization etching process. Form.
이어서, 상기 절연막(180)에 대해 CMP공정을 진행하여 절연막(180)의 단차를 제거한다. 여기서, 상기 CMP공정은 액티브영역 위에서 절연막 두께를 측정하는 층간절연막 (ILD : InterLayer Dielectric) CMP공정으로 진행할 수 있으며, 또는 금속층 위에서 절연막 두께를 측정하는 층간절연막 (IMD : InterMetal Dielectric) CMP공정으로 진행할 수 있다.Subsequently, a CMP process is performed on the insulating layer 180 to remove the step of the insulating layer 180. The CMP process may be performed by an interlayer dielectric (ILD: CMP) process for measuring the thickness of an insulating layer on the active region, or may be performed by an intermetal dielectric (IMD: C) process that measures the thickness of an insulating layer on a metal layer. have.
이러한 CMP공정 진행시, 금속층 크기가 수천 ㎛되는 부분인 웨이퍼 에지부분의 금속층(120b)에서 인-시튜(in-situ)로 절연막(180) 두께를 측정한 후 이러한 두께측정결과로 산출된 연마시간을 곧 바로 자동으로 CMP장비에 피드백하여 나머지 웨이퍼패턴을 측정하는데 이용한다. 이때, 상기 절연막 두께측정시 상기 절연막은 습식 또는 건식상태로 두께를 측정한다.During the CMP process, the polishing time calculated as a result of the thickness measurement after measuring the thickness of the insulating layer 180 in-situ in the metal layer 120b at the edge portion of the wafer where the size of the metal layer is several thousand μm. Is automatically fed back to the CMP machine to measure the remaining wafer pattern. In this case, when the thickness of the insulating film is measured, the thickness of the insulating film is measured in a wet or dry state.
이러한 방식에 의하면, 매 층마다 웨이퍼패턴을 측정장비에 인식시키지 않고도 다이맵을 이용하여 측정위치를 명시할 수 있으므로 CMP공정 시간을 줄일 수 있다.According to this method, the CMP process time can be reduced because the measurement position can be specified by using a die map without recognizing the wafer pattern in each layer.
도 3은 본 발명에 따른 CMP 장비의 플래튼을 도시한 평면도이며, 도 4는 두께측정기 및 플랫존센서를 구비한 플래튼을 도시한 단면도이다.3 is a plan view showing a platen of the CMP apparatus according to the present invention, Figure 4 is a cross-sectional view showing a platen having a thickness gauge and a flat zone sensor.
도 3 및 도 4에 도시된 바와 같이, 플래튼(300)에는 두께측정기용 윈도우(320)와 플랫존센서용 윈도우(340)가 개구되어 있다.As shown in FIGS. 3 and 4, the platen 300 has a window 320 for a thickness gauge and a window 340 for a flat zone sensor.
여기서, 플랫존센서(420)는 윈도우(340)를 통해 헤드(440)에 의해 고정된 웨이퍼(100)를 정렬하며, 두께측정기(400)는 또 다른 윈도우(320)를 통해 상기 웨이퍼(100)상의 절연막(180) 두께를 측정한다.Here, the flat zone sensor 420 aligns the wafer 100 fixed by the head 440 through the window 340, the thickness meter 400 is the wafer 100 through another window 320 The thickness of the insulating layer 180 is measured.
상술한 바와 같이, 본 발명은 매 층마다 웨이퍼패턴을 측정장비에 인식시키지 않고도 다이맵을 이용하여 측정위치를 명시할 수 있으므로 CMP공정 시간을 감소할 수 있다는 효과가 있다.As described above, the present invention can reduce the CMP process time since the measurement position can be specified using the die map without recognizing the wafer pattern in each layer.
또한, 실제 웨이퍼에서 이용되지 않는 에지부분을 이용하여 인-시튜(in-situ)로 절연막 두께를 측정하고, 곧 바로 연마시간을 피드백할 수 있어 공정상의 불편함을 해소할 수 있다는 효과가 있다.In addition, the thickness of the insulating film is measured in-situ using an edge portion which is not actually used in the wafer, and the polishing time can be fed back immediately, thereby eliminating the inconvenience of the process.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (8)
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| KR1020020072028A KR20040043737A (en) | 2002-11-19 | 2002-11-19 | Method for measuring thickness of insulator using edge of wafer |
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