JPH0685029A - Test wafer for semiconductor manufacturing device - Google Patents
Test wafer for semiconductor manufacturing deviceInfo
- Publication number
- JPH0685029A JPH0685029A JP23323492A JP23323492A JPH0685029A JP H0685029 A JPH0685029 A JP H0685029A JP 23323492 A JP23323492 A JP 23323492A JP 23323492 A JP23323492 A JP 23323492A JP H0685029 A JPH0685029 A JP H0685029A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor manufacturing
- film
- manufacturing device
- performance
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体製造装置の検査用
ウェーハに関し、特にドライエッチング装置の性能チェ
ックに用いる半導体製造装置の検査用ウェーハに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection wafer for a semiconductor manufacturing apparatus, and more particularly to an inspection wafer for a semiconductor manufacturing apparatus used for checking the performance of a dry etching apparatus.
【０００２】[0002]
【従来の技術】従来の半導体製造装置の検査用ウェーハ
は、シリコンウェーハ上に単一の膜種を成膜したもの、
あるいは、単一の膜種を成膜後、ホトリソグラフィ工程
にて所定の回路パターンを形成したものであった。2. Description of the Related Art Conventional inspection wafers for semiconductor manufacturing equipment are those in which a single film type is formed on a silicon wafer,
Alternatively, after forming a single film type, a predetermined circuit pattern is formed by a photolithography process.
【０００３】[0003]
【発明が解決しようとする課題】従来の半導体製造装置
の検査用ウェーハでは、１枚のシリコンウェーハ上には
一種類の膜、または、パターンしか形成されていなかっ
た。このため、一台の半導体製造装置の基本性能をチェ
ックするためには複数枚のシリコンウェーハを準備し、
それらを順次半導体製造装置で処理を行い、それに応じ
た種々の測定を行っていた。In the conventional inspection wafer of the semiconductor manufacturing apparatus, only one kind of film or pattern was formed on one silicon wafer. Therefore, in order to check the basic performance of one semiconductor manufacturing device, prepare multiple silicon wafers,
These were sequentially processed by a semiconductor manufacturing apparatus, and various measurements were performed accordingly.
【０００４】そのために、半導体製造装置の基本性能の
確認には多大の時間と工数を必要とするという問題点が
あった。Therefore, there has been a problem that it takes a lot of time and man-hours to confirm the basic performance of the semiconductor manufacturing apparatus.
【０００５】本発明の目的は、性能確認時間と作業工数
を低減できる半導体製造装置の検査用ウェーハを提供す
ることにある。An object of the present invention is to provide an inspection wafer for a semiconductor manufacturing apparatus, which can reduce performance confirmation time and work steps.
【０００６】[0006]
【課題を解決するための手段】本発明は、シリコンウェ
ーハと、該シリコンウェーハ上に形成された下層膜と、
該下層膜上に積層形成された上層膜とを有し、かつ、前
記上層膜が前記下層膜より面積が小さい構造となってい
る。The present invention provides a silicon wafer, an underlayer film formed on the silicon wafer,
An upper layer film laminated on the lower layer film, and the upper layer film has a smaller area than the lower layer film.
【０００７】[0007]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【０００８】図１（ａ），（ｂ）は本発明の一実施例を
示す平面図及びその断面図、図２（ａ）〜（ｄ）は図１
（ａ），（ｂ）の実施例の製造方法を説明する工程順に
示した断面図である。1 (a) and 1 (b) are a plan view and a sectional view showing an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are shown in FIG.
FIG. 6A is a cross-sectional view showing the manufacturing method of the embodiment of FIGS.
【０００９】まず、図２（ａ）に示す様に、シリコンウ
ェーハ１上に化学的気相成長法等を用いて酸化膜２を形
成する。次に、図２（ｂ）に示す様に、酸化膜２上にポ
リシリコン膜３を積層形成する。次に、図２（ｃ）に示
す様に、ホトリソグラフィ法を用いてポリシリコン膜３
上にホトレジスト４を形成する。次に、図２（ｄ）に示
すように、ポリシリコン膜３をエッチングすることによ
り、酸化膜２を露出させる。その後、ホトレジスト４を
剥離することにより、図１（ａ），（ｂ）に示した半導
体製造装置の検査用ウェーハが完成する。First, as shown in FIG. 2A, an oxide film 2 is formed on a silicon wafer 1 by a chemical vapor deposition method or the like. Next, as shown in FIG. 2B, a polysilicon film 3 is laminated on the oxide film 2. Next, as shown in FIG. 2C, the polysilicon film 3 is formed by using the photolithography method.
A photoresist 4 is formed on top. Next, as shown in FIG. 2D, the polysilicon film 3 is etched to expose the oxide film 2. After that, the photoresist 4 is peeled off to complete the inspection wafer of the semiconductor manufacturing apparatus shown in FIGS.
【００１０】この方法により得られた半導体製造装置の
検査用ウェーハを半導体製造装置にて処理すると半導体
製造装置の検査用ウェーハ一枚の処理のみでポリシリコ
ン膜３および、酸化膜２のエッチレートおよび選択性の
測定が可能となる。When the inspection wafer of the semiconductor manufacturing apparatus obtained by this method is processed by the semiconductor manufacturing apparatus, the etching rate of the polysilicon film 3 and the oxide film 2 and It is possible to measure the selectivity.
【００１１】[0011]
【発明の効果】以上説明したように本発明は、一枚の半
導体製造装置の検査用ウェーハ上に異種の膜を積層形成
し、かつ、下層膜上に、下層膜より面積の小さい上層膜
をもつ構造とすることにより、半導体製造装置の性能確
認時間の短縮および作業工数を低減できる効果がある。As described above, according to the present invention, different kinds of films are laminated on the inspection wafer of one semiconductor manufacturing apparatus, and the upper layer film having a smaller area than the lower layer film is formed on the lower layer film. By having such a structure, there is an effect that the performance confirmation time of the semiconductor manufacturing apparatus can be shortened and the number of work steps can be reduced.
【図１】本発明の一実施例を示す平面図及びその断面図
である。FIG. 1 is a plan view and a cross-sectional view showing an embodiment of the present invention.
【図２】図１の実施例の製造方法を説明する工程順に示
した断面図である。2A to 2D are cross-sectional views showing the manufacturing method of the embodiment in FIG. 1 in order of steps.
１ シリコンウェーハ ２ 酸化膜 ３ ポリシリコン膜 ４ ホトレジスト 1 Silicon wafer 2 Oxide film 3 Polysilicon film 4 Photoresist
Claims (1)
ハ上に形成された下層膜と、該下層膜上に積層形成され
た上層膜とを有し、かつ、前記上層膜が前記下層膜より
面積が小さい構造となっていることを特徴とする半導体
製造装置の検査用ウェーハ。1. A silicon wafer, a lower layer film formed on the silicon wafer, and an upper layer film laminated on the lower layer film, and the upper layer film has a smaller area than the lower layer film. An inspection wafer for semiconductor manufacturing equipment, which has a structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23323492A JPH0685029A (en) | 1992-09-01 | 1992-09-01 | Test wafer for semiconductor manufacturing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23323492A JPH0685029A (en) | 1992-09-01 | 1992-09-01 | Test wafer for semiconductor manufacturing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0685029A true JPH0685029A (en) | 1994-03-25 |
Family
ID=16951864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23323492A Pending JPH0685029A (en) | 1992-09-01 | 1992-09-01 | Test wafer for semiconductor manufacturing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0685029A (en) |
-
1992
- 1992-09-01 JP JP23323492A patent/JPH0685029A/en active Pending
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19981215 |