KR20040043382A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20040043382A KR20040043382A KR1020020071625A KR20020071625A KR20040043382A KR 20040043382 A KR20040043382 A KR 20040043382A KR 1020020071625 A KR1020020071625 A KR 1020020071625A KR 20020071625 A KR20020071625 A KR 20020071625A KR 20040043382 A KR20040043382 A KR 20040043382A
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 43
- 150000004767 nitrides Chemical class 0.000 claims abstract description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000000203 mixture Substances 0.000 claims abstract 2
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims description 2
- 230000003247 decreasing effect Effects 0.000 abstract description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 34
- 239000010410 layer Substances 0.000 description 21
- 239000007789 gas Substances 0.000 description 17
- 210000002381 plasma Anatomy 0.000 description 6
- 230000000873 masking effect Effects 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
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- Chemical Kinetics & Catalysis (AREA)
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Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게는 포토레지스트에 대한 질화막의 선택비를 증가시켜 질화막 두께의 마진을 확보하여 임계치수 (Critical Dimension)를 개선할 수 있는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of improving a critical dimension by increasing a selectivity of a nitride film to a photoresist to secure a margin of the nitride film thickness. It is about.
일반적으로 로직을 포함한 반도체소자의 제조공정 중 소자분리막 형성공정, 게이트 형성공정, 전하저장전극 콘택홀 형성공정, 전하저장전극 형성공정등의 식각공정에서 질화막 하드마스킹 방식이 이용되고 있다.In general, a nitride film hard masking method is used in an etching process such as a device isolation film forming process, a gate forming process, a charge storage electrode contact hole forming process, and a charge storage electrode forming process.
종래에는 도 1a 내지 도 1c에 도시된 바와 같이, 포토레지스트 마스크(20)를 이용하여 식각타겟층(10)을 패터닝하는 경우 디자인룰이 감소함에 따라 포토레지스트의 선폭과 두께가 줄어들어 포토레지스트의 마진을 확보하는데 어려움이 있엇다.1A to 1C, when the etching target layer 10 is patterned using the photoresist mask 20, the line width and thickness of the photoresist decrease as the design rule decreases, thereby reducing the margin of the photoresist. Difficult to secure.
이러한 포토레지스트의 마진 확보의 어려움을 해결하기 위해, 도 2a 내지 도 2c에 도시된 바와 같이 종래에는 식각타겟층(10)과 포토레지스트 마스크(20) 사이에 증착된 질화막(15)을 마스크로 사용하는 질화막 하드마스킹 방식이 이용되고 있다.In order to solve the difficulty of securing the margin of the photoresist, a nitride film 15 deposited between the etching target layer 10 and the photoresist mask 20 is used as a mask, as shown in FIGS. 2A to 2C. A nitride film hard masking method is used.
도 2a 내지 도 2c는 종래기술에 따른 하드 마스킹방식을 이용한 반도체소자의 제조방법을 도시한 공정별 단면도로서, 웨이퍼(5)상에 식각타겟층(10), 하드마스크 질화막(15) 및 포토레지스트 마스크(20)가 적층된 경우의 식각순서를 도시하고 있다.2A to 2C are cross-sectional views illustrating a method of fabricating a semiconductor device using a hard masking method according to the related art, and include an etching target layer 10, a hard mask nitride film 15, and a photoresist mask on a wafer 5. The etching order in the case where (20) is stacked is shown.
종래의 반도체소자의 식각공정에서 식각후의 패턴크기는 소자의 특성측면에서 매우 중요한데, 이러한 패턴 크기는 식각시 사용하는 혼합가스와 밀접한 관계가 있으며, 이러한 혼합가스하에서는 선택비와 반비례관계에 있다.In the etching process of the conventional semiconductor device, the pattern size after etching is very important in terms of the characteristics of the device, and the pattern size is closely related to the mixed gas used for etching, and is inversely related to the selectivity under the mixed gas.
즉, 하드마스크 질화막의 선택비가 큰 경우에는 포토레지스트 마스크를 이용하여 형성한 패턴크기를 그대로 가져갈 수 있어 패턴 크기가 커지는 반면, 하드마스크 질화막의 선택비가 작은 경우에는 측면 식각특성이 커지기 때문에 패턴 크기가 작아진다.That is, when the selectivity of the hard mask nitride film is large, the pattern size formed by using the photoresist mask can be taken as it is, and the pattern size is increased. Becomes smaller.
이렇게 해서 패턴크기가 작아지면 상대적으로 저항은 커지기 때문에 디바이스 구동시 큰 문제가 되고 있다.In this way, the smaller the pattern size, the larger the resistance, which is a big problem when driving the device.
이러한 식각선택비는 도 1a 내지 도 1c에 도시된 바와 같이 서로 다른 종류의 박막을 동일한 플라즈마 조건하에서 식각할 때 각각의 박막에 대한 식각속도의 상대적인 비를 의미하는데, 다시말하면 A박막에 대한 임의의 플라즈마 조건하에서의 식각속도를 EA라고 하고, 상기 A박막의 플라즈마 조건과 동일한 플라즈마 조건하에서의 B박막에 대한 식각속도를 EB라고 할때 식각선택비는 다음과 같다.As shown in FIGS. 1A to 1C, the etching selectivity refers to a relative ratio of etching rates for each thin film when different kinds of thin films are etched under the same plasma conditions. When the etching rate under the plasma condition is called EA and the etching rate for the B thin film under the same plasma condition as that of the A thin film is EB, the etching selectivity is as follows.
SA / B = EA / EB ---- (1)SA / B = EA / EB ---- (1)
한편, 종래의 포토레지스트의 식각공정은 주로 다음과 같은 반응식에 의해 수행된다.Meanwhile, the etching process of the conventional photoresist is mainly performed by the following reaction formula.
C + O2→ CO2, C + O → CO, H2+ ½O2→ H2O ---- (2)C + O 2 → CO 2 , C + O → CO, H 2 + ½O 2 → H 2 O ---- (2)
또한, 종래의 질화막의 식각공정은 CF4, C2F6, CHF3, NF3및 SF6등의 가스를 이용하며 그 반응식은 다음과 같다.In addition, the conventional nitride film etching process uses gases such as CF 4 , C 2 F 6 , CHF 3 , NF 3 and SF 6 , and the reaction scheme is as follows.
Si3N4+ 12F → 3SiF4+ 2N2----- (3)Si 3 N 4 + 12F → 3SiF 4 + 2N 2 ----- (3)
이때, C2F6,CHF3에 O2를 첨가하면 이방성 식각특성을 얻을 수 있는데, 이는 식각시 C-F계열의 폴리머를 발생시켜 이방성 식각 프로파일을 형성하기 때문이다.In this case, when O 2 is added to C 2 F 6 and CHF 3 , anisotropic etching characteristics may be obtained, because an anisotropic etching profile is formed by generating a CF-based polymer during etching.
그러나, 플루오르를 기초로 한 플라즈마는 강한 로딩(loading)효과를 나타낸다.However, fluorine-based plasmas exhibit a strong loading effect.
이러한 하드마스크 질화막의 식각시 종래의 혼합가스(CH2F2를 포함)를 사용하면 하드마스크 질화막의 선택비가 낮아 임계치수가 낮아지고 이로 인해 다시 저항이 증가되는 문제점이 있다.When the conventional mixed gas (including CH 2 F 2 ) is used to etch the hard mask nitride film, the selectivity of the hard mask nitride film is low, thereby lowering the critical dimension, thereby increasing resistance.
이로써 메모리 또는 로직 디바이스의 전극 또는 배선의 저항이 커지게 되면 독출 및 라이트시 문제가 발생되며, 더 나아가 디바이스에 결함이 발생하여 디바이스의 고유기능을 상실하게 된다는 문제점이 있다.As a result, when the resistance of the electrode or the wiring of the memory or the logic device increases, a problem occurs during reading and writing, and furthermore, a problem occurs in the device, which causes the device to lose its unique function.
따라서, 본 발명은 상기 종래기술의 제반문제점을 해결하기 위하여 안출한것으로서, 하드마스크 질화막의 식각시 임계치수가 낮아지는 것을 방지하여 전극 또는 배선 저항이 증가하는 것을 방지할 수 있을 뿐만 아니라 소자의 개발비용을 줄일 수 있는 반도체소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, it is possible to prevent the increase in the electrode or wiring resistance by preventing the threshold dimension during the etching of the hard mask nitride film as well as the development cost of the device It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can reduce the number.
도 1a 내지 도 1c는 종래기술에 따른 반도체소자의 제조방법을 도시한 공정별 단면도.1A to 1C are cross-sectional views illustrating processes of manufacturing a semiconductor device according to the related art.
도 2a 내지 도 2c는 종래기술에 따른 또 다른 하드 마스킹방식을 이용한 반도체소자의 제조방법을 도시한 공정별 단면도.2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device using another hard masking method according to the related art.
도 3a 내지 도 3d는 본 발명에 따른 혼합가스의 각 성분에 따른 식각률과 선택비 차이를 도시한 그래프.3a to 3d are graphs showing the difference in etching rate and selectivity according to each component of the mixed gas according to the present invention.
도 4a 내지 도 4b는 본 발명에 따른 선택비별 인-라인 임계치수를 도시한 SEM 사진.4A to 4B are SEM photographs showing in-line critical dimensions according to selection ratios according to the present invention.
도 5a 내지 도 5d는 본 발명에 따른 선택비 및 위치별 아웃-라인 절단면을 도시한 SEM 사진.Figures 5a to 5d is a SEM photograph showing the selectivity and position-specific cut out section according to the present invention.
도 6a 및 도 6b는 본 발명에 따른 하드마스킹 방식을 이용한 반도체소자의 제조방법을 도시한 공정별 단면도.6A and 6B are cross-sectional views illustrating a method of manufacturing a semiconductor device using a hard masking method according to the present invention.
(도면의 주요부분에 대한 부호설명)(Code description of main parts of drawing)
50 : 반도체기판100, 100a : 패드산화막50: semiconductor substrate 100, 100a: pad oxide film
150, 150a : 질화막200, 200a : MTO산화막150, 150a: nitride film 200, 200a: MTO oxide film
250, 250a : 산질화막300 : 포토레지스트250, 250a: oxynitride film 300: photoresist
상기 목적을 달성하기 위한 본 발명은, 반도체기판상에 하부물질층과 하드마스크 물질층을 차례로 형성하는 단계; 상기 하드마스크 물질층상에 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴 대로 CF4, CHF3, O2및 Ar의 혼합가스하에서 상기 하드마스크 물질층을 식각하는 단계; 및 상기 식각된 하드마스크 물질층을 마스크로 하여 상기 하부물질층을 식각하는 단계를 포함하여 구성됨을 특징으로 한다.The present invention for achieving the above object, the step of sequentially forming a lower material layer and a hard mask material layer on the semiconductor substrate; Forming a photoresist pattern on the hardmask material layer; Etching the hard mask material layer under a mixed gas of CF 4 , CHF 3 , O 2, and Ar according to the photoresist pattern; And etching the lower material layer by using the etched hard mask material layer as a mask.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3d는 본 발명에 따른 혼합가스의 각 성분에 따른 식각률과 선택비 차이를 도시한 그래프로서, 도 3a는 CF4가스성분에 따른 하드마스크 질화막의 식각률과 선택비를, 도 3b는 CHF3가스성분에 따른 하드마스크 질화막의 식각률과 선택비를, 도 3c는 O2가스성분에 따른 하드마스크 질화막의 식각률과 선택비를, 그리고 도 3d는 Ar가스성분에 따른 하드마스크 질화막의 식각률과 선택비를 도시하고있다.3A to 3D are graphs showing the difference in etching rate and selectivity according to each component of the mixed gas according to the present invention, and FIG. 3A is an etching rate and selectivity of the hard mask nitride film according to CF 4 gas component, and FIG. Etch rate and selectivity of the hard mask nitride film according to the CHF 3 gas component, Figure 3c shows the etch rate and selectivity of the hard mask nitride film according to the O 2 gas component, and Figure 3d shows the etching rate and selectivity of the hard mask nitride film according to the Ar gas component The selection costs are shown.
먼저, 도 3a에 도시된 바와 같이 하드마스크 질화막(SiN)은 CF4가스에 의해 다음과 같은 반응식으로 식각된다. 여기서, 상기 하드마스크 질화막은 산질화막(SiON) 또는 산화막(SiO2)일 수 있으며, 이를 단일막 또는 복합막으로 형성할 수도 있다.First, as shown in FIG. 3A, the hard mask nitride layer SiN is etched by the CF 4 gas in the following scheme. The hard mask nitride layer may be an oxynitride layer (SiON) or an oxide layer (SiO 2), and may be formed as a single layer or a composite layer.
SiN4+ 3CF4→ 3SiF4+ 2N2+ 3C ---- (4)SiN 4 + 3CF 4 → 3SiF 4 + 2N 2 + 3C ---- (4)
상기 식에서 발생하는 3C는 O2와 반응하여 CO2또는 CO를 형성하게 되고, 이는 휘발성이므로 잘 날아간다.3C generated in the above formula reacts with O 2 to form CO 2 or CO, which is volatile and thus flies well.
결과적으로 CF4를 증가시키면 상기 반응이 활성화된다.As a result, increasing CF 4 activates the reaction.
또한, 도 3b에 도시된 바와 같이 CHF3유량을 증가시킨 경우 하드마스크 질화막의 식각률이 증가하는 반면, 포토레지스트의 경우는 폴리머의 증착으로 인해 식각률이 급격하게 감소한다.In addition, as shown in FIG. 3B, when the flow rate of CHF 3 is increased, the etching rate of the hard mask nitride film is increased, whereas in the case of photoresist, the etching rate is drastically decreased due to deposition of a polymer.
또한, 도 3c에 도시된 바와 같이 상기 반응식(2)에 의해 O2유량이 증가하면 포토레지스트의 식각률이 증가하는 반면, 상기 하드마스크 질화막의 식각률은 감소한다.In addition, as shown in FIG. 3C, when the flow rate of O 2 is increased by the reaction formula (2), the etching rate of the photoresist is increased while the etching rate of the hard mask nitride film is decreased.
한편, 도 3d에 도시된 바와 같이, 물리적인 측면에서 보면 Ar을 증가시킬 경우 플라즈마 밀도의 증가로 인해 스퍼터링 수율이 증가하게 되고 이런 이유로 식각률도 증가하게 되는데 반해, 화학적인 측면에서 보면 Ar을 증가시킬 경우 화학적인 희석효과로 식각률이 감소한다.On the other hand, as shown in Fig. 3d, in the physical aspect, if the Ar is increased, the sputtering yield is increased due to the increase in the plasma density, and for this reason, the etching rate is also increased, whereas in the chemical aspect, the Ar is increased. In this case, the etching rate decreases due to the chemical dilution effect.
도 4a 내지 도 4b는 본 발명에 따른 선택비별 인-라인 임계치수를 도시한 SEM 사진으로서, 도 4a는 낮은 선택비에서의 인-라인 임계치수를, 그리고 도 4b는 높은 선택비에서의 인-라인 임계치수를 도시하고 있다.4A to 4B are SEM photographs showing in-line thresholds for selection ratios according to the present invention, FIG. 4A for in-line thresholds at low selection ratios, and FIG. 4B for in-line thresholds at high selection ratios. Line thresholds are shown.
도 5a 내지 도 5d는 본 발명에 따른 선택비 및 위치별 아웃-라인 절단면을 도시한 SEM 사진으로서, 도 5a는 낮은 선택비와 웨이퍼중심에서의 아웃-라인 절단면을, 그리고 도 5b는 높은 선택비와 웨이퍼중심에서의 아웃-라인 절단면을, 도 5c는 낮은 선택비와 웨이퍼 가장자리에서의 아웃-라인 절단면을, 그리고 도 5d는 높은 선택비와 웨이퍼 가장자리에서의 아웃-라인 절단면을 도시하고 있다.Figures 5a to 5d are SEM images showing the selectivity and position-specific out-line cross section according to the present invention, Figure 5a is a low selectivity and an out-line cut surface at the wafer center, Figure 5b is a high selectivity And out-line cutaway at the wafer center, FIG. 5C shows low selectivity and out-line cutaway at the wafer edge, and FIG. 5D shows high selectivity and out-line cutaway at the wafer edge.
도 4 및 도 5에 도시된 바와 같이, 하드마스크 질화막의 식각시 CF4, CHF3, O2및 Ar의 혼합가스를 이용하는 경우 식각률의 차이가 유발되고 이는 다시 하드마스크 질화막의 선택비 증가의 원인이 되는데, 이를 이용하면 임계치수가 낮아지는 것을 방지할 수 있다.As shown in FIGS. 4 and 5, when a mixed gas of CF 4 , CHF 3 , O 2 and Ar is used to etch the hard mask nitride layer, a difference in etching rate is induced, which in turn causes an increase in the selectivity of the hard mask nitride layer. This can be used to prevent the lowering of the critical dimension.
이때, 상기 하드마스크 질화막은 건식식각으로 식각할 수 있으며, 상기 건식식각은 플라즈마 소스에 따른 플라나 타입, RIE(Reactive Ion Etching), 또는 MERIE(Magnetically Enhanced RIE)을 이용한다.In this case, the hard mask nitride layer may be etched by dry etching, and the dry etching may use a planar type, a reactive ion etching (RIE), or a magnetically enhanced RIE (MERIE) according to a plasma source.
또한, 상기 건식식각은 CF4, CHF3, O2및 Ar의 혼합가스에 N2, He, C2F6및 CO의 가스를 한가지 이상 혼합하여 사용할 수 있다.In addition, the dry etching may be used by mixing at least one gas of N 2 , He, C 2 F 6 and CO to a mixed gas of CF 4 , CHF 3 , O 2 and Ar.
결과적으로, 본 발명에 따른 혼합가스하에서는 포토레지스트와 질화막 하드마스크 사이에 식각률의 차이가 유발되어 하드마스크 질화막의 선택비가 증가하여 임계치수가 커지게 되고, 저항은 임계치수에 반비례하여 작아지게 된다.As a result, in the mixed gas according to the present invention, the difference in etching rate is caused between the photoresist and the nitride film hard mask, so that the selectivity of the hard mask nitride film is increased to increase the critical dimension, and the resistance is reduced in inverse proportion to the critical dimension.
한편, 도 6a 및 도 6b에 도시된 본 발명의 다른 실시예에서는 하드마스크 질화막을 이용한 모든 식각공정에 적용하여 포토레지스트 마스크의 마진을 확보할 수 있다. 이를 간략히 설명하면 다음과 같다.Meanwhile, in another embodiment of the present invention illustrated in FIGS. 6A and 6B, the margin of the photoresist mask may be secured by applying to all etching processes using the hard mask nitride layer. Briefly described as follows.
먼저, 도 6a에 도시된 바와 같이 반도체기판(50)상에 패드산화막(100), 하드마스크 질화막(150), MTO(Medium Temperature Oxide)산화막(200), SiON(250)을 차례로 형성한 후 그 결과물의 상부에 포토레지스트(300)를 패터닝하여 형성한다.First, as shown in FIG. 6A, the pad oxide film 100, the hard mask nitride film 150, the MTO (Medium Temperature Oxide) oxide film 200, and the SiON 250 are sequentially formed on the semiconductor substrate 50. It is formed by patterning the photoresist 300 on top of the resultant.
그 다음, 도 6b에 도시된 바와 같이 상기 패터닝된 포토레지스트(300)를 마스크로 하여 CF4, CHF3, O2및 Ar의 혼합가스하에서 반도체기판(50)의 상면이 노출될 때 까지 식각한다.Next, as shown in FIG. 6B, the patterned photoresist 300 is used as a mask and etched until the upper surface of the semiconductor substrate 50 is exposed under a mixed gas of CF 4 , CHF 3 , O 2, and Ar. .
이로써, 측면식각이 전혀 없이 포토레지스트의 패턴크기 대로 패드산화막(100a), 하드마스크 질화막(150a), MTO(Medium Temperature Oxide)산화막(200a) 및 SiON(250a)가 형성된다.As a result, the pad oxide film 100a, the hard mask nitride film 150a, the MTO (Medium Temperature Oxide) oxide film 200a, and the SiON 250a are formed according to the pattern size of the photoresist without any side etching.
여기서, 상기 하드마스크 질화막의 식각후 상기 포토레지스트를(300) 제거함이 없이 상기 식각타겟층을 식각하거나 또는 상기 포토레지스트(300)를 제거한 후 상기 식각타겟층을 식각할 수도 있다.Here, the etching target layer may be etched without removing the photoresist 300 after the hard mask nitride layer is etched, or the etching target layer may be etched after removing the photoresist 300.
결과적으로, 포토레지스트의 패턴크기 대로 식각되어 포토레지스트의 마진이확보된다.As a result, the photoresist is etched according to the pattern size, thereby securing a margin of the photoresist.
상술한 바와 같이, 본 발명은 하드마스크 질화막 식각시 포토레지스트와 하드마스크 질화막사이에 하드마스크 질화막의 선택비를 증가시켜 임계치수가 증가하게 되고 이로써 포토레지스트의 마진을 확보할 수 있다는 효과가 있다.As described above, the present invention increases the selectivity of the hard mask nitride film between the photoresist and the hard mask nitride film during the etching of the hard mask nitride film, thereby increasing the critical dimension, thereby securing a margin of the photoresist.
또한, 패턴의 크기 및 프로파일등을 조절할 수 있는 데이타를 확보함으로써 모든 질화막 식각공정에 적용하여 소자의 개발비용을 줄일 수 있다는 효과가 있다.In addition, it is possible to reduce the development cost of the device by applying to all nitride film etching process by securing data that can control the size and profile of the pattern.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (6)
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