KR20040040125A - Apparatus and method for recovering a sampling clock in ofdm systems - Google Patents

Abstract

PURPOSE: A clock error detector for recovering a sampling clock and an OFDM receiver having the same are provided to recover stably the sampling clock by removing an influence of a channel in a process of estimating a frequency error. CONSTITUTION: A clock error detector for recovering a sampling clock includes an OFDM symbol delay(350), a first complex conjugate multiplier(355), a pilot delay(360), a second complex conjugate multiplier(365), an accumulator(370), a phase calculator(375), and a multiplier(380). The OFDM symbol delay(350) delays an output symbol of an FFT as much as an OFDM symbol. The first complex conjugate multiplier(355) is used for removing the phase distortion of the received symbol due to a multi-path channel. The pilot delay(360) delays an output of the first complex conjugate multiplier as much as α. The second complex conjugate multiplier(365) is used for multiplying the complex conjugate number of the output of the pilot delay by the output of the first complex conjugate multiplier. The accumulator(370) is used for accumulating the outputs of the second complex conjugate multiplier. The phase calculator(375) is used for calculating a phase value of the complex number outputted from the accumulator. The multiplier(380) is used for converting the phase value in radian units to a sampling clock error rate by multiplying the output of the phase calculator by a coefficient.

Description

Apparatus and method for clock error detection for recovering sampling clock, and method thereof, and a receiver thereof including the same device {APPARATUS AND METHOD FOR RECOVERING A SAMPLING CLOCK IN OFDM SYSTEMS}

The present invention relates to an Orthogonal Frequency Division Multiplexing (OFDM) receiver, and in particular, a clock error detecting apparatus and method, which are necessary for stably restoring a sampling clock without being influenced by a channel, and a device comprising the same. To a receiver.

OFDM is a technique of dividing a channel having a given bandwidth into a plurality of subchannels and transmitting signals through subcarriers orthogonal to each other.

Since OFDM is configured to overlap bands between adjacent subchannels using orthogonality of subcarriers, bandwidth efficiency can be maximized compared to frequency division multiplexing (FDM) in the past. It has a very long symbol length compared to the impulse response length, and a guard interval, which has a cyclic repetition characteristic, is added to allow complete elimination of Inter Symbol Interference (ISI). It is suitable for high speed communication system under path channel.

Symbol timing synchronization, carrier frequency synchronization, sampling clock frequency synchronization, and the like are required for synchronization for demodulating OFDM signals, and a method specific to the OFDM method is used for each synchronization method.

1 shows a basic configuration of an apparatus for recovering a sampling clock in an OFDM receiver.

Referring to FIG. 1, an input analog OFDM signal is converted into a digital signal by the ADC unit 100 and input to the FFT unit 200. The FFT unit 200 converts a signal in the time domain into a signal in the frequency domain by performing a fast Fourier transform, and the clock error detector 300 extracts a pilot symbol from the converted signal in the frequency domain to change its phase rotation. Estimate and output sampling clock error rate with.

The loop filter 400 then performs the sampling clock error rate estimation signal ( In order to reduce the influence of noise and to determine the convergence characteristic of the entire sampling clock recovery loop, the output signal of the loop filter unit 400 is fed back to the ADC unit 100 to remove the VCXO or the resampling filter of the ADC unit 100. To adjust the sampling rate.

Meanwhile, a conventional algorithm for implementing the clock error detector 300 extracting a pilot symbol from the sampling clock recovery apparatus shown in FIG. 1 and estimating a sampling clock error rate with a phase rotation change can be described as follows.

First, the symbol on the k-th subcarrier of the i-th OFDM symbol input to the IFFT (Inverse FFT) is transmitted from the transmitter. In this case, the corresponding FFT output of the signal received through the channel is the received symbol of Equation 1 Can be modeled as: The addition noise term is omitted to clarify the development of the equation.

In Equation 1 Is a phase error caused by Common Phase Erroe (CPE) or residual carrier frequency offset, Is the FFT window position offset, N is the FFT length, Is the frequency response of the corresponding subchannel.

If some of the pilot symbols in the frequency domain are located at a certain carrier frequency spacing α, the set of positions is { }, Set { and } By multiplying the complex conjugate of Equation 1 and the delayed equation by α for the pilot symbol corresponding to Equation 2 below. Obtain

On the property of the pilot symbol in Equation 2 Considering 1 does not impair generality.

If the channel change with frequency is small enough, Wow Equation 2 can be approximated to Equation 3 below if it is sufficiently non-numeric.

So set { }About When the sum is calculated to obtain a phase, the following Equation 4 is obtained.

From this, the FFT window position offset of the OFDM symbol can be estimated as shown in Equation 5 below.

In conclusion, an estimate of the sampling clock error rate is obtained by the following equation.

In Equation 6 Is the amount of change in the FFT window position offset during the D OFDM symbol, Is the length of the protective section.

2 illustrates the configuration of the clock error detector 300 based on the algorithm described above.

In FIG. 2, the pilot delay unit 310 receives a received pilot symbol output from the FFT unit 200. Output by delaying by. The complex conjugate multiplier 315 is a delayed pilot symbol output from the pilot delay unit 310 Is complex conjugated and the pilot symbol output from the FFT unit 200 And multiply by The reason for doing this is to remove the phase error caused by the CPE or residual carrier frequency offset, and to obtain the phase rotation according to the FFT window offset.

Meanwhile, the accumulator 320 outputs the complex conjugate multiplier 315 during one OFDM symbol period. ) And the phase calculator 325 calculates and outputs a complex phase value output from the accumulator 320. To the output of the phase calculator 325 By multiplication, the phase difference in radians is converted into an FFT window offset. The variation calculator 335 calculates and outputs a difference between the current FFT window offset and the FFT window offset before the D OFDM symbol. Multiplying the FFT window offset by the sampling clock error rate ( Is converted to).

The clock error detector 300, which is designed based on the above-described algorithm, has a relatively simple structure and has the advantage that the sampling clock frequency synchronization and the symbol timing synchronization can be performed at the same time. This directly leads to distortion in the computation of the algorithm, which also severely limits the choice of α, resulting in a very poor statistical performance for the additive noise, resulting in a significant deterioration in performance at low SNR.

This problem is caused by the subchannel frequency response required by the algorithm. Wow Because α must be chosen as small as possible to satisfy the conditions that must be sufficiently similar to each other, in order to increase the statistical immunity to the additive noise, a contradictory relationship occurs in which α should be selected as large as possible. .

Accordingly, an object of the present invention is to solve the above-described problem in an OFDM receiver, and removes the influence of the channel in estimating the frequency error of the sampling clock, thereby restoring the sampling clock stably and accurately even under extreme frequency selective channels and poor SNR. To provide a clock error detection device and a method thereof,

Another object of the present invention is to provide an OFDM receiver including a clock error detection apparatus capable of restoring a sampling clock stably and accurately.

1 is a block diagram of an apparatus for recovering a sampling clock in a typical OFDM receiver.

2 is a detailed configuration diagram of the clock error detector 300 of FIG. 1.

3 is a detailed block diagram of a clock error detection unit according to an embodiment of the present invention.

4 is a diagram for explaining a distributed pilot structure in the European digital terrestrial TV broadcasting standard.

An OFDM receiver according to an embodiment of the present invention for achieving the above object,

An FFT unit for converting a digital OFDM signal in a time domain into a digital OFDM signal in a frequency domain;

A clock error detector for extracting pilot symbols from the output of the FFT unit to remove phase distortion of a received symbol by a multipath channel and to calculate an estimated sampling clock error rate from a phase rotation change between pilot symbols;

A loop filter for reducing the influence of noise on the estimated sampling clock error rate and determining the convergence characteristic of the entire sampling clock recovery loop;

And an ADC unit for sampling the input analog OFDM signal at an adjusted sampling rate by using a VCXO or a resampling filter according to the output signal of the loop filter unit and outputting the digital OFDM signal.

The clock error detector in the OFDM receiver,

An OFDM symbol delay unit for delaying a symbol output from the FFT unit by D OFDM symbols;

A first complex conjugate multiplier for complex-conjugating a delay symbol output from the OFDM symbol delay unit and multiplying it with a symbol output from the FFT unit to remove phase distortion of a received symbol by a multipath channel;

A pilot delay unit for delaying the output of the first complex conjugate multiplier by α;

A second complex conjugate multiplier that complex conjugates the output of said pilot delay unit and multiplies it with the output of said first complex conjugate multiplier;

An accumulator for accumulating the output of the second complex conjugate multiplier for predetermined pilot symbol positions for one OFDM symbol period;

A phase calculator for calculating a complex phase value output from the accumulator;

And a multiplier for converting a phase value in radians into a sampling clock error rate by multiplying a coefficient by an output of the phase calculator.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

First, a new algorithm of the clock error detection apparatus according to the embodiment of the present invention is described as follows.

In the transmitter, a symbol carried on the k th subcarrier of the i th OFDM symbol input to the IFFT is used. In this case, the corresponding FFT output of the signal received through the channel is the received symbol of Equation 7 Can be modeled as: The addition noise term is omitted to clarify the development of the equation.

In Equation 7 Is a phase error caused by Common Phase Erroe (CPE) or residual carrier frequency offset, Is the FFT window position offset, N is the FFT length, Is the frequency response of the corresponding subchannel.

Here, the following equation (8) can be obtained by multiplying the complex conjugate of the equation (7) by the delay of the D OFDM symbol.

If the channel does not change over time or is slow enough Is almost constant or at least Equation 8 can be approximated by Equation 9 when it is sufficiently similar to Equation 8.

In the frequency domain some pilot symbols are located at some constant carrier frequency spacing α and Wow If you have the same location in, set the location to { }, Set { and } May be converted into the following Equation 10 for the pilot symbol corresponding to}.

Due to the property of the pilot symbol in Equation 10 Considering 1 does not impair generality.

By multiplying the complex conjugate of Equation 10 and the delayed expression by α, Equation 11 Obtain

Referring to Equation 11, it can be seen that a phase having information on the amount of change in the FFT window position offset is not affected by the channel.

So set { }About When the sum is calculated to obtain a phase, the following Equation 12 is obtained.

In Equation 12 Is the amount of change in the FFT window position offset during the D OFDM symbol.

In conclusion, an estimate of the sampling clock error rate is obtained by the following equation (13).

In Equation 13 Is the length of the protective section.

It is shown in FIG. 3 that the clock error detecting apparatus is constructed based on the algorithm described above.

In FIG. 3, the OFDM symbol delay unit 350 receives a received pilot symbol output from the FFT unit 200. Is delayed by D OFDM symbol and output. Where D is the set { } The symbols belonging to Wow It should be decided that all of them are pilot symbols.

The first complex conjugate multiplier 355 is a delayed pilot symbol output from the OFDM symbol delay unit 350 Complex conjugate and pilot symbol output from the FFT unit 200 And multiply by The reason for this is that the phase distortion of the received symbol by the multipath channel, i.e. This is to cancel the effects of the channel by canceling the phase rotation effects of each other by the above process.

Meanwhile, the pilot delay unit 360 is output from the first complex conjugate multiplier 355. Output by delaying by. Where α represents the spacing when some of the pilot symbols are located at a certain carrier frequency spacing in the frequency domain. } And the statistical performance of the clock error detector.

The second complex conjugate multiplier 365 is output from the pilot delay unit 360. Is complex conjugated and is output from the first complex conjugate multiplier 355. And multiply by The reason for doing this is to eliminate the phase error caused by the CPE or residual carrier frequency offset, and to obtain only the degree of phase change due to the change of the FFT window offset.

The accumulator 370 outputs the output of the second complex conjugate multiplier 365 during one OFDM symbol period. ), And the phase calculator 375 calculates and outputs a complex phase value output from the accumulator 370. For reference, the phase calculator 375 uses a CORDIC (Coordinate Rotation DIgital Computer) algorithm or the like. Implementation is possible.

The output of the phase calculator 375 is then counted in a multiplier 380 Multiply by, resulting in a phase value in radians Is converted to).

As compared with the configuration of the clock error detector shown in FIG. 2, the configuration of the clock error detector shown in FIG.

The clock error detection unit according to an embodiment of the present invention performs phase distortion of a reception symbol by a multipath channel through an OFDM symbol delay unit 350 and a first complex conjugate multiplier 355. Since the effects of the channel rotation can be canceled by canceling the phase rotation effects, the sampling clock error rate can be obtained stably and accurately even under extreme frequency selective channels and poor SNR.

As an actual application example of the present invention, the OFDM receiver for the European Digital Terrestrial TV Broadcasting Standard (DVB-T) may be applied to the present invention as follows.

FIG. 4 shows a scattered pilot structure defined in the European digital terrestrial TV broadcasting standard, and a black color indicates a position of a distributed pilot symbol in the corresponding OFDM symbol. Referring to this, the distributed pilot symbols are located at 12 carrier frequency intervals in the frequency domain, and the position pattern is repeated every 4 OFDM symbols.

Therefore, in applying the present invention to recover the sampling clock, a distributed pilot having such characteristics can be used. In this case, D must be a multiple of 4 and α must be a multiple of 12 within the range defined by the European digital terrestrial TV broadcasting standard. It is easy to see.

For reference, in the case of a dynamic multipath channel in which the characteristics of the channel change drastically with time, it is advantageous to select D as small as possible. In general, selecting a value as large as α is advantageous for improving statistical immunity to additive noise. Do.

In addition, the continuous pilot structure of the 8K FFT mode in the European digital terrestrial TV standard has a form in which the continuous pilot structure of the 2K FFT mode is repeated four times in units of 1704 carrier frequency intervals in the frequency domain.

Therefore, in the 8K FFT mode, a continuous pilot having such characteristics can be used in applying the present invention to recover the sampling clock. In this case, D is a natural number and α is a multiple of 1704 within the range defined by the European digital terrestrial TV broadcasting standard. It can be readily seen that it should be determined (1704, 3408, 5112).

As described above, the present invention removes the influence of the channel in the process of estimating the frequency error of the sampling clock in the OFDM receiver, and thus has the effect of restoring the sampling clock stably and accurately under the severe frequency selective channel and the poor SNR.

On the other hand, the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be defined only by the appended claims.

Claims (9)

In the clock error detection apparatus for recovering the sampling clock in the OFDM receiver, An OFDM symbol delay unit for delaying a symbol output from the FFT unit by D OFDM symbols; A first complex conjugate multiplier for complex-conjugating a delay symbol output from the OFDM symbol delay unit and multiplying it with a symbol output from the FFT unit to remove phase distortion of a received symbol by a multipath channel; A pilot delay unit for delaying the output of the first complex conjugate multiplier by α; A second complex conjugate multiplier that complex conjugates the output of said pilot delay unit and multiplies it with the output of said first complex conjugate multiplier; An accumulator for accumulating the output of the second complex conjugate multiplier for predetermined pilot symbol positions for one OFDM symbol period; A phase calculator for calculating a complex phase value output from the accumulator; And a multiplier for converting a phase value in radians into a sampling clock error rate by multiplying a coefficient by an output of the phase calculator. The method according to claim 1, wherein when the pilot symbol has a distributed pilot structure defined in the DVB-T standard, α and D are each selected as one of multiples of 12 and multiples of 4 within a range defined by the DVB-T standard. Clock error detection apparatus, characterized in that determined. The method according to claim 1, wherein when the pilot symbol has a continuous pilot structure of the 8K FFT mode specified in the DVB-T standard, the α is selected and determined to be any one of multiples of 1704 within the range defined by the DVB-T standard. The clock error detection apparatus, characterized in that the selection is determined by any one of natural numbers. An FFT unit for converting a digital OFDM signal in a time domain into a digital OFDM signal in a frequency domain, a loop filter unit for reducing the influence of noise on an estimated sampling clock error rate and determining a convergence characteristic of an entire sampling clock recovery loop, and the loop An OFDM receiver comprising: an ADC unit for sampling an input analog OFDM signal at an adjusted sampling rate using an VCXO or a resampling filter according to an output signal of the filter unit, and outputting the digital OFDM signal as an output; Further comprising a clock error detection unit for extracting the pilot symbol from the output of the FFT unit to remove the phase distortion of the received symbol by the multi-path channel and calculates and outputs the estimated sampling clock error rate from the phase rotation change between the pilot symbols, The clock error detector; An OFDM symbol delay unit for delaying a symbol output from the FFT unit by D OFDM symbols; A first complex conjugate multiplier for complex-conjugating a delay symbol output from the OFDM symbol delay unit and multiplying it with a symbol output from the FFT unit; A pilot delay unit for delaying the output of the first complex conjugate multiplier by α; A second complex conjugate multiplier that complex conjugates the output of said pilot delay unit and multiplies it with the output of said first complex conjugate multiplier; An accumulator for accumulating the output of the second complex conjugate multiplier for predetermined pilot symbol positions for one OFDM symbol period; A phase calculator for calculating a complex phase value output from the accumulator; Coefficient to the phase calculator output And a multiplier for converting a phase value in radians into a sampling clock error rate by multiplying by a multiplier. The method according to claim 4, wherein when the pilot symbol has a distributed pilot structure defined in the DVB-T standard, α and D are each selected as one of multiples of 12 and multiples of 4 within a range defined by the DVB-T standard. OFDM receiver, characterized in that determined. The method according to claim 4, wherein when the pilot symbol has a continuous pilot structure of 8K FFT mode specified in the DVB-T standard, the α is selected and determined to be any one of multiples of 1704 within the range defined by the DVB-T standard, OFDM is selected by any one of natural numbers. A clock error detection method for recovering a sampling clock in an OFDM receiver, a) delaying the FFT output symbol by a D OFDM symbol; b) complex conjugating the delayed symbol and multiplying it by an FFT output symbol to remove phase distortion of the received symbol by the multipath channel; c) delaying the multiplication result by α; d) complex conjugating the result delayed in step c and multiplying it by the result of step b; e) accumulating the results of step d for the location of predetermined pilot symbols for one OFDM symbol period; f) calculating a phase value of the accumulated complex number; g) coefficient to said phase value And converting a phase value in radians into a sampling clock error rate by multiplying by. The method according to claim 7, wherein when the pilot symbol has a distributed pilot structure defined in the DVB-T standard, α and D are each selected to be one of 12 multiples and 4 multiples within the range defined by the DVB-T standard. Clock error detection method, characterized in that determined. The method according to claim 7, wherein when the pilot symbol has a continuous pilot structure of the 8K FFT mode specified in the DVB-T standard, the α is selected and determined to be any one of multiples of 1704 within the range defined by the DVB-T standard. The clock error detection method characterized in that the selection is determined by any one of the natural number.