JP2007151097A - Delay profile analysis circuit and device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a delay profile analysis circuit and device using the same in which a delay profile containing only transmission path characteristics can be generated by adaptively eliminating a noise component contained in a measured signal. <P>SOLUTION: A noise component elimination part 20 of a delay profile analysis circuit 100-1 determines a modulation error ratio from a carrier symbol in which transmission path characteristics are equalized using an SP signal, estimates an S/N equivalent therewith and sets a threshold value. Threshold value processing for eliminating components lower than or equal with the threshold value is then performed on a delay profile determined by performing IFFT on a transmission path response by an IFFT part 41. Namely, a noise component of which an amplitude is lower than or equal with a predetermined threshold is eliminated for a delay profile utilizing characters of the noise component being uniformly distributed on a delay wave and a delay time appearing as a sinc function. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an apparatus for measuring a received signal in digital broadcasting or digital transmission using an OFDM (Orthogonal Frequency Division Multiplexing) system, and in particular, a noise component of a delay profile which is a delay time distribution of an incoming delay wave. The present invention relates to a delay profile analysis circuit that generates and displays a delay profile that includes only transmission path characteristics, and an apparatus using the delay profile analysis circuit.

  FIG. 3 is a block diagram showing a configuration of a conventional delay profile analysis circuit. The delay profile analysis circuit 1 includes a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, a GI removal unit 5, an FFT unit 6, a transmission line response calculation unit 7, and an IFFT unit 8. The frequency converter 2 receives the signal under measurement, converts the signal under measurement into an IF band signal, and outputs an IF signal. The A / D conversion unit 3 receives the IF signal and converts the analog IF signal into a digital IF signal using a sampling clock from a synchronous reproduction unit (not shown). The quadrature demodulator 4 receives a digital IF signal, performs quadrature demodulation on the digital IF signal, and outputs an equivalent baseband signal.

  The GI removal unit 5 receives an equivalent baseband signal, and uses a signal (symbol timing) indicating the symbol period and timing of the OFMD signal from a synchronous reproduction unit (not shown), and a period corresponding to a guard interval (GI: Guard Interval). And a signal having a time length corresponding to an effective symbol period (an OFDM signal in a time domain corresponding to the effective symbol period) is extracted. The FFT unit 6 receives an OFDM signal in the time domain for the effective symbol period, performs FFT (Fast Fourier Transform), and converts it into a carrier symbol that is a frequency domain signal. The transmission path response calculation unit 7 receives a carrier symbol and calculates a transmission path response (transmission path characteristics) from the carrier symbol. The IFFT unit 8 inputs a transmission line response, performs an IFFT (Inverse Fast Fourier Transform) on the transmission line response, and obtains a delay profile. Thus, the delay profile analysis circuit 1 inputs and analyzes the signal under measurement and outputs a delay profile.

  FIG. 4 is a block diagram showing a configuration of the transmission path response calculation unit 7 shown in FIG. The transmission line response calculation unit 7 includes a pilot signal extraction unit 7-1, a pilot signal generation unit 7-2, a division unit 7-3, and an interpolation unit 7-4. Pilot signal extraction section 7-1 receives the carrier symbol converted by FFT section 6 in FIG. 3, and extracts a pilot signal transmitted by a predetermined symbol number and subcarrier. The reference pilot signal generation unit 7-2 generates a reference pilot signal having a predetermined amplitude and phase.

  The division unit 7-3 divides the pilot signal extracted by the pilot signal extraction unit 7-1 by the reference pilot signal generated by the reference pilot signal generation unit 7-2, and outputs the result as a transmission path response. The interpolation unit 7-4 receives the transmission line response from the division unit 7-3 and interpolates the transmission line response between symbols. As described above, the transmission line response calculation unit 7 can calculate the transmission line response using the pilot signal.

  An apparatus using such a delay profile analysis circuit 1 is described in Patent Documents 1 to 3, for example.

JP 2000-115087 A JP 2003-224536 A JP 2003-300131 A

  Usually, the delay profile analysis circuit 1 shown in FIG. 3 obtains the delay time distribution (delay profile) of the delay wave in the transmission path. However, in reality, various noises are added to the signal under measurement input to the delay profile analysis circuit 1 before and after passing through the transmission line. Since this noise component is uniformly distributed on the delay profile, it is not easy to discriminate an actual delay wave from the noise component in the obtained delay profile.

  Therefore, the present invention has been made to solve such a problem, and its purpose is to adaptively remove noise components contained in the signal under measurement and generate a delay profile containing only the transmission path characteristics. It is an object of the present invention to provide a delay profile analyzing circuit and a device using the same.

  The delay profile analysis circuit according to the present invention includes an FFT unit that performs FFT on an input OFDM signal into a carrier symbol in a frequency domain, and a transmission line response calculation unit that calculates a transmission line response from the carrier symbol converted by the FFT unit. An IFFT unit that IFFTs the transmission path response calculated by the transmission path response calculation unit into a delay profile on a time axis; a channel equalization unit that equalizes a channel of the carrier symbol converted by the FFT unit; Noise that sets a threshold based on the equalized carrier symbol equalized by the channel equalization unit, performs threshold processing on the delay profile converted by the IFFT unit, and removes noise components And a component removing unit.

  In the delay profile analysis circuit according to the present invention, the noise component removal unit may detect a known transmission symbol having the smallest Euclidean distance on the signal space with the carrier symbol after equalization by the channel equalization unit. A determination unit that determines an estimated value of an actually transmitted carrier symbol, an estimated value of a transmission carrier symbol that is determined by the determination unit, and an equalized carrier symbol that is equalized by the channel equalization unit An error calculation unit that calculates an error between the modulation unit, and a modulation that calculates a modulation error ratio using all data symbols from the estimated value of the transmission carrier symbol determined by the determination unit and the error calculated by the error calculation unit An error ratio calculation unit, and the S / N of the delay profile is estimated from the modulation error ratio calculated by the modulation error ratio calculation unit; A threshold setting unit for setting, and a threshold processing unit for removing a signal component equal to or lower than the threshold set by the threshold setting unit from the delay profile converted by the IFFT unit. Features.

  In the delay profile analysis circuit according to the present invention, the transmission line response calculation unit generates a pilot signal transmitted by a subcarrier having a predetermined symbol number and subcarrier number from the carrier symbol converted by the FFT unit. A pilot signal extraction unit for extraction, a reference pilot signal generation unit for generating a reference pilot signal having a predetermined amplitude and phase, and a pilot signal extracted by the pilot signal extraction unit by the reference pilot signal generation unit A division unit that divides by the generated reference pilot signal and calculates a transmission line response at a frequency of a subcarrier on which the pilot signal is transmitted.

  In the delay profile analysis circuit according to the present invention, the transmission line response calculation unit generates a pilot signal transmitted by a subcarrier having a predetermined symbol number and subcarrier number from the carrier symbol converted by the FFT unit. A pilot signal extraction unit for extraction, a reference pilot signal generation unit for generating a reference pilot signal having a predetermined amplitude and phase, and a pilot signal extracted by the pilot signal extraction unit by the reference pilot signal generation unit A division unit that divides by the generated reference pilot signal and calculates a transmission line response at a frequency of a subcarrier in which the pilot signal is transmitted; an interpolation unit that performs interpolation of the transmission line response calculated by the division unit; The carrier symbol converted by the FFT unit is interpolated. The known transmission symbol having the smallest Euclidean distance in the signal space between the division unit for performing channel equalization and the carrier symbol after equalization output by the division unit is actually divided by the channel response interpolated by And determining a transmission channel response by dividing the carrier symbol converted by the FFT unit by the estimated value of the transmission carrier symbol determined by the determination unit. And a division unit.

  The delay profile analysis circuit according to the present invention also includes an FFT unit that performs FFT on an input OFDM signal into a carrier symbol in the frequency domain, and a transmission channel response calculation that calculates a transmission channel response from the carrier symbol converted by the FFT unit. A IFFT unit that IFFTs the transmission path response calculated by the transmission path response calculation unit into a delay profile on a time axis, and calculates a minimum value of the signal power of the delay profile converted by the IFFT unit And a noise component removing unit configured to set a threshold value and perform threshold processing to remove a noise component.

  In the delay profile analysis circuit according to the present invention, the noise component removal unit is configured to divide the delay profile converted by the IFFT unit into a plurality of blocks for each delay time and the division unit. For each block of the delay profile, an average signal power calculation unit that calculates an average signal power per unit discrete time of the delay profile; a minimum value calculation unit that calculates a minimum value of the average signal power per unit discrete time for the number of divisions; A multiplication unit that multiplies a minimum value of the average signal power calculated by the minimum value calculation unit by a predetermined constant and outputs it as a threshold value, and a delay profile converted by the IFFT unit. And a threshold value processing unit that removes a signal component less than or equal to the threshold value output by the unit.

  In the delay profile analysis circuit according to the present invention, the noise component removal unit performs weighting moving average processing on the delay profile converted by the IFFT unit, and weighted by the weighting moving average processing unit. For a delay profile that has been subjected to moving average processing, a minimum value calculation unit that calculates the minimum value of the delay profile, and a minimum value of the delay profile calculated by the minimum value calculation unit is multiplied by a predetermined constant. A multiplier that outputs as a threshold, and a threshold processor that removes a signal component that is equal to or lower than the threshold output by the multiplier from the delay profile converted by the IFFT unit. And

  The wraparound canceller according to the present invention filters the received signal to generate a replica signal of the wraparound wave, a subtractor that subtracts the replica signal generated by the adaptive filter from the received signal, and the delay profile. And a delay profile analyzing circuit that generates a filter coefficient for generating a replica signal of a sneak wave, and cancels a sneak wave caused by coupling between transmitting and receiving antennas from the received signal.

  According to the present invention, it is possible to adaptively remove a noise component included in an input OFDM signal and generate a delay profile including only transmission path characteristics.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiment of the present invention includes a first configuration of a delay profile analysis circuit (delay profile analysis circuit / example 1), a second configuration of a delay profile analysis circuit (delay profile analysis circuit / example 2), and a delay profile. Third configuration of analysis circuit (delay profile analysis circuit / example 3), fourth configuration of delay profile analysis circuit (delay profile analysis circuit / example 4), and first configuration of wraparound canceller (wraparound canceller / implementation) Example 1), second configuration of wraparound canceller (wraparound canceller / embodiment 2), third configuration of wraparound canceller (wraparound canceller / embodiment 3), and fourth configuration of wraparound canceller (wraparound canceller / embodiment) The description will be divided into 8). The first wraparound canceller is a device that uses the first delay profile analysis circuit, the second wraparound canceller is a device that uses the second delay profile analysis circuit, and the third and fourth wraparound cancellers are the first one. This is an apparatus using three or four delay profile analysis circuits. The delay profile analysis circuit is characterized in that a threshold value is set by a predetermined process from the carrier symbol of the signal under measurement, and a noise component is removed from the delay profile using the threshold value. The wraparound canceller uses the delay profile analysis circuit to remove a noise component from a wraparound wave replica signal.

[Delay Profile Analysis Circuit / Example 1]
First, a first embodiment of the delay profile analysis circuit will be described. FIG. 1 is a block diagram showing a first configuration of a delay profile analysis circuit according to an embodiment of the present invention. The delay profile analysis circuit 100-1 includes a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, a GI removal unit 5, an FFT unit 6, and a channel equalization unit 10 having a transmission line response calculation unit 30, A noise component removing unit 20 and an IFFT unit 41 are provided. The channel equalization unit 10 includes a transmission path response calculation unit 30 and a division unit 15, and the noise component removal unit 20 includes a determination unit 21, an error calculation unit 22, a modulation error ratio calculation unit 23, a threshold setting unit 24, And a threshold processing unit 25. The transmission path response calculation unit 30 includes an SP signal extraction unit 11, a reference SP signal generation unit 12, a division unit 13, and an interpolation unit 14.

  Comparing the delay profile analysis circuit 100-1 shown in FIG. 1 with the conventional delay profile analysis circuit 1 shown in FIG. 3, the two are the frequency converter 2, the A / D converter 3, the quadrature demodulator 4, the GI. Although it is the same in that the removal unit 5 and the FFT unit 6 are provided in this order, the delay profile analysis circuit 100-1 includes a channel equalization unit 10 having a transmission line response calculation unit 30, a noise component removal unit. 20 and the IFFT unit 41 are different in that they are provided in place of the transmission path response calculation unit 7 and the IFFT unit 8 of the delay profile analysis circuit 1. In the following, in FIG. 1, the same reference numerals as those in FIG.

  In FIG. 1, a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, a GI removal unit 5, and an FFT unit 6 have the same functions as those shown in FIG. Here, the carrier symbols converted by the FFT unit 6 are divided into two, one is a training signal extraction unit in the channel response calculation unit 30 of the channel equalization unit 10 and one is to the division unit 15 of the channel equalization unit 10. Each is input to a certain SP signal extraction unit 11.

  The SP signal extraction unit 11 receives a carrier symbol from the FFT unit 6 and receives an SP (scattered pilot) signal which is a pilot signal transmitted by a subcarrier having a predetermined symbol number and subcarrier number. Extract and output. The reference SP signal generation unit 12 generates an SP signal having a predetermined amplitude and phase and outputs it as a reference SP signal. The division unit 13 inputs the SP signal of the signal under measurement from the SP signal extraction unit 11, receives the reference SP signal from the reference SP signal generation unit 12, divides the SP signal of the signal under measurement by the reference SP signal, and transmits the signal. Calculate and output the road response. The interpolation unit 14 receives the transmission line response from the division unit 1, interpolates transmission line characteristics between symbols, and outputs the result. Here, the transmission path response output by the interpolation unit 14 is divided into two, one being input to the division unit 15 and the other being input to the IFFT unit 41.

  The division unit 15 receives a carrier symbol from the FFT unit 6, receives a transmission line response from the division unit 15, and divides a data symbol of the carrier symbol by a transmission line response in the subcarrier, thereby obtaining a channel or the like. And output. Here, the equalized data symbols output by the dividing unit 15 are divided into two, one being input to the error calculating unit 22 and the other being input to the determining unit 21.

  The determination unit 21 receives the equalized data symbol from the division unit 15, and is a known value having the smallest Euclidean distance in the signal space between the equalized data symbol and the known transmission symbol. The transmission symbol is used as an estimated value of the transmission symbol, and the estimated value of the transmission symbol is output. Details of the noise component removal unit 20 including the determination unit 21, the error calculation unit 22, the modulation error ratio calculation unit 23, the threshold value setting unit 24, and the threshold value processing unit 25 will be described later. Here, the estimated value of the transmission symbol output by the determination unit 21 is divided into two, one being input to the error calculation unit 22 and the other being input to the modulation error ratio calculation unit 23.

  The error calculator 22 receives the equalized data symbol from the divider 15, receives the transmission symbol estimate from the determiner 21, calculates the error between them, and outputs it. The modulation error ratio calculation unit 23 inputs an error between the equalized data symbol and the estimated value of the transmission symbol from the error calculation unit 22, inputs the estimated value of the transmission symbol from the determination unit 21, and all the data Using the symbol, a modulation error ratio (MER) is calculated from the error and the estimated value of the transmission symbol and output. The threshold value setting unit 24 receives the modulation error ratio from the modulation error ratio calculation unit 23, estimates the S / N of the delay profile from the modulation error ratio, sets the threshold value, and outputs it.

  The IFFT unit 41 receives the transmission line response from the interpolation unit 14, performs an IFFT on the transmission line response, converts it into a delay profile, and outputs it. The threshold processing unit 25 receives a delay profile from the IFFT unit 41, inputs a threshold from the threshold setting unit 24, performs threshold processing using the threshold on the delay profile, and performs noise processing. The component is removed, and the delay profile after removal of the noise component is output.

  The operation when the delay profile analysis circuit 100-1 of FIG. 1 configured as described above is applied to terrestrial digital broadcasting of the ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) transmission method is described below.

In the ISDB-T system and the DVB-T (Digital Video Broadcasting-Terrestrial) system, which are broadcasting systems for terrestrial digital television broadcasting, as shown in FIG. 7, a specific subcarrier of a specific symbol is SP as a pilot signal. Assigned to. In FIG. 7, SP is indicated by a black circle, and other carrier symbols such as data symbols are indicated by white circles. Hereinafter, regarding the SP arrangement, the interval in the subcarrier direction in consecutive symbols is N _f , and the interval in the symbol direction in the same subcarrier is N _t . Since the amplitude and phase of the SP are predetermined values, the same signal can be generated on the receiving side (the reference SP signal generation unit 12 of the delay profile analysis circuit 100-1 illustrated in FIG. 1).

を満足する。但し、ｍｏｄは剰余を示す。以下、式（１）を満足するｉ，ｋをそれぞれｉ_ｐ，ｋ_ｐとする。 The SP arrangement is as follows: symbol number i and subcarrier number k

Satisfied. However, mod indicates a remainder. Hereinafter, i and k satisfying the expression (1) are assumed to be i _p and k _p , respectively.

ここでは、パイロット信号としてＩＳＤＢ−Ｔ方式で採用されているＳＰを用いて説明したが、受信側において既知のシンボルであればＳＰでなくても同様に伝送路応答を求めることができる。 In FIG. 1, the SP of the signal under measurement extracted by the SP signal extraction unit 11 is Y (i _p , k _p ), and the reference SP generated by the reference SP signal generation unit 12 is X (i _p , k _p ). Then, for the symbol number i and the subcarrier number k, the transmission path response H (i _p , k _p ) calculated by the division unit 13 is expressed by the following equation.

Here, the SP employed in the ISDB-T system has been described as the pilot signal. However, if the symbol is a known symbol on the receiving side, the transmission path response can be obtained in the same manner even if it is not the SP.

ここで、ｍは遅延プロファイルの離散時間を示す。 The IFFT unit 41 can obtain the delay profile h (i, m) by performing the IFFT on the transmission line response H (i _p , k _p ).

Here, m represents the discrete time of the delay profile.

ここで、Ｄ（ｉ，ｋ）は送信信号を、Ｎ（ｉ，ｋ）は加法性雑音を示す。 Further, when the carrier symbol of the signal under measurement FFTed by the FFT unit 6 is Y (i, k), it is expressed by the following equation.

Here, D (i, k) represents a transmission signal, and N (i, k) represents additive noise.

Therefore, Formula (3) becomes like the following formula.

  As described above, additive noise is added in the delay profile analysis using SP. In general, a delay wave appears as a sinc function on the delay profile, whereas a noise component is uniformly distributed over the delay time. Therefore, the threshold value processing unit 25 of the noise component removing unit 20 uses the property of the delay wave appearing as a sinc function and the noise component uniformly distributed on the delay time, and the amplitude has a predetermined amplitude with respect to the delay profile. Noise components that are components below the threshold are removed. Thereby, it is possible to realize a delay profile analysis circuit capable of adaptively removing a noise component included in a signal under measurement and generating a delay profile including only transmission path characteristics.

[Delay Profile Analysis Circuit / Embodiment 2]
Next, a second embodiment of the delay profile analysis circuit will be described. FIG. 2 is a block diagram showing a second configuration of the delay profile analysis circuit according to the exemplary embodiment of the present invention. The delay profile analysis circuit 100-2 includes a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, a GI removal unit 5, an FFT unit 6, a noise component removal unit 20, and a channel equalization unit 10. A road response calculation unit 30 and an IFFT unit 41 are provided. The transmission path response calculation unit 30 includes a channel equalization unit 10, a determination unit 21, and a division unit 31, and the channel equalization unit 10 includes an SP signal extraction unit 11, a reference SP signal generation unit 12, a division unit 13, and an interpolation. A unit 14 and a division unit 15 are provided. Further, the noise component removal unit 20 includes a determination unit 21, an error calculation unit 22, a modulation error ratio calculation unit 23, a threshold value setting unit 24, and a threshold value processing unit that overlap with a part of the transmission path response calculation unit 30. 25.

  Comparing the delay profile analysis circuit 100-2 shown in FIG. 2 with the delay profile analysis circuit 100-1 shown in FIG. 1, the two are the frequency conversion unit 2, the A / D conversion unit 3, the quadrature demodulation unit 4, and the GI. Although the removal unit 5 and the FFT unit 6 are the same in that they are configured in this order, the configurations of the channel equalization unit 10, the noise component removal unit 20, and the transmission path response calculation unit 30 are different.

  In FIG. 2, the frequency conversion unit 2, the A / D conversion unit 3, the quadrature demodulation unit 4, the GI removal unit 5, and the FFT unit 6 have the same functions as those shown in FIGS. Here, the carrier symbols converted by the FFT unit 6 are divided into three and input to the division unit 15, the SP signal extraction unit 11 that is a training signal extraction unit, and the division unit 31, respectively.

  The SP signal extraction unit 11, the reference SP signal generation unit 12, the division unit 13, the interpolation unit 14, and the division unit 15 have the same functions as those shown in FIG. That is, the SP signal extraction unit 11 extracts an SP signal from the carrier symbol, the reference SP signal generation unit 12 generates a reference SP signal, the division unit 13 calculates a transmission line response, and the interpolation unit 14 calculates the transmission line response. Interpolate. Here, the transmission path response output by the interpolation unit 14 is input to the division unit 15. The division unit 15 calculates the equalized data symbol.

  The determination unit 21, the error calculation unit 22, the modulation error ratio calculation unit 23, and the threshold value setting unit 24 have the same functions as those shown in FIG. That is, the determination unit 21 determines the estimated value of the transmission symbol. Here, the estimated value of the transmission symbol output by the determination unit 21 is divided into three and input to the error calculation unit 22, the modulation error ratio calculation unit 23, and the division unit 31, respectively. The error calculator 22 calculates an error between the equalized data symbol and the estimated value of the transmission symbol. The modulation error ratio calculation unit 23 calculates the modulation error ratio from the error and the estimated value of the transmission symbol using all the data symbols. The threshold setting unit 24 estimates the S / N of the delay profile from the modulation error ratio, and sets the threshold.

  Division unit 31 receives a carrier symbol from FFT unit 6, receives an estimated value of a transmission symbol from determination unit 21, divides the carrier symbol by an estimated value of the transmission symbol, calculates a transmission path response, and outputs it. . The IFFT unit 41 receives the transmission line response from the division unit 31, performs IFFT on the transmission line response, converts it into a delay profile, and outputs it.

  The threshold processing unit 25 has a function equivalent to that shown in FIG. That is, the threshold processing unit 25 performs threshold processing on the delay profile to remove the noise component, and outputs the delay profile after removal of the noise component.

このように、Ｚ（ｉ，ｋ）は、式（６）の第２項により信号点Ｄ（ｉ，ｋ）を中心に分散する。ここで、Ｄ（ｉ，ｋ）は送信信号、Ｎ（ｉ，ｋ）は加法性雑音を示す。 The operation of the delay profile analysis circuit 100-2 of FIG. 2 configured as described above will be described below. The division unit 15 transmits the channel response H (i, k) output from the interpolation unit 14 for the carrier symbols (data symbols) Y (i, k) other than SP among the carrier symbols output by the FFT unit 6. By dividing by, channel equalized data (data symbol after equalization) Z (i, k) is calculated. Assuming that the transmission path response is estimated ideally, Z (i, k) is expressed by the following equation.

Thus, Z (i, k) is distributed around the signal point D (i, k) by the second term of the equation (6). Here, D (i, k) represents a transmission signal, and N (i, k) represents additive noise.

このように、除算部３１は、式（８）により、伝送路応答を算出する。尚、伝送路応答Ｈ（ｉ，ｋ）の算出方法以外は、図１に示した遅延プロファイル解析回路１００−１の第１の構成と同様であるため、説明を省略する。 The determination unit 21 outputs the equalized data symbol Z (i, k) and a known transmission symbol having the shortest Euclidean distance in the signal space as an estimated value of the transmission symbol. The estimated value of the transmission symbol is as shown in Equation (7).

As described above, the division unit 31 calculates the transmission path response according to the equation (8). Except for the method of calculating the transmission line response H (i, k), the description is omitted because it is the same as the first configuration of the delay profile analysis circuit 100-1 shown in FIG.

ここで、δＺ（ｉ，ｋ）は雑音による誤差成分を表している。変調誤差比算出部２３により算出される変調誤差比は、次式で定義される。

[Noise component removal unit]
Next, the noise component removal unit 20 shown in FIGS. 1 and 2 will be described in detail. The equalized data symbol Z (i, k) output from the division unit 15 is expressed as a vector as follows.

Here, δZ (i, k) represents an error component due to noise. The modulation error ratio calculated by the modulation error ratio calculation unit 23 is defined by the following equation.

  The modulation error ratio and C / N are equivalent when the main deterioration factor is Gaussian noise, and are known to have a linear relationship (“ETR290: Measurement guidelines for DVB systems”, ETSI Technical Report). (1997).). That is, the C / N of the signal under measurement can be estimated by obtaining the modulation error ratio.

The S / N average value SNR (dB), which is the noise floor of the delay profile, is represented by N _{c as} the number of subcarriers used to calculate the delay profile, and CNR (dB) as the C / N average value of all subcarriers. Then, it can be expressed by the following formula.

雑音のピークマージンＭは、１０〜２０ｄＢ程度にするとよい。図８に、最も振幅の大きい到来波に対する振幅比が１０ｄＢ、遅延時間１０μｓである遅延波が存在し、また遅延プロファイルの算出に用いた全サブキャリヤの平均のＣ／Ｎが２０ｄＢの場合に、遅延プロファイル解析回路１００−２を用いて求めた遅延プロファイルの例を示す。この例は、ＩＦＦＴ部４１により出力され、雑音成分除去部２０へ入力される遅延プロファイルを示している。また、図９に、雑音成分除去部２０からの出力例であるしきい値以下が除去された遅延プロファイルを示す。 For example, in the delay profile analysis circuit 100-1, in the ISDB-T mode 3, the total number of subcarriers used for calculating the delay profile is 1873, and the S / N of the delay profile is higher than the C / N of the received signal. About 32.7 dB (= ₁₀ log ₁₀ 1873) is observed greatly. In the delay profile analysis circuit 100-2, in ISDB-T mode 3, the number of carrier symbols used for calculation of the delay profile is 5617, and the S / N of the delay profile is approximately equal to the C / N of the received signal. 37.5 dB ( ₁₀ log ₁₀ 5617) is observed greatly. If the amplitude of additive noise n (i, m) is a normal distribution centered on the noise floor of SNR, the noise profile appears at a level lower than SNR in delay profile h (i, m) at discrete time m. . Therefore, the threshold value setting unit 24 sets and outputs the value obtained by subtracting the noise peak margin M (dB) from the SNR (dB) as the threshold value th.

The noise peak margin M is preferably about 10 to 20 dB. In FIG. 8, when there is a delayed wave having an amplitude ratio of 10 dB with respect to an incoming wave having the largest amplitude and a delay time of 10 μs, and the average C / N of all subcarriers used for calculating the delay profile is 20 dB, The example of the delay profile calculated | required using the delay profile analysis circuit 100-2 is shown. This example shows a delay profile output from the IFFT unit 41 and input to the noise component removing unit 20. Further, FIG. 9 shows a delay profile from which a threshold value or less, which is an output example from the noise component removing unit 20, is removed.

尚、遅延プロファイル解析回路１００−１，２は、しきい値処理部２５により出力される雑音成分除去後の遅延プロファイルを、再度ＦＦＴして雑音成分除去後の周波数応答として出力するようにしてもよい。 The threshold processing unit 25 uses the threshold th output from the threshold setting unit 24 to remove components whose amplitude is equal to or smaller than th at each discrete time m of the delay profile output from the IFFT unit 41. To do. A delay profile for removing a component equal to or less than the threshold th is as shown in Expression (13).

Note that the delay profile analysis circuits 100-1 and 100-2 may perform the FFT of the delay profile after removal of the noise component output by the threshold processing unit 25 again and output it as a frequency response after removal of the noise component. Good.

  As described above, according to the delay profile analysis circuit 100-1 of the first embodiment and the delay profile analysis circuit 100-2 of the second embodiment, the noise component removal unit 20 equalizes the transmission path characteristics using the SP signal. Then, the modulation error ratio is obtained from the carrier symbol after the delay, the S / N of the delay profile is estimated from the obtained modulation error ratio, the threshold is set, and the delay obtained by IFFT of the transmission line response by the IFFT unit 41 Threshold processing for removing components below the threshold is performed on the profile. Thereby, it is possible to realize a delay profile analysis circuit capable of adaptively removing a noise component included in a signal under measurement and generating a delay profile including only transmission path characteristics.

[Delay Profile Analysis Circuit / Example 3]
Next, a third embodiment of the delay profile analysis circuit will be described. FIG. 10 is a block diagram showing a third configuration of the delay profile analysis circuit according to the exemplary embodiment of the present invention. The delay profile analysis circuit 100-3 includes a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, a GI removal unit 5, an FFT unit 6, a transmission path response calculation unit 33, an IFFT unit 41, and a noise component. A removal unit 26 is provided. The transmission path response calculation unit 33 includes an SP signal extraction unit 11, a reference SP signal generation unit 12, a division unit 13, and an interpolation unit 14. The noise component removing unit 26 includes a threshold processing unit 25 and a threshold setting unit 70.

  When the delay profile analysis circuit 100-3 shown in FIG. 10 and the delay profile analysis circuit 100-1 shown in FIG. 1 are compared, the frequency conversion unit 2, the A / D conversion unit 3, the quadrature demodulation unit 4, the GI are the same. The delay profile analysis circuit 100-3 is the same in that the removal unit 5, the FFT unit 6, and the IFFT unit 41 are provided. The delay profile analysis circuit 100-3 includes the transmission line response calculation unit 33 and the noise component removal unit 26. −1 channel equalization unit 10 and noise component removal unit 20 are provided instead.

  In FIG. 10, the frequency conversion unit 2, the A / D conversion unit 3, the quadrature demodulation unit 4, the GI removal unit 5, and the FFT unit 6 have the same functions as those shown in FIG. Here, the carrier symbol converted by the FFT unit 6 is input to the SP signal extraction unit 11 of the transmission path response calculation unit 33.

  The SP signal extraction unit 11, the reference SP signal generation unit 12, the division unit 13, and the interpolation unit 14 of the transmission path response unit 33 have functions equivalent to those shown in FIG. That is, the SP signal extraction unit 11 extracts an SP signal from the carrier symbol, the reference SP signal generation unit 12 generates a reference SP signal, the division unit 13 calculates a transmission line response, and the interpolation unit 14 calculates the transmission line response. Interpolate. Here, the transmission path response output by the interpolation unit 14 is input to the IFFT unit 41.

  The IFFT unit 41 and the threshold value processing unit 25 of the noise component removal unit 26 have functions equivalent to those shown in FIG. That is, the IFFT unit 41 performs IFFT on the transmission line response and converts it into a delay profile, and the threshold processing unit 25 inputs the delay profile from the IFFT unit 41 and the threshold from the threshold setting unit 70, respectively. Then, threshold processing is performed on the delay profile to remove noise components.

[Threshold setting section]
First, the first configuration of the threshold setting unit 70 shown in FIG. 10 will be described. FIG. 11 is a block diagram showing a first configuration of the threshold value setting unit 70. The threshold value setting unit 70-1 includes a dividing unit 71, an average power calculating unit 72, a minimum value calculating unit 73, and a multiplying unit 74 for each delay time range of the delay profile divided by the dividing unit 71. . The dividing unit 71 receives the delay profile from the IFFT unit 41, divides the delay time range of the obtained delay profile into a plurality of blocks, and outputs the delay profiles in the divided delay time blocks to the average power calculating unit 72, respectively.

  Each average power calculation unit 72 receives the delay profile in the delay time block from the division unit 71, and calculates and outputs the average signal power per unit discrete time for the delay profile. The minimum value calculation unit 73 receives the average signal power per unit discrete time of the delay profile for each delay time block from the average power calculation unit 72, calculates the minimum value, and outputs it. The multiplier 74 receives the minimum average signal power from the minimum value calculator 73, multiplies the minimum signal power by a predetermined constant, and outputs the result as a threshold value.

とする。ここで、ｉは時間、ｍは遅延プロファイルに関する離散時間を示す。尚、以下の説明においてｉは省略する。 Next, the threshold value setting unit 70-1 shown in FIG. 11 will be described in detail. The delay profile output from the IFFT unit 41

And Here, i is time, and m is discrete time related to the delay profile. In the following description, i is omitted.

ここで、Ｎは各遅延ブロックに含まれる遅延プロファイルの標本数を示し、Ｎ＝Ｍ／Ｋである。 The dividing unit 71 divides the delay time width to be measured into K delay blocks, and outputs a signal represented by the following equation.

Here, N indicates the number of samples of the delay profile included in each delay block, and N = M / K.

Here, in order to simplify the explanation, K and N are divisors of M, but it is not always necessary to divide them for the same number of samples. Moreover, each delay block may overlap. For example, for the delay block k, m _k samples may be extracted from the discrete time n _k of h (n), and a signal represented by the following equation may be output.

The average power calculation unit 72 obtains the average signal power per unit discrete time of the delay profile for each delay block as in the following equation.

ここで、ω_ｎは、遅延ブロック内の離散時間ｎにおける重みを示す。 Here, for simplicity of explanation, the average value in the delay block is obtained, but each discrete time in the delay block is weighted, and the average signal power is obtained as in the following equation. Also good.

Here, ω _n indicates a weight at discrete time n in the delay block.

In each delay block, when there is a significant delayed wave, the above-mentioned average signal power P _k becomes large, and when there is no significant delayed wave, the average signal power P _k is the delay profile. S / N.

The minimum value calculation unit 73 obtains and outputs the minimum value in the following k range for the average signal power calculated by the average power calculation unit 72.

The multiplying unit 74 multiplies the minimum signal power calculated by the minimum value calculating unit 73 by a predetermined constant α to provide a noise peak margin, and outputs the result as a threshold value as in the following equation. .

Note that the number of samples M / K included in each delay block needs to be a sufficient number so that the average signal power P _k becomes the average of the sample values even when there is no delay wave. Further, the number of delay blocks K needs to be large so that there is no delay wave in at least one delay block.

  FIG. 13 is a diagram for explaining a threshold setting method by the threshold setting unit 70-1 shown in FIG. 11, and an example of a delay profile is shown in a waveform diagram. As shown in FIG. 13, the threshold value setting unit 70-1 divides the delay profile into a plurality of delay blocks using the delay time interval indicated by the dotted line as a delay time width, and the signal power for each delay block. Is obtained as a threshold value.

  Next, the second configuration of the threshold setting unit 70 shown in FIG. 10 will be described. FIG. 12 is a block diagram showing a second configuration of the threshold value setting unit 70. The threshold value setting unit 70-2 includes a weighted moving average processing unit 75, a minimum value calculation unit 76, and a multiplication unit 77. The weighted moving average processing unit 75 receives a delay profile from the IFFT unit 41, performs a weighted moving average process in the time direction of the delay profile to smooth the delay profile, and outputs a smoothed delay profile.

  The minimum value calculation unit 76 receives the smoothed delay profile from the weighted moving average processing unit 75, obtains the minimum value of the sample values of the delay profile at each discrete time, and outputs it as the minimum signal power. The multiplier 77 receives the minimum signal power from the minimum value calculator 76, multiplies the minimum signal power by a predetermined constant, and outputs the result as a threshold value.

The threshold value setting unit 70-2 of FIG. 12 configured as described above corresponds to the case where m _k is a constant and n _{k + 1} −n _k = 1. Is omitted.

  As described above, according to the delay profile analysis circuit 100-3 of the third embodiment, the transmission line response calculation unit 33 calculates the transmission line characteristic using the SP signal, and the noise component removal unit 26 uses the IFFT unit 41. The threshold value processing for removing components below the threshold value is performed on the delay profile obtained by IFFT of the transmission line response using the threshold value based on the minimum signal power in the delay profile. I made it. Thereby, it is possible to realize a delay profile analysis circuit capable of adaptively removing a noise component included in a signal under measurement and generating a delay profile including only transmission path characteristics.

[Delay Profile Analysis Circuit / Embodiment 4]
Next, a fourth embodiment of the delay profile analysis circuit will be described. FIG. 14 is a block diagram showing a fourth configuration of the delay profile analysis circuit according to the exemplary embodiment of the present invention. The delay profile analysis circuit 100-4 includes a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, a GI removal unit 5, an FFT unit 6, a transmission line response calculation unit 34, an IFFT unit 41, and a noise component. A removal unit 26 is provided. The transmission path response calculation unit 34 includes a channel equalization unit 10, a determination unit 21, and a division unit 31, and the channel equalization unit 10 includes an SP signal extraction unit 11, a reference SP signal generation unit 12, a division unit 13, and an interpolation. A unit 14 and a division unit 15 are provided. The noise component removing unit 26 includes a threshold processing unit 25 and a threshold setting unit 70.

  Comparing the delay profile analysis circuit 100-4 shown in FIG. 14 with the delay profile analysis circuit 100-2 shown in FIG. 2, they both have the channel equalization unit 10 and the transmission line response calculation units 30 and 34 having the same configuration. I have. Further, when comparing the delay profile analysis circuit 100-4 of FIG. 14 with the delay profile analysis circuit 100-3 shown in FIG. 10, both include the IFFT unit 41 and the noise component removal unit 26 having the same configuration. That is, the delay profile analysis circuit 100-4 includes the transmission line response calculation unit 30 included in the delay profile analysis circuit 100-2, and the IFFT unit 41 and the noise component removal unit 26 included in the delay profile analysis circuit 100-3. It is configured in combination.

  In FIG. 14, the frequency conversion unit 2, the A / D conversion unit 3, the quadrature demodulation unit 4, the GI removal unit 5 and the FFT unit 6 have functions equivalent to those shown in FIGS. The transmission path response unit 34 has a function equivalent to that shown in FIG. 2, and the IFFT unit 41 and the noise component removal unit 26 have a function equivalent to that shown in FIG.

  As described above, according to the delay profile analysis circuit 100-4 of the fourth embodiment, the transmission line response calculation unit 34 calculates the transmission line characteristic using the SP signal, and the noise component removal unit 26 uses the IFFT unit 41. The threshold value processing for removing components below the threshold value is performed on the delay profile obtained by IFFT of the transmission line response using the threshold value based on the minimum signal power in the delay profile. I made it. Thereby, it is possible to realize a delay profile analysis circuit capable of adaptively removing a noise component included in a signal under measurement and generating a delay profile including only transmission path characteristics.

[Wraparound canceller / Example 1]
Next, Example 1 of the wraparound canceller will be described. FIG. 5 is a block diagram showing a first configuration of a wraparound canceller using delay profile analysis circuit 100-1 (delay profile analysis circuit of Example 1) according to the embodiment of the present invention. The sneak canceller 200-1 includes a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, an adaptive filter 54, a subtraction unit 55, an orthogonal modulation unit 56, a D / A converter 57, a frequency conversion unit 58, And a sneak path estimation unit 61. The wraparound channel estimation unit 61 includes a GI removal unit 5, an FFT unit 6, a channel equalization unit 10 having a transmission path response calculation unit 30, a noise component removal unit 20, a cancellation residual calculation unit 51, an IFFT unit 41, and an addition unit. 52 and a delay unit 53. The channel equalization unit 10 includes a transmission line response calculation unit 30 and a division unit 15. The transmission line response calculation unit 30 includes an SP signal extraction unit 11, a reference SP signal generation unit 12, a division unit 13, and an interpolation unit 14. I have. The noise component removing unit 20 includes a determination unit 21, an error calculation unit 22, a modulation error ratio calculation unit 23, a threshold setting unit 24, and a threshold processing unit 25.

  In FIG. 5, the frequency converter 2 receives a received signal, converts the received signal into an IF band signal, and outputs an IF signal. The A / D conversion unit 3 receives the IF signal and converts the analog IF signal into a digital IF signal using a sampling clock from a synchronous reproduction unit (not shown). The quadrature demodulator 4 receives a digital IF signal, performs quadrature demodulation on the digital IF signal, and outputs an equivalent baseband signal. The subtractor 55 receives the equivalent baseband signal from the quadrature demodulator 4, receives the sneak wave replica signal from the adaptive filter 54, subtracts the sneak wave replica signal from the equivalent baseband signal, and subtracts the replica signal The equivalent baseband signal is output. Here, the equivalent baseband signal output from the subtracting unit 55 is divided into three and input to the quadrature modulation unit 56, the adaptive filter 54, and the GI removal unit 5 of the sneak path estimation unit 61, respectively.

  The quadrature modulation unit 56 receives the equivalent baseband signal from the subtraction unit 55, performs quadrature modulation on the equivalent baseband signal, and outputs a digital IF signal. The D / A converter 57 receives a digital IF signal, converts the digital IF signal into an analog IF signal using a sampling clock from a synchronous reproduction unit (not shown), and outputs the analog IF signal. The frequency conversion unit 58 receives an analog IF signal, converts the frequency of the analog IF signal, and outputs it as a transmission signal to the outside.

  The GI removing unit 5 receives the other equivalent baseband signal from the subtracting unit 55, and uses a signal (symbol timing) indicating the symbol period and timing of the OFMD signal from a synchronous reproduction unit (not shown) to generate one OFDM transmission symbol. A period corresponding to GI is removed from the period, and a signal having a time length corresponding to an effective symbol period (an OFDM signal in a time domain corresponding to the effective symbol period) is extracted. The FFT unit 6 receives an OFDM signal in the time domain for the effective symbol period, and performs FFT to convert it into a carrier symbol that is a frequency domain signal. Here, the carrier symbols converted by the FFT unit 6 are divided into two, one being input to the division unit 15 and the other being input to the SP signal extraction unit 11.

  The SP signal extraction unit 11, the reference SP signal generation unit 12, the division unit 13, the interpolation unit 14, and the division unit 15 have the same functions as those shown in FIG. That is, the SP signal extraction unit 11 extracts an SP signal from the carrier symbol, the reference SP signal generation unit 12 generates a reference SP signal, the division unit 13 calculates a transmission line response, and the interpolation unit 14 calculates the transmission line response. Interpolate. Here, the transmission path response output by the interpolation unit 14 is divided into two, one being input to the division unit 15 and the other being input to the cancellation residual calculation unit 51. The division unit 15 calculates the equalized data symbol.

  The determination unit 21, the error calculation unit 22, the modulation error ratio calculation unit 23, and the threshold value setting unit 24 have the same functions as those shown in FIG. That is, the determination unit 21 determines the estimated value of the transmission symbol. Here, the estimated value of the transmission symbol output by the determination unit 21 is divided into two and input to the error calculation unit 22 and the modulation error ratio calculation unit 23, respectively. The error calculator 22 calculates an error between the equalized data symbol and the estimated value of the transmission symbol. The modulation error ratio calculation unit 23 calculates the modulation error ratio from the error and the estimated value of the transmission symbol using all the data symbols. The threshold setting unit 24 estimates the S / N of the delay profile from the modulation error ratio, and sets the threshold.

  The cancellation residual calculation unit 51 receives the transmission line response from the interpolation unit 14 and calculates and outputs the transmission line response of the wraparound cancellation residual included in the equivalent baseband signal. The IFFT unit 41 receives the transmission path response of the wraparound cancellation residual from the cancellation residual calculation section 51, performs IFFT on the transmission path response, converts it to an update of the impulse response of the wraparound propagation path, and outputs it. The adder 52 receives the updated impulse response from the IFFT unit 41, inputs the filter coefficient after the previous update from the delay unit 53, adds the updated impulse response to the filter coefficient, and outputs it as a filter coefficient. . The threshold processing unit 25 receives a filter coefficient from the adding unit 52, inputs a threshold from the threshold setting unit 24, performs threshold processing using the threshold on the filter coefficient, and performs noise processing. The component is removed, and the filter coefficient after removal of the noise component is output. Here, the filter coefficients output by the threshold processing unit 25 are divided into two, one input to the adaptive filter 54 and the other input to the delay unit 53.

  The delay unit 53 receives the filter coefficient from the threshold processing unit 25, delays and holds the filter coefficient until the next filter coefficient update, and outputs it to the adder 52 at the next filter coefficient update. The adaptive filter 54 receives a filter coefficient from the threshold processing unit 25, receives an equivalent baseband signal from the subtraction unit 55, filters the equivalent baseband signal using the filter coefficient, and generates a sneak wave replica signal. It is generated and output to the subtracting unit 55.

  The operation of the sneak canceller 200-1 of FIG. 5 configured as described above will be described below. A sneak canceller is an apparatus for canceling a sneak wave caused by coupling between transmitting and receiving antennas from a received signal and retransmitting only a master station signal in an SFN broadcast wave relay station that performs retransmission at the same frequency as the frequency of the received signal. It is.

  The wraparound occurs when a part of the radio wave radiated from the transmission antenna passes through the wraparound propagation path and is received by the reception antenna. For this reason, if a circuit having the same characteristics as the sneak path can be realized inside the sneak canceller, a sneak wave replica signal can be generated.

  The operating principle of the sneak canceller is to cancel the sneak by subtracting the internally generated sneak wave replica signal from the received signal and take out only the master station signal. The adaptive filter 54 shown in FIG. 5 realizes the same transmission path characteristic as that of the sneak path, and the filter coefficient input by the adaptive filter 54 is generated based on the delay profile of the sneak path.

  The delay profile analysis circuit 100-1 shown in FIG. 1 can be used for the sneak path estimation unit 61 in the sneak canceller 200-1 shown in FIG. The difference between the sneak path estimation unit 61 shown in FIG. 5 and the delay profile analysis circuit 100-1 shown in FIG. 1 is that the sneak path estimation unit 61 is between the interpolation unit 14 and the IFFT unit 41. The cancellation residual calculation unit 51 is provided, and the noise component removal unit 20 is provided after the addition unit 52. The details of the wraparound canceller are disclosed in Japanese Patent Application Laid-Open No. 11-355160, “wraparound canceller” and academic conference paper “Basic study of wraparound canceller for broadcast wave relay station in digital terrestrial broadcasting SFN” (Journal of the Video Information Media Society Vol.54). , No. 11, pp. 1568-1575 (2000)), description thereof is omitted here.

[Wraparound canceller / Example 2]
Next, a second embodiment of the wraparound canceller will be described. FIG. 6 is a block diagram showing a second configuration of the wraparound canceller using the delay profile analysis circuit 100-2 (delay profile analysis circuit of the second embodiment) according to the embodiment of the present invention. The sneak canceller 200-2 includes a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, an adaptive filter 54, a subtraction unit 55, an orthogonal modulation unit 56, a D / A converter 57, a frequency conversion unit 58, And a sneak path estimation unit 62. The sneak path estimation unit 62 includes a GI removal unit 5, an FFT unit 6, a channel response calculation unit 30 having a channel equalization unit 10, a noise component removal unit 20, a cancellation residual calculation unit 51, an IFFT unit 41, and an addition unit. 52 and a delay unit 53. The transmission path response calculation unit 30 includes a channel equalization unit 10, a determination unit 21, and a division unit 31, and the channel equalization unit 10 includes an SP signal extraction unit 11, a reference SP signal generation unit 12, a division unit 13, and an interpolation. A unit 14 and a division unit 15 are provided. The noise component removing unit 20 includes a determination unit 21, an error calculation unit 22, a modulation error ratio calculation unit 23, a threshold setting unit 24, and a threshold processing unit 25.

  When the sneak canceller 200-2 shown in FIG. 6 is compared with the sneak canceller 200-1 shown in FIG. 5, the frequency converter 2, the A / D converter 3, the quadrature demodulator 4, the subtractor 55, and the quadrature Although it is the same in that the modulator 56, the D / A converter 57, and the frequency converter 58 are provided in this order, and the adaptive filter 54 that feeds back the replica signal of the sneak wave to the subtractor 55 is provided. The configuration of the sneak path estimation unit 62, that is, the configuration of the channel equalization unit 10, the noise component removal unit 20, and the transmission path response calculation unit 30 is different.

  In FIG. 6, a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, a subtraction unit 55, an orthogonal modulation unit 56, a D / A converter 57, a frequency conversion unit 58, a GI removal unit 5 and an FFT unit 6 Has the same function as that shown in FIG. Here, the carrier symbols converted by the FFT unit 6 are divided into three and input to the division unit 15, the SP signal extraction unit 11 that is a training signal extraction unit, and the division unit 31, respectively.

  The SP signal extraction unit 11, the reference SP signal generation unit 12, the division unit 13, the interpolation unit 14, and the division unit 15 have the same functions as those shown in FIG. Here, the transmission path response output by the interpolation unit 14 is input to the division unit 15.

  The determination unit 21, the error calculation unit 22, the modulation error ratio calculation unit 23, and the threshold value setting unit 24 have the same functions as those shown in FIG. Here, the estimated value of the transmission symbol output by the determination unit 21 is divided into three and input to the error calculation unit 22, the modulation error ratio calculation unit 23, and the division unit 31, respectively.

  Division unit 31 receives a carrier symbol from FFT unit 6, receives an estimated value of a transmission symbol from determination unit 21, divides the carrier symbol by an estimated value of the transmission symbol, calculates a transmission path response, and outputs it. .

  Cancellation residual calculation unit 51, IFFT unit 41, addition unit 52, threshold processing unit 25, and delay unit 53 have the same functions as those shown in FIG. That is, the cancellation residual calculation unit 51 receives the transmission line response from the division unit 31, calculates and outputs the transmission line response of the wraparound cancellation residual included in the equivalent baseband signal. The IFFT unit 41 performs IFFT on the transmission line response, converts it into an updated impulse response of the sneak path, and outputs it. The adder 52 adds the updated impulse response to the filter coefficient, and outputs the filter coefficient. The threshold processing unit 25 performs threshold processing using a threshold on the filter coefficient to remove a noise component, and outputs the filter coefficient after the noise component is removed. The delay unit 53 delays and holds the filter coefficient until the next filter coefficient update, and outputs the filter coefficient to the adder 52 at the next filter coefficient update. Further, the adaptive filter 54 filters the equivalent baseband signal using the filter coefficient, generates a sneak wave replica signal, and outputs it to the subtractor 55.

  The sneak canceller 200-2 of FIG. 6 configured as described above is the same as the sneak canceller 200-1 shown in FIG. 5 except for the method of calculating the transmission path response H (i, k). Omitted.

[Wraparound canceller / Example 3]
Next, a third embodiment of the wraparound canceller will be described. FIG. 15 is a block diagram showing a third configuration of the wraparound canceller using the delay profile analysis circuit 100-3 (the delay profile analysis circuit of Example 3) according to the embodiment of the present invention. The wraparound canceller 200-3 includes a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, an adaptive filter 54, a subtraction unit 55, an orthogonal modulation unit 56, a D / A converter 57, a frequency conversion unit 58, And a sneak path estimation unit 63. The wraparound channel estimation unit 63 includes a GI removal unit 5, an FFT unit 6, a transmission channel response calculation unit 33, a cancellation residual calculation unit 51, an IFFT unit 41, an addition unit 52, a noise component removal unit 27, and a delay unit 53. I have. The transmission path response calculation unit 33 includes an SP signal extraction unit 11, a reference SP signal generation unit 12, a division unit 13, and an interpolation unit 14. The noise component removing unit 27 includes a threshold setting unit 70 and a threshold processing unit 25.

  Comparing the sneak canceller 200-3 shown in FIG. 15 with the sneak canceller 200-1 shown in FIG. 5, the frequency converter 2, the A / D converter 3, the quadrature demodulator 4, the subtractor 55, and the quadrature Although it is the same in that the modulator 56, the D / A converter 57, and the frequency converter 58 are provided in this order, and the adaptive filter 54 that feeds back the replica signal of the sneak wave to the subtractor 55 is provided. The configuration of the sneak path estimation unit 63 is different.

  In FIG. 15, a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, an adaptive filter 54, a subtraction unit 55, an orthogonal modulation unit 56, a D / A converter 57, a frequency conversion unit 58, and a GI removal unit 5 The FFT unit 6 has a function equivalent to that shown in FIG. Here, the carrier symbol converted by the FFT unit 6 is input to the SP signal extraction unit 11.

  The SP signal extraction unit 11, the reference SP signal generation unit 12, the division unit 13, and the interpolation unit 14 have the same functions as those shown in FIG. Here, the transmission path response output by the interpolation unit 14 is input to the cancellation residual calculation unit 51.

  The cancellation residual calculation unit 51, the IFFT unit 41, the addition unit 52, and the delay unit 53 have the same functions as those shown in FIG. Here, the output of the IFFT unit 41 is divided into two and input to the threshold value setting unit 70 and the addition unit 52 of the noise component removal unit 27, respectively. The threshold setting unit 70 and the threshold processing unit 25 have functions equivalent to those of the delay profile analysis circuit 100-3 shown in FIG.

[Wraparound canceller / Example 4]
Next, a fourth embodiment of the wraparound canceller will be described. FIG. 16 is a block diagram showing a fourth configuration of the wraparound canceller using the delay profile analysis circuit 100-4 (the delay profile analysis circuit of the fourth example) according to the embodiment of the present invention. The wraparound canceller 200-4 includes a frequency conversion unit 2, an A / D conversion unit 3, an orthogonal demodulation unit 4, an adaptive filter 54, a subtraction unit 55, an orthogonal modulation unit 56, a D / A converter 57, a frequency conversion unit 58, And a sneak path estimation unit 64. The sneak path estimation unit 64 includes a GI removal unit 5, an FFT unit 6, a channel response calculation unit 34 having a channel equalization unit 10, a cancellation residual calculation unit 51, an IFFT unit 41, an addition unit 52, and a noise component removal unit. 27, and a delay unit 53. The transmission path response calculation unit 34 includes a channel equalization unit 10, a determination unit 21, and a division unit 31, and the channel equalization unit 10 includes an SP signal extraction unit 11, a reference SP signal generation unit 12, a division unit 13, and an interpolation. A unit 14 and a division unit 15 are provided. The noise component removing unit 27 includes a threshold setting unit 70 and a threshold processing unit 25.

  When the sneak canceller 200-4 shown in FIG. 16 is compared with the sneak canceller 200-2 shown in FIG. 6, the GI removal unit 5, the FFT unit 6, and the transmission path response calculation units 30 and 34 having the same configuration are used. I have. Further, when the sneak canceller 200-4 shown in FIG. 16 and the sneak canceller 200-3 shown in FIG. 15 are compared, they both have a cancellation residual calculation unit 51, an IFFT unit 41, an adder 52, a noise component having the same configuration. A removal unit 27 and a delay unit 53 are provided. That is, the wraparound canceller 200-4 includes the GI removal unit 5, the FFT unit 6, and the transmission path response calculation unit 30 included in the wraparound canceller 200-2, and the cancellation residual calculation unit 51 included in the wraparound canceller 200-3. The IFFT unit 41, the adding unit 52, the noise component removing unit 27, and the delay unit 53 are combined.

  In FIG. 16, the frequency conversion unit 2, the A / D conversion unit 3, the quadrature demodulation unit 4, the adaptive filter 54, the subtraction unit 55, the quadrature modulation unit 56, the D / A converter 57, the frequency conversion unit 58, and the GI removal unit 5 The FFT unit 6 has the same function as that shown in FIGS. Here, the carrier symbols converted by the FFT unit 6 are divided into three and input to the division unit 15, the SP signal extraction unit 11, and the division unit 31.

  The SP signal extraction unit 11, the reference SP signal generation unit 12, the division unit 13, the interpolation unit 14, the division unit 15, the determination unit 21, and the division unit 31 have functions equivalent to those illustrated in FIG. Here, the transmission path response output by the division unit 31 is input to the cancellation residual calculation unit 51. Cancellation residual calculation unit 51, IFFT unit 41, addition unit 52, threshold setting unit 70, threshold processing unit 25, and delay unit 53 have the same functions as those shown in FIG.

  As described above, the sneak propagation path estimation units 61, 62, 63, and 64 of the sneak cancellers 200-1, 2, 3, and 4 shown in FIG. 5, FIG. 6, FIG. 15, and FIG. When the conventional delay profile analysis circuit 1 is used, the estimated sneak path characteristics (filter coefficients output from the sneak path estimation units 61, 62, 63, and 64) include noise components included in the transmission signal. End up. For this reason, when the adaptive filter 54 generates a replica signal of a sneak wave, it also generates a noise component corresponding thereto. Since the noise component is additive, the noise component is added even if the sneak wave replica signal is subtracted from the received signal, and as a result, the quality of the transmission signal is degraded.

  However, when the delay profile analysis circuits 100-1, 2, 3, and 4 according to the embodiment of the present invention shown in FIGS. 1, 2, 10, and 14 are used, the estimated sneak path characteristics ( The noise component is removed from the filter coefficient, that is, the filter coefficient does not include the noise component. For this reason, the adaptive filter 54 does not generate unnecessary noise components. Therefore, the wraparound cancellers 200-1, 2, 3, and 4 can cancel the wraparound component included in the received signal satisfactorily.

  The present invention has been described with reference to the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the technical idea thereof. For example, in the above embodiment, the example of the sneak cancellers 200-1, 2, 3, 4 using the delay profile analysis circuits 100-1, 2, 3, 4 has been described. The delay profile analysis circuits 100-1, 2, 3, and 4 can also be used for the relay device or the data processing device.

  1, 2, 5, 6, 10, 14, 15, 15 and 16, the delay profile analysis circuits 100-1, 2, 3, 4 and the wraparound cancellers 200-1, 2, 3 are used. , 4 are configured in the order of the frequency conversion unit 2, the A / D conversion unit 3, the quadrature demodulation unit 4, and the GI removal unit 5, but the arrangement of the A / D conversion unit 3 and the quadrature demodulation unit 4 is reversed. That is, the frequency converter 2, the orthogonal demodulator 4, the A / D converter 3, and the GI remover 5 may be configured in this order. In this case, the analog quadrature demodulator, which is the quadrature demodulator 4, outputs I and Q equivalent baseband signals, and one A / D converter 3 of the two A / D converters 3 is the equivalent base of I. A band signal is input and a digital signal is output, and the other A / D converter 3 inputs a Q equivalent baseband signal and outputs a digital signal.

It is a block diagram which shows the 1st structure of the delay profile analysis circuit by embodiment of this invention. It is a block diagram which shows the 2nd structure of the delay profile analysis circuit by embodiment of this invention. It is a block diagram which shows the structure of the conventional delay profile analysis circuit. It is a block diagram which shows the structure of the transmission line response calculation part of FIG. It is a block diagram which shows the 1st structure of the wraparound canceller using the delay profile analysis circuit by embodiment of this invention. It is a block diagram which shows the 2nd structure of the wraparound canceller using the delay profile analysis circuit by embodiment of this invention. It is a figure explaining arrangement | positioning of SP. It is a wave form diagram which shows the example of a delay profile. It is a wave form diagram which shows the example of the delay profile calculated | required by the delay profile analysis circuit by embodiment of this invention. It is a block diagram which shows the 3rd structure of the delay profile analysis circuit by embodiment of this invention. It is a block diagram which shows the 1st structure of the threshold value setting part in FIG. It is a block diagram which shows the 2nd structure of the threshold value setting part in FIG. It is a wave form diagram which shows the example of the delay profile for demonstrating a threshold value setting method. It is a block diagram which shows the 4th structure of the delay profile analysis circuit by embodiment of this invention. It is a block diagram which shows the 3rd structure of the wraparound canceller using the delay profile analysis circuit by embodiment of this invention. It is a block diagram which shows the 4th structure of the wraparound canceller using the delay profile analysis circuit by embodiment of this invention.

Explanation of symbols

1, 100-1, 100-2, 100-3, 100-4 Delay profile analysis circuit 2, 57 Frequency conversion unit 3 A / D conversion unit 4 Orthogonal demodulation unit 5 GI removal unit 6 FFT unit 7 Transmission path response calculation unit 7-1 Pilot signal extraction unit 7-2 Pilot signal generation unit 7-3, 13, 15, 31 Division unit 7-4 Interpolation unit 8, 41 IFFT unit 10 Channel equalization unit 11 SP signal extraction unit 12 Reference SP signal generation Unit 14 interpolation unit 20, 26 noise component removal unit 21 determination unit 22 error calculation unit 23 modulation error ratio calculation unit 24, 70 threshold setting unit 25 threshold processing units 30, 33, 34 transmission line response calculation unit 51 cancel Residual calculation unit 52 Addition unit 53 Delay unit 54 Adaptive filter 55 Subtraction unit 56 Orthogonal modulation unit 57 D / A converters 60, 61, 62, 63, 64 Detour propagation path estimation unit 71 Division unit 72 Equalizing power calculation unit 73 and 76 the minimum value calculation unit 74 and 77 multiplying unit 75 weighted moving average processing unit 200-1,200-2,200-3,200-4 CLI Canceller

Claims (8)

An FFT unit for FFT of an input OFDM signal into a carrier symbol in the frequency domain;
A transmission line response calculation unit for calculating a transmission line response from the carrier symbol converted by the FFT unit;
An IFFT unit that IFFTs the transmission path response calculated by the transmission path response calculation unit into a delay profile on a time axis;
A channel equalization unit for performing channel equalization of the carrier symbol converted by the FFT unit;
Noise that sets a threshold based on the equalized carrier symbol equalized by the channel equalization unit, performs threshold processing on the delay profile converted by the IFFT unit, and removes noise components A delay profile analysis circuit comprising a component removal unit. The noise component removing unit is
A determination unit that determines a known transmission symbol having the smallest Euclidean distance on the signal space with the equalized carrier symbol equalized by the channel equalization unit as an estimated value of the actually transmitted carrier symbol;
An error calculation unit that calculates an error between the estimated value of the transmission carrier symbol determined by the determination unit and the carrier symbol after equalization by the channel equalization unit;
A modulation error ratio calculation unit that calculates a modulation error ratio using all data symbols from the estimated value of the transmission carrier symbol determined by the determination unit and the error calculated by the error calculation unit;
A threshold value setting unit that estimates the S / N of the delay profile from the modulation error ratio calculated by the modulation error ratio calculation unit, and sets a threshold value;
The threshold processing unit for removing a signal component below a threshold set by the threshold setting unit from the delay profile converted by the IFFT unit. Delay profile analysis circuit. The transmission line response calculation unit,
A pilot signal extraction unit for extracting a pilot signal transmitted by a subcarrier having a predetermined symbol number and subcarrier number from the carrier symbol converted by the FFT unit;
A reference pilot signal generator for generating a reference pilot signal having a predetermined amplitude and phase;
A division unit for dividing a pilot signal extracted by the pilot signal extraction unit by a reference pilot signal generated by the reference pilot signal generation unit, and calculating a transmission line response at a frequency of a subcarrier on which the pilot signal is transmitted The delay profile analysis circuit according to claim 1 or 2, characterized by comprising: The transmission line response calculation unit,
A pilot signal extraction unit for extracting a pilot signal transmitted by a subcarrier having a predetermined symbol number and subcarrier number from the carrier symbol converted by the FFT unit;
A reference pilot signal generator for generating a reference pilot signal having a predetermined amplitude and phase;
A division unit for dividing a pilot signal extracted by the pilot signal extraction unit by a reference pilot signal generated by the reference pilot signal generation unit, and calculating a transmission line response at a frequency of a subcarrier on which the pilot signal is transmitted When,
An interpolation unit that performs interpolation of the transmission line response calculated by the division unit;
A division unit that divides the carrier symbol converted by the FFT unit by the transmission path response interpolated by the interpolation unit and performs channel equalization;
A determination unit that determines a known transmission symbol having the smallest Euclidean distance on the signal space with the equalized carrier symbol output from the division unit as an estimated value of the actually transmitted carrier symbol;
3. The division unit according to claim 2, further comprising: a division unit that divides the carrier symbol converted by the FFT unit by an estimated value of the transmission carrier symbol determined by the determination unit and calculates a transmission line response. Delay profile analysis circuit. An FFT unit for FFT of an input OFDM signal into a carrier symbol in the frequency domain;
A transmission line response calculation unit for calculating a transmission line response from the carrier symbol converted by the FFT unit;
An IFFT unit that IFFTs the transmission path response calculated by the transmission path response calculation unit into a delay profile on a time axis;
The delay profile converted by the IFFT unit includes a noise component removing unit that calculates a minimum value of the signal power, sets a threshold value, and performs threshold processing to remove a noise component. Delay profile analysis circuit. The noise component removing unit is
A division unit that divides the delay profile converted by the IFFT unit into a plurality of blocks for each delay time;
An average signal power calculation unit for obtaining an average signal power per unit discrete time of the delay profile for each block of the delay profile divided by the dividing unit;
A minimum value calculation unit for obtaining a minimum value of average signal power per unit discrete time for the number of divisions;
A multiplier for multiplying a minimum value of the average signal power calculated by the minimum value calculator by a predetermined constant and outputting the result as a threshold;
6. The delay profile analysis according to claim 5, further comprising: a threshold value processing unit that removes a signal component that is not more than a threshold value output by the multiplication unit from the delay profile converted by the IFFT unit. circuit. The noise component removing unit is
A weighted moving average processing unit that performs weighted moving average processing on the delay profile converted by the IFFT unit;
A minimum value calculating unit that calculates a minimum value of the delay profile for the delay profile subjected to the weighted moving average processing by the weighted moving average processing unit;
A multiplication unit that multiplies a minimum value of the delay profile calculated by the minimum value calculation unit by a predetermined constant and outputs it as a threshold value;
6. The delay profile analysis according to claim 5, further comprising: a threshold value processing unit that removes a signal component that is not more than a threshold value output by the multiplication unit from the delay profile converted by the IFFT unit. circuit. An adaptive filter that filters a received signal and generates a replica signal of a sneak wave;
A subtractor for subtracting the replica signal generated by the adaptive filter from the received signal;
The delay profile analysis circuit according to any one of claims 1 to 7, wherein the delay profile is generated as a filter coefficient for generating a replica signal of a sneak wave.
A sneak canceller that cancels a sneak wave caused by coupling between transmitting and receiving antennas from the received signal.

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