KR100345329B1 - Apparatus for sampling clock recovery in an OFDM receiver and method therof - Google Patents

Abstract

The present invention discloses a sampling clock recovery apparatus and method thereof in an orthogonal frequency division multiplexing receiver.

The present invention provides a device for recovering a sampling clock in an OFDM receiver, wherein the output of an analog-to-digital converter and an analog-to-digital converter for sampling an analog OFDM pilot signal according to an input sampling clock signal and converting the analog clock into a digital signal are converted into FFTs. FFT unit for extracting pilot pattern by Fast Fourier Transform, frequency detector for calculating estimated sampling frequency error by obtaining pilot pattern of previous frame and pilot pattern of previous frame by using input signal of pilot pattern and corresponding FFT unit And a VCXO for reducing the noise of the estimated sampling frequency error, and outputting the sampling clock signal according to an output value of the loop filter unit and the loop filter unit for determining the convergence range and the convergence speed of the pilot signal.

According to the present invention, the sampling frequency offsets of the current and previous frames are obtained by using the sampled pilot signal and the pilot pattern obtained by FFT the sampled signal, and the estimated frequency error is calculated to calculate the frequency error. By feeding back the sampling frequency, the optimum sampling frequency with the minimum error is found, thereby efficiently recovering the sampling clock in the OFDM receiver.

Description

Apparatus for sampling clock recovery in an OFDM receiver and method therof}

The present invention relates to the field of orthogonal frequency division multiplexing, and more particularly, to a method and apparatus for sampling clock recovery in an orthogonal frequency division multiplexing receiver.

Orthogonal Frequency Division Multiplexing (hereinafter, referred to as OFDM) is a technology for effectively transmitting data using a plurality of subcarriers within a bandwidth of a channel. The subcarriers are configured to maximize bandwidth efficiency compared to past transmission schemes such as frequency division multiplexing (FDM).

In the FDM scheme, since each subcarrier exists in a different frequency band and a frequency guard band is provided so that interference does not occur between subcarriers, there is a lot of overhead and bandwidth efficiency is low. However, the OFDM scheme maximizes bandwidth efficiency by overlapping each subcarrier in a frequency domain, but does not cause interference between subcarriers by making another subcarrier null (zero) at the center frequency of each subcarrier. In addition, the OFDM symbol is much longer than the channel impulse response and can completely eliminate the interference between the symbols, and thus has strong characteristics in multipath fading.

Synchronization performed when demodulating an OFDM signal requires frame synchronization, sampling synchronization, carrier frequency synchronization, and the like. For each synchronization, a method specific to OFDM should be used.

1 is a block diagram of a conventional sampling synchronization device.

The pilot signal is input to the ADC unit 10 and converted from an analog signal to a digital signal, and the result is FFT (Fast Fourier Transform) in the FFT unit 11 so that the detected pilot pattern is phased. The sampling timing offset value output by phase detection from the detector 12 reduces noise in the loop filter 13, so that the convergence property of the entire loop is determined, and this value is determined by the PDM modulator 14. Converted to an analog value, the sampling clock is generated by the VCXO 15 and fed back to the ADC unit 10 to correct the sampling frequency error to restore the sampling clock.

However, the PLL (Phase Locked Loop) method used in the OFDM demodulator for synchronization of sampling frequency has a very fast convergence speed and has an advantage of restoring the sampling position, but has a disadvantage in that it does not converge for a wide sampling frequency error. . Therefore, it is difficult to apply to a system that does not use a very precise sampling frequency generator.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an apparatus and method for recovering a sampling clock in an OFDM receiver to solve the above problems.

1 is a block diagram of a conventional sampling synchronization device.

2 is a block diagram illustrating a sampling clock recovery apparatus in an OFDM receiver according to the present invention.

3 illustrates pilot signals and sampling positions of an OFDM (n-1) th frame and an n th frame.

Figure 4 shows the flow of operation of the frequency detector according to the present invention.

5 is a block diagram showing the configuration of the frequency detector according to the present invention.

6 is a block diagram showing the configuration of the loop filter unit.

An apparatus for restoring a sampling clock in an OFDM receiver according to the present invention for solving the above technical problem, comprising: an analog-to-digital converter for sampling an analog OFDM pilot signal according to an input sampling clock signal and converting the analog clock into a digital signal; An FFT unit extracting a pilot pattern by performing FFT (Fast Fourier Transform) on the output of the analog-digital converter; A frequency detector for calculating an estimated sampling frequency error by obtaining a pilot pattern of a current frame and a pilot pattern of a previous frame by using the pilot pattern and an input signal of the FFT unit corresponding thereto; A loop filter unit which reduces noise of the estimated sampling frequency error and determines a convergence range and a convergence speed of the pilot signal; And a VCXO for outputting the sampling clock signal according to the output value of the loop filter unit.

The apparatus may further include a digital-to-analog converter for outputting the analog signal, which is the output of the loop filter unit, to the VCXO for converting the analog signal into a corresponding digital signal.

The frequency detector includes means for estimating a sampling offset of a current frame using the plurality of pilot patterns and input signals corresponding to the FFT unit; Means for estimating a sampling offset of a previous frame by using the plurality of pilot patterns and input signals corresponding to the FFT unit; And means for calculating an estimated sampling frequency error by obtaining an average per frame of the difference between the estimated sampling offset of the current frame and the estimated sampling offset of the previous frame.

A method for recovering a sampling clock in an OFDM receiver according to the present invention for solving the other technical problem, the method comprising the steps of: (a) sampling the analog OFDM pilot signal according to the input sampling clock signal to convert it into a digital signal; (b) extracting a pilot pattern by performing a fast fourier transform (FFT) on the digitally converted signal; (c) calculating an estimated sampling frequency error by obtaining a pilot pattern of a current frame and a pilot pattern of a previous frame by using the pilot pattern and an input signal before FFT corresponding thereto; (d) filtering to reduce noise of the estimated sampling frequency error, and to determine a convergence range and a convergence speed of the pilot signal; And (e) outputting the sampling clock signal according to the output value of the loop filter unit.

In this case, in the step (c), when N is the number of sampling of the frame, m is the frequency bin index, and d is a predetermined constant, it is received at the (m1) th frequency bin for each of the current frame and the previous frame. Conjugating the signal; (c2) conjugating the signal received at the (m + d) th frequency bin; (c3) conjugating the complexed complex number of step (c2) with the result of FFT of the signal received at the (m + d) th frequency bin with a result of complex multiplication; (c4) The value of m is multiplied by the complexed complex number in step (c1) with the complex signal multiplied by the result of FFT of the signal received at the m th frequency bin. Adding from 0 to Nd; (c5) calculating the size of the complex number resulting from the step (c4); And (c6) to the result of step (c5). And calculating the estimated frequency error by dividing the sampling timing offset for the current frame obtained by multiplying by subtracting the sampling timing offset for the previous frame by the sampling number of the frame.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a sampling clock recovery apparatus in an OFDM receiver according to the present invention. This device has a configuration similar to that of FIG.

The ADC unit 20 converts an input analog pilot signal into a digital signal, and the FFT unit 21 FFTs an input signal to extract a pilot pattern. The frequency detector 22 estimates the sampling frequency error, and the loop filter 23 removes the influence of noise from the estimated sampling frequency error, and determines the convergence property of the entire loop. The PDM modulator 24 converts an input digital signal into an analog value, and the VCXO 25 generates a sampling clock according to the input value.

3 illustrates pilot signals and sampling positions of an OFDM (n-1) th frame and an n th frame. The position where the original signal is sampled for transmission and the position where the received signal is simplified are indicated by solid and dotted arrows, respectively.

The pilot signal to be transmitted is called c (k), and the signal received and sampled is called x (k), and at this time, the Sampling Timing Offset (STO) As many exist. In this case, each FFT result is expressed by the following equation.

From here Is a normalized STO, with a value of 1 for one sample error and an intermediate value when sampled in the middle between the original samples. N is the FFT size and m is the frequency bin index. For example, if 255 FFTs are used, the frequency bin index is from 1 to 255.

In the above equation, when the STO is present, the received signal has a phase shift with respect to the original signal. For example, if STO has a value of 0.5, the last frequency bin of the received signal Will have as much phase shift Inverted value is displayed.

Since the phase shift shown in the above equation is caused by the error of the sampling position as shown in FIG. 3, the sampling position offset is calculated by calculating it from the received signal, and the frequency error value is estimated from this value and the STO obtained in the previous frame. Explain this.

Figure 4 shows the flow of operation of the frequency detector according to the present invention.

This operation estimates the sampling offset of the current frame using the plurality of pilot patterns and the corresponding signal before each pilot pattern is FFT (step 40), estimates the sampling offset of the previous frame (step 42), and the steps In operation 44, the estimated sampling offset of the current frame and the estimated sampling offset of the previous frame are obtained.

5 is a block diagram showing the configuration of the frequency detector according to the present invention. The frequency detector includes first to third conjugated units 50, 51, and 52 that conjugate the input pilot pattern, an adder 53 that adds input complex values, and a magnitude of an output complex number of the adder 53. It includes a size calculating section 54 and a frequency error calculating section 55 for calculating the estimated sampling frequency error.

The STO is calculated from the phase shift difference between the mth signal and the (m + d) th signal in the FFT result of the FFT unit 11.

The received signal X (m) at the mth frequency bin is conjugated by the first conjugated unit 50 and multiplied by the signal C (m) which is a signal before the received signal X (m) is FFTed by the FFT unit 21. . The second conjugation unit 51 conjugates the received signal X (m + d) at the (m + d) th frequency bin, multiplies the original signal C (m + d), and multiplies the product by the third conjugation unit 52. Conjugate). If you multiply these two result values, the result is expressed as the following equation.

In this equation, the sampling position offset appears only in the phase part. Therefore, taking the phase component from Multiply by the STO value Can be obtained. In an actual system, STO of the current frame (nth) is an average of values obtained from a plurality of pilot signals in the entire waveform as shown in FIG. Estimate (step 40).

The adder 53 adds the values obtained from the plurality of pilot signals, and the magnitude calculator 54 calculates the magnitude of the complex number which is the value added by the adder 53. And on this result Multiply by the STO value Obtain The result of the above process is expressed by the following equation.

In the same way, the STO of the (n-1) th frame that is the previous frame Obtain (step 42). And in the frequency error calculation unit 55 in The result of subtracting is divided by the sampled number of frames, that is, the size of the FFT, N, gives the estimated sampling frequency error of the current frame (the nth frame). Can be obtained (step 44). This is expressed as the following equation.

The estimated sampling frequency error value is input to the loop filter unit 23.

6 is a block diagram showing the configuration of the loop filter unit. When the estimated sampling frequency error to be input is input, two signals g1 and g2 having the same properties are separated, and the signal g2 is inversely multiplied by the original signal g2, and the result is multiplied by g1 and output. At this time, the loop filter unit 23 reduces the role of noise included in the pilot signal or the estimated sampling frequency error and determines the convergence property of the signal, that is, the signal convergence speed and convergence range.

The output of the loop filter unit 23 is input to the VCXO 25 through the PDM modulation and demodulation unit 24 that converts the digital signal into analog pulses. The PDM demodulator 24 determines the density or duration of the analog pulse output according to the value of the input digital signal and outputs an analog signal corresponding to the input digital signal. You may use a conventional D / A converter for this function.

The VCXO 25 generates a sampling clock corresponding to the value of the analogized input estimated sampling frequency error and feeds it back to the ADC unit 20.

The frequency corresponding to the estimated sampling frequency error is again applied to the ADC unit 20 to obtain the frequency error value as described above. Correct by This process is executed every frame. That is, by feeding back a pilot signal sampled at a frequency adjusted to make the sampling frequency error value obtained in the current frame substantially zero, the frequency error value is made substantially zero. The optimum sampling frequency is then found.

Examples included in the above description are introduced for the understanding of the present invention, and these examples do not limit the spirit and scope of the present invention. It will be apparent to those skilled in the art that various embodiments in accordance with the present invention in addition to the above examples are possible.

Each of the steps of the present invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, CD-RW, magnetic tape, floppy disk, HDD, optical disk, magneto-optical storage, and the like. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

According to the present invention, the sampling frequency offsets of the current and previous frames are obtained by using the sampled pilot signal and the pilot pattern obtained by FFT the sampled signal, and the estimated frequency error is calculated to calculate the frequency error. By feeding back the sampling frequency, the optimum sampling frequency with the minimum error is found, thereby efficiently recovering the sampling clock in the OFDM receiver.

Claims (7)

An apparatus for recovering a sampling clock in an OFDM receiver, An analog-to-digital converter configured to sample the analog OFDM pilot signal according to an input sampling clock signal and convert the analog OFDM pilot signal into a digital signal; An FFT unit extracting a pilot pattern by performing FFT (Fast Fourier Transform) on the output of the analog-digital converter; A frequency detector which calculates an estimated sampling frequency error by obtaining a pilot pattern of a current frame and a pilot pattern of a previous frame by using the pilot pattern and an input signal of the FFT unit corresponding thereto; A loop filter unit which reduces noise of the estimated sampling frequency error and determines a convergence range and a convergence speed of the pilot signal; And And a VCXO for outputting the sampling clock signal according to the output value of the loop filter unit. The method of claim 1, And a digital-analog converter for outputting the analog signal, which is the output of the loop filter unit, to the VCXO for converting the analog signal to a digital signal corresponding thereto. The method of claim 1, wherein the frequency detector Means for estimating a sampling offset of a current frame using the plurality of pilot patterns and input signals corresponding to the FFT unit; Means for estimating a sampling offset of a previous frame by using the plurality of pilot patterns and input signals corresponding to the FFT unit; And Means for calculating an estimated sampling frequency error by obtaining an average per frame of the difference between the estimated sampling offset of the current frame and the estimated sampling offset of a previous frame. . The method of claim 1, wherein the frequency detector Where N is the number of samples in the frame, m is the frequency bin index, and d is the current frame and the previous frame, respectively, when d is a predetermined constant. a first conjugate unit configured to conjugate the signal received at the m th frequency bin; a second conjugate unit configured to conjugate the signal received at the (m + d) th frequency bin; A third conjugated unit configured to conjugate the output signal of the second conjugated unit by the FFT of a signal received at the (m + d) th frequency bin and a complex product of the resultant signal; An adder configured to complex-multiply the result signal of the first conjugated unit by the FFT signal of the signal received at the m-th frequency bin, and add the complex value multiplied by the output of the third conjugated unit from 0 to N-d; A size calculation unit for obtaining a size of a complex number that is a sum of the addition units; And To the output of the size calculator In the OFDM receiver comprising a frequency error calculator for calculating the estimated frequency error by dividing the sampling timing offset for the current frame obtained by multiplying the sampling timing offset for the previous frame by the number of samples of the frame Device to restore the sampling clock of. A method for recovering a sampling clock in an OFDM receiver, (a) sampling the analog OFDM pilot signal according to an input sampling clock signal and converting the analog OFDM pilot signal into a digital signal; (b) extracting a pilot pattern by performing a fast fourier transform (FFT) on the digitally converted signal; (c) calculating an estimated sampling frequency error by obtaining a pilot pattern of a current frame and a pilot pattern of a previous frame by using the pilot pattern and an input signal before FFT corresponding thereto; (d) filtering to reduce noise of the estimated sampling frequency error, and to determine a convergence range and a convergence speed of the pilot signal; And and (e) outputting the sampling clock signal according to the output value of the loop filter unit. The method of claim 5, wherein step (c) Where N is the number of samples in the frame, m is the frequency bin index, and d is a predetermined constant, for each of the current frame and the previous frame. (c1) conjugating the signal received at the m th frequency bin; (c2) conjugating the signal received at the (m + d) th frequency bin; (c3) conjugating the complexed complex number of step (c2) with the result of FFT of the signal received at the (m + d) th frequency bin with a result of complex multiplication; (c4) The value of m is multiplied by the complexed complex number in step (c1) with the complex signal multiplied by the result of FFT of the signal received at the m th frequency bin. Adding from 0 to Nd; (c5) calculating the size of the complex number resulting from the step (c4); And (c6) to the result of step (c5) And calculating the estimated frequency error by dividing the sampling timing offset for the current frame obtained by multiplying the sampling timing offset for the previous frame by the number of samplings of the frame. How to restore the clock. The method of claim 5, wherein step (c) Estimating a sampling offset of a current frame using the plurality of pilot patterns and corresponding signals before the FFT operation in step (b); Estimating a sampling offset of a previous frame by using the plurality of pilot patterns and corresponding signals before the FFT operation of step (b); And Calculating an estimated sampling frequency error by obtaining a per-frame average of the difference between the estimated sampling offset of the current frame and the estimated sampling offset of the previous frame, and calculating an estimated sampling frequency error. .