KR20040038530A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
- Publication number
- KR20040038530A KR20040038530A KR1020020067521A KR20020067521A KR20040038530A KR 20040038530 A KR20040038530 A KR 20040038530A KR 1020020067521 A KR1020020067521 A KR 1020020067521A KR 20020067521 A KR20020067521 A KR 20020067521A KR 20040038530 A KR20040038530 A KR 20040038530A
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- semiconductor substrate
- oxide film
- film
- forming
- concentration impurity
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 15
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 description 10
- 230000010354 integration Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 기판상의소정 영역에 이온의 확산 속도가 매우 느린 SiGe막을 SEG에 의해 형성하고, 저농도 불순물 영역을 SiGe막상에 형성함으로써 저농도 불순물 영역의 이온이 SiGe막에 의해 채널 영역으로 확산되는 것을 억제할 수 있어 단채널 효과를 최대한 억제할 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a SiGe film having a very slow diffusion rate of ions is formed by SEG in a predetermined region on a semiconductor substrate, and a low concentration impurity region is formed on a SiGe film, whereby ions in a low concentration impurity region are formed. The present invention relates to a method for manufacturing a semiconductor device which can suppress diffusion into a channel region by a film and can suppress a short channel effect to the maximum.
반도체 소자의 집적도가 향상될수록 소오스와 드레인의 거리가 짧아지게 되고, 이에 따라 단채널 효과(short channel effect)가 발생하게 된다. 이러한 단채널 효과로 인하여 소자의 문턱 전압이 급격하게 감소하거나 오프 전류(off current)가 증가하게 되어 소자의 신뢰성을 저하시키게 될 뿐만 아니라 고집적화에 장애로 작용하게 된다.As the degree of integration of the semiconductor device is improved, the distance between the source and the drain becomes shorter, thereby causing a short channel effect. Due to such a short channel effect, the threshold voltage of the device is drastically reduced or the off current is increased, thereby degrading the reliability of the device and acting as a barrier to high integration.
단채널 효과를 방지하기 위해 LDD 구조의 접합 영역을 형성하기 위한 저농도 불순물 영역에 주입된 이온들이 채널 영역으로 확산되는 것을 방지하는 노력이 시행되고 있다. 이러한 노력의 일환으로 저농도 불순물 영역을 형성하기 위한 이온 주입 공정을 극히 낮은 에너지(ultra low energy)를 이용하여 실시하거나 소오스 및 드레인 영역을 형성하기 위한 열처리 공정으로 스파이크 RTA를 적용하여 저농도 불순물 영역에 주입된 이온의 확산을 최대한 억제한다. 그러나, 극히 낮은 에너지를 이용하여 저농도 불순물 이온을 주입할 경우 원하는 양의 이온이 주입되지 않을 수도 있으며, 스파이크 RTA를 적용하면 원하는 깊이까지 확산 영역을 확장시키지 못할 수도 있다.In order to prevent the short channel effect, efforts have been made to prevent the ions implanted into the low concentration impurity region to form the junction region of the LDD structure into the channel region. As part of this effort, an ion implantation process for forming low concentration impurity regions is performed using ultra low energy or a heat treatment process for forming source and drain regions, and spike RTA is applied to low concentration impurity regions. Suppresses the diffusion of ions as much as possible. However, when implanting low concentration impurity ions using extremely low energy, a desired amount of ions may not be implanted, and spike RTA may not extend the diffusion region to a desired depth.
본 발명의 목적은 저농도 불순물 영역이 형성될 영역에 이온의 확산 속도가 매우 느린 SiGe막을 형성하고 SiGe막내에 저농도 불순물 영역을 형성함으로써 단채널 효과의 발생을 방지할 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing the occurrence of a short channel effect by forming a SiGe film having a very slow diffusion rate of ions in a region where a low concentration impurity region is to be formed and a low concentration impurity region in the SiGe film. It is.
본 발명에 따른 반도체 소자의 제조 방법은 반도체 기판 상부에 게이트 산화막, 폴리실리콘막 및 제 1 산화막을 순차적으로 형성하는 단계와, 상기 제 1 산화막, 폴리실리콘막 및 게이트 산화막의 소정 영역을 식각하여 게이트를 패터닝하는 단계와, 상기 폴리실리콘막의 측면 및 상기 반도체 기판 상의 소정 영역에 제 2 산화막을 형성하는 단계와, 상기 제 1 산화막을 마스크로 식각 공정을 실시하여 상기 반도체 기판을 소정 깊이로 식각하는 단계와, 상기 반도체 기판의 식각된 부분에 SiGe막을 형성하는 단계와, 저농도 불순물 이온 주입 공정을 실시하여 상기 SiGe막상에 저농도 불순물 영역을 형성하는 단계와, 상기 게이트 측벽에 스페이서를 형성한 후 고농도 불순물 이온 주입 공정을 실시하여 상기 반도체 기판상의 소정 영역에 고농도 불순물 영역을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention includes the steps of sequentially forming a gate oxide film, a polysilicon film and a first oxide film on a semiconductor substrate, etching a predetermined region of the first oxide film, the polysilicon film and the gate oxide film to gate Forming a second oxide film on a side surface of the polysilicon film and a predetermined region on the semiconductor substrate, and etching the semiconductor substrate to a predetermined depth by performing an etching process using the first oxide film as a mask. And forming a low concentration impurity region on the SiGe layer by forming a SiGe film on the etched portion of the semiconductor substrate, performing a low concentration impurity ion implantation process, and forming a spacer on the sidewall of the gate, and then forming a high concentration impurity ion. A high concentration impurity region is formed in a predetermined region on the semiconductor substrate by performing an implantation process. Characterized in that it comprises a step of forming.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method for manufacturing a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판12 : 게이트 산화막11: semiconductor substrate 12: gate oxide film
13 : 폴리실리콘막14 : 제 1 산화막13 polysilicon film 14 first oxide film
15 : 제 2 산화막16 : SiGe막15 Second Oxide Film 16 SiGe Film
17 : 저농도 불순물 영역18 : 제 3 산화막17 low concentration impurity region 18 third oxide film
19 : 질화막20 : 고농도 불순물 영역19: nitride film 20: high concentration impurity region
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써 본 발명을 상세히 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예는 본발명의 개시가 완전하도록 하며, 이 기술 분야에서 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 또한, 도면상에서 동일 부호는 동일 요소를 지칭한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided to fully inform the scope of the invention. In addition, in the drawings, like reference numerals refer to like elements.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a semiconductor device according to the present invention.
도 1(a)를 참조하면, 반도체 기판(11) 상부에 게이트 산화막(12), 폴리실리콘막(13) 및 제 1 산화막(14)을 순차적으로 형성한다. 이때, 제 1 산화막(14)은 300∼1000Å 정도의 두께로 형성한다. 게이트 마스크를 이용한 리소그라피 공정 및 식각 공정으로 제 1 산화막(14), 폴리실리콘막(13) 및 게이트 산화막(12)의 소정 영역을 식각하여 게이트를 패터닝한다. 그리고, 열산화 공정을 실시하여 폴리실리콘막(13)의 측면 및 반도체 기판(11)상에 30∼100Å 정도의 제 2 산화막(15)을 형성한다. 이때, 제 2 산화막(15)은 열산화 공정을 실시하지 않고 증착 공정으로 형성할 수도 있다.Referring to FIG. 1A, the gate oxide film 12, the polysilicon film 13, and the first oxide film 14 are sequentially formed on the semiconductor substrate 11. At this time, the first oxide film 14 is formed to a thickness of about 300 to 1000 GPa. The gate is patterned by etching a predetermined region of the first oxide film 14, the polysilicon film 13, and the gate oxide film 12 by a lithography process and an etching process using a gate mask. Then, a thermal oxidation step is performed to form a second oxide film 15 of about 30 to 100 Å on the side surface of the polysilicon film 13 and the semiconductor substrate 11. In this case, the second oxide film 15 may be formed by a deposition process without performing a thermal oxidation process.
도 1(b)를 참조하면, 제 1 산화막(14)을 마스크로 반도체 기판(11)을 식각한다. 이때의 식각 공정은 방향성이 있는 건식 식각 공정으로 실시하여 폴리실리콘막(13) 측면에 형성된 제 2 산화막(15)은 식각되지 않으면서 반도체 기판(11)이 300∼800Å 정도의 깊이로 식각되도록 한다. 한편, 이러한 식각 공정은 반도체 기판(11)과 제 1 산화막(14)의 식각 선택비를 조절하여 제 1 산화막(14)이 모두 제거되지 않도록 한다. 그리고, 선택적 에피택셜 성장법(Selective Epitaxial Growth; SEG)을 이용하여 식각된 반도체 기판(11)상에 SiGe막(16)을 형성한다. 이때, SEG 공정에 의한 SiGe막(16)은 600∼750℃의 온도에서 디클로로 실란(dichloro silane; DCS)과 HCl을 이용하여 형성한다. 한편, 디클로로 실란 대신에 SiH4또는 Si2H6를 이용할 수 있으며, HCl 대신에 Cl을 이용할 수 있다. 그리고, SiGe막(16)의 성장 두께는 반도체 기판(11)의 식각 깊이와 같도록 하는데, 예를들어 300∼800Å의 두께로 형성한다. 저농도 불순물 이온 주입 공정을 실시하여 SiGe막(16)상에 저농도 불순물 영역(17)을 형성한다.Referring to FIG. 1B, the semiconductor substrate 11 is etched using the first oxide film 14 as a mask. At this time, the etching process is performed by a dry etching process with a direction so that the semiconductor substrate 11 is etched to a depth of about 300 to 800 kPa without etching the second oxide film 15 formed on the side of the polysilicon film 13. . On the other hand, such an etching process controls the etching selectivity of the semiconductor substrate 11 and the first oxide film 14 so that not all of the first oxide film 14 is removed. Then, the SiGe film 16 is formed on the etched semiconductor substrate 11 by using selective epitaxial growth (SEG). At this time, the SiGe film 16 by the SEG process is formed using dichloro silane (DCS) and HCl at a temperature of 600 ~ 750 ℃. Meanwhile, SiH 4 or Si 2 H 6 may be used instead of dichloro silane, and Cl may be used instead of HCl. The growth thickness of the SiGe film 16 is equal to the etching depth of the semiconductor substrate 11, for example, is formed to a thickness of 300 to 800 kPa. A low concentration impurity ion implantation process is performed to form a low concentration impurity region 17 on the SiGe film 16.
도 1(c)를 참조하면, 전체 구조 상부에 제 3 산화막(18) 및 질화막(19)을 형성한 후 전면 식각 공정을 실시하여 게이트 패턴 측면에 스페이서를 형성한다. 그리고 고농도 불순물 이온 주입 공정을 실시하여 고농도 불순물 영역(20)을 형성한다. 이에 의해 저농도 불순물 영역(17) 및 고농도 불순물 영역(20)이 중첩된 접합 영역이 형성된다.Referring to FIG. 1C, after forming the third oxide film 18 and the nitride film 19 on the entire structure, a spacer is formed on the side surface of the gate pattern by performing an entire surface etching process. The high concentration impurity ion implantation process is performed to form the high concentration impurity region 20. As a result, a junction region in which the low concentration impurity region 17 and the high concentration impurity region 20 overlap each other is formed.
상술한 바와 같이 본 발명에 의하면 반도체 기판상의 소정 영역에 이온의 확산 속도가 매우 느린 SiGe막을 SEG에 의해 형성하고, 저농도 불순물 영역을 SiGe막상에 형성함으로써 저농도 불순물 영역의 이온이 SiGe막에 의해 채널 영역으로 확산되는 것을 억제할 수 있어 단채널 효과를 최대한 억제할 수 있다.As described above, according to the present invention, a SiGe film having a very slow diffusion rate of ions is formed by SEG in a predetermined region on a semiconductor substrate, and a low concentration impurity region is formed on the SiGe film, whereby ions in the low concentration impurity region are channeled by the SiGe film. Diffusion can be suppressed and the short channel effect can be suppressed as much as possible.
Claims (7)
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