KR20040036759A - FABRICATION METHOD FOR PLANAR LIGHTWAVEGUIDE USING OF Si ETCHING - Google Patents

Abstract

PURPOSE: A method for manufacturing a planar optical waveguide by using a silicon etching is provided to rapidly etch at a high speed by using the etch of silicon substrate. CONSTITUTION: A method for manufacturing a planar optical waveguide by using a silicon etching includes the steps of: coating a photoresist layer on a silicon substrate; etching the silicon substrate along the optical waveguide pattern formed on the photoresist layer; removing the photoresist layer formed on the silicon substrate by using the etching process and oxidizing the silicon substrate; depositing the core layer on the oxidized silicon substrate; performing the planarization by removing the core layer by a chemical mechanical polishing(CMP); and depositing an over-clad layer on the planarized core layer.

Description

FABRICATION METHOD FOR PLANAR LIGHT WAVEGUIDE USING OF Si ETCHING

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar optical waveguide manufacturing method using silicon etching, and more particularly, to a planar optical waveguide manufacturing method using silicon (Si) etching, in which an etching reaction occurs easily by using an etching of a silicon substrate, so that the speed of the etching process may be accelerated. It is about.

In general, silica (SiO ₂ ) optical waveguide among optical devices is the same material as optical fiber, and its optical loss is very good with light loss of 0.01㏈ / cm or less, and is very stable to environmental changes such as temperature, humidity, etc. Device process can be used as it is, mass production, low cost is possible. In addition, since the waveguide mode is similar to the optical fiber, the connection loss with the optical fiber is small, which is a lot of recent research.

Generally, silica deposition methods include chemical vapor deposition (CVD), sputtering, sol-gel deposition, and flame hydrolysis (FHD). Flame Hydrolysis Deposition) is used.

However, in order to use silica in an optical integrated circuit, under-cladding (˜10 μm), core (˜7 μm), and over cladding (˜15 μm) Since the silica needs to be deposited with a thickness of 20 to 30 μm, the deposition rate is very important in the selection of equipment. Therefore, generally, the FHD method and the CVD method (especially PECVD) are used to deposit silica for optical waveguides.

The deposition rate of the FHD method is about 0.5 ~ 1㎛ / min, the method burns hydrogen and oxygen to make a flame, and then burns together gases such as SiCl ₄ , GeCl ₄ in the flame 10 ~ 100nm SiO _{2 It} is a method of forming fine powder (Soot). The SiO ₂ micropowder is then deposited onto a silicon substrate and made at a high temperature of 1350 ° C. or higher.

This has the advantage of very fast deposition rate, but the thickness uniformity (5%) of the deposited film is lower than that of the CVD method (2-3%), and the product yield is very low when entering mass production due to the large process change. There are disadvantages to losing.

On the other hand, the CVD method is a general method used in silicon electronic device technology, it is possible to make a good quality film, it can have an excellent thickness uniformity of 2 to 3%. However, the ordinary CVD method is not used well because its deposition rate is very slow at 10 to 20 nm / min, and PECVD with a deposition rate of 200 to 300 nm / min is mainly used.

In recent years, HDP-CVD (High Density Plasma CVD) using high density plasma has been used among PECVD methods, thereby making it possible to produce a much better silica film in terms of deposition rate and film properties.

1A to 1D are diagrams illustrating a manufacturing process of manufacturing a planar optical waveguide device using a general PECVD method or an FHD method. As shown in FIG. 1A, first, an under clad layer is deposited on a Si substrate with a thickness of 10 to 15 μm with SiO ₂ .

As shown in FIG. 1B, a core layer is deposited on the under cladding layer with SiO ₂ doped with germanium (Ge) to a thickness of 6 μm to 10 μm. Here, the core layer deposits a material having a higher refractive index than the under cladding layer.

Next, as shown in FIG. 1C, a waveguide pattern is formed through a photo process, and the core layer is etched leaving only the waveguide portion.

Finally, as shown in FIG. 1D, SiO ₂ of the over clad layer is deposited on the under cladding layer and the waveguide formed after etching to have a finish of about 10 μm. Here, the under cladding layer and the over cladding layer have the same refractive index, and only the core layer of the formed waveguide increases the refractive index so that total reflection occurs and propagates when light passes through the waveguide.

If the method of forming the planar optical waveguide is applied to the FHD method, each of the SiO ₂ films is deposited and then subjected to a solidification process.

On the other hand, the etching method, it may be divided into two types of wet etching and dry etching. Wet etching is an etching method using an etchant, and isotropic etching is generally performed.

Dry etching is expressed in two ways: etching by chemical reaction between active particles and the target material to be etched in the plasma, and removing and removing the target material by physical ion bombardment.

FIG. 2 is a view illustrating etching reactions using chemical reactions and etching reactions due to physical impacts in dry etching using a plasma. As shown in the drawing, etching by chemical reaction is performed isotropically as in wet etching, but etching due to physical ion bombardment is anisotropic.

Silica anisotropic etching techniques are usually etched with the aid of chemical reactions and ion bombardment.

Usually, a gas containing carbon and fluorine atoms is used as a reaction gas. Fluorine is used as an etching element that reacts with a silicon atom to form a highly volatile reactant and desorbs it.

Carbon, on the other hand, forms a C-F-based polymer and has an effect of inhibiting etching, which acts as an important factor for obtaining selectivity in the etching reaction.

3 is a diagram illustrating SiO ₂ anisotropic etching using a fluorocarbon gas. As shown here, carbon, a byproduct of the reaction, forms a polymer, which deposits entirely on the SiO ₂ surface. At this time, if a bias is applied to the substrate side, ions having high kinetic energy collide perpendicularly to the substrate, and polymers are detached from the surface where the collision occurs and the substrate may be exposed while etching. On the other hand, since there is no collision at the side of the etched portion, the polymer is continuously deposited, and the etching reaction is suppressed to enable vertical etching.

In addition, the collision effect weakens the SiO ₂ structure and continues the etching reaction at a high speed, and thus, anisotropic etching occurs because the etching speed of the vertical portion is much faster than the other surfaces.

In the case of silica, the Si-O bond is 200 ㎉ / mol, which has a bond strength more than twice that of 80 ㎉ / mol of the Si-Si bond, so that even if the F group is adsorbed at the SiO ₂ interface, positively charged argon or helium This is because the Si-O chain can be broken by penetrating the SiO ₂ interface only with the impact energy of.

In addition, since the Si-O bonding energy is large, even if a high density plasma equipment is used as the etching equipment, the etching rate has only a value of about 300 nm / min.

As such a low etching rate and accelerated ion collisions are required, the etching mask used to form the waveguide pattern uses a hard mask such as hard metal (aluminum, chromium) or amorphous silicon.

In manufacturing the waveguide, the process of depositing and etching the hard mask has a problem that the etching speed is slow and the process is long.

The present invention has been made to improve the above problems, to provide a method for manufacturing a planar optical waveguide using silicon etching that can be easily etched reaction using the etching of the silicon substrate to speed up the etching process. There is this.

1A to 1D illustrate a manufacturing process of manufacturing a planar optical waveguide device using a general PECVD method or an FHD method.

2 is a view showing an etching reaction by etching and physical impact using a chemical reaction in dry etching using a conventional plasma.

3 illustrates SiO ₂ anisotropic etching using carbon fluoride gas.

4A to 4F are views illustrating a manufacturing process of a planar optical waveguide using silicon etching according to the present invention.

In order to achieve the above object, a planar optical waveguide manufacturing method using silicon etching according to the present invention,

Coating a photosensitive film on which a waveguide pattern is formed on the silicon substrate through a photo process;

Etching the silicon substrate according to the waveguide pattern of the coated photoresist;

Removing and oxidizing the photosensitive film of the silicon substrate on which the pattern of the waveguide is formed by the etching;

Depositing a core layer on the oxidized silicon substrate by forming the waveguide pattern;

Forming a planarization of the deposited core layer while removing core layers other than the waveguide patterned by a CMP process;

And characterized by depositing an over clad layer on the planarized substrate.

Here, in particular, it is characterized in that it uses wet oxidation, dry oxidation or high pressure oxidation in the step of oxidizing the silicon.

According to the present invention, by using the etching of the silicon substrate, the etching reaction occurs easily, so that the speed of the etching process is fast to improve the reliability of the optical waveguide.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A to 4F are views illustrating a manufacturing process of a planar optical waveguide using silicon etching according to the present invention. As shown in FIG. 4A, the photosensitive film is coated by patterning only a portion where the waveguide is to be formed on the silicon substrate through a photo process.

And, as shown in Figure 4b, the step of etching the silicon substrate in accordance with the waveguide pattern of the coated photosensitive film. Here, in etching the silicon substrate, a separate hard mask is etched by dry etching or wet etching to a thickness of about 7 μm without the need for the etching.

Subsequently, as illustrated in FIG. 4C, the photoresist of the silicon (Si) substrate on which the waveguide pattern is formed by the etching is removed and oxidized. Here, the silicon (Si) substrate is oxidized to a thickness of 15 ~ 20㎛, as a method of oxidizing the silicon (Si) substrate using a common oxidation method such as wet oxidation, dry oxidation, high pressure oxidation.

Next, as shown in FIG. 4D, a core layer is deposited with SiO ₂ on the silicon (Si) substrate on which the waveguide pattern is formed. Here, the core layer is deposited with a material having a higher refractive index than the silicon substrate.

As shown in FIG. 4E, planarization is performed through a CMP process so that only the core layer remains on the pattern formed on the silicon (Si) substrate to form a waveguide.

Here, the CMP (Chemical Mechanical Polishing) process refers to a polishing process in which mechanical removal processing and chemical removal processing are mixed in one processing method. The CMP is an essential process for manufacturing a submicron scale semiconductor chip together with a Plasma Enhanced Chemical Vapor Deposition (PECVD) and a RIE process.

In the semiconductor process, the main role of the CMP is to form a wide planarization of each layer in order to obtain a three-dimensional shape degree, and in order to do the above, the ILD (Inter Layer Dielectric) CMP and the metal CMP Must be applied continuously on the surface of all device layers. In the polishing process of CMP, mechanical and chemical actions are simultaneously performed to cause interaction with each other.

The basic concept of CMP is to polish the object by combining the advantages of these two processes.

As mentioned above, the CMP process is generally divided into an ILD (Interlayer Insulation Film) CMP process and a metal CMP. SiO ₂ (silica) is mainly used as the interlayer insulation film, and the CMP process is very common. .

Subsequently, an over clad layer is deposited after the planarization process, as shown in FIG. 4F. Here, the deposition method of the core layer and the over cladding layer uses PECVD or FHD.

As described above, in the method of etching a silicon (Si) substrate, the bonding force of Si-Si (80 kPa / mol) has a relatively lower bonding force than that of Si-O (200 kPa / mol). It has a very large etching rate.

It can be seen that when using the same high-density plasma equipment as the silica dry etching equipment, the etching rate has a value of about 3 μm / min, and the etching rate of 300 nm / min is very fast compared to silica.

In addition, the photoresist and the silicon etching selectivity is very high, there is an advantage that the photoresist used in the photo process can be used as an etching mask as it is.

While etching, the etching cross section can be maintained vertically, which can simplify the process except for the deposition and etching of hard mask materials.

In addition, silicon may be wet etched with an etchant such as a KOH aqueous solution, and isotropic etching is performed. However, in the case of single crystal silicon etching through a KOH aqueous solution, since the etching speed is different according to each crystal direction, the surface has the fastest etching speed.

Anisotropic wet etching of single crystal silicon substrates is a very difficult technique because the structures must be patterned by precisely aligning the crystal directions, and only simple patterning of structures can be achieved, but there is an advantage that an expensive semiconductor etching equipment is not required.

Even in oxidizing the silicon substrate in which the pattern is formed, it is possible to oxidize tens to hundreds of sheets at a time in ordinary oxidizing equipment, thereby lowering the process cost through mass production.

Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in the planar optical waveguide manufacturing method using silicon (Si) etching according to the present invention, an etching reaction may be easily performed by using an etching of a silicon substrate, thereby speeding up the etching process.

Claims (2)

Coating a photosensitive film on which a waveguide pattern is formed on the silicon substrate through a photo process; Etching the silicon substrate according to the waveguide pattern of the coated photoresist; Removing and oxidizing the photosensitive film of the silicon substrate on which the pattern of the waveguide is formed by the etching; Depositing a core layer on the oxidized silicon substrate by forming the waveguide pattern; Forming a planarization of the deposited core layer while removing core layers other than the waveguide patterned by a CMP process; And depositing an over clad layer on the planarized substrate. The method of claim 1, Method of manufacturing a planar optical waveguide using silicon etching, characterized in that using the wet oxidation, dry oxidation or high pressure oxidation in the step of oxidizing the silicon.