KR20040036415A - Method of manufacturing a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to improve contact resistance between an upper electrode and a metal interconnection by depositing a metal layer on the upper electrode and by electrically connecting the metal interconnection with the upper electrode by the metal layer. CONSTITUTION: A lower electrode(16) for forming a cylindrical capacitor is formed on a semiconductor substrate in which a cell area and a peripheral circuit area are defined. A dielectric layer(18) is formed to form the cylindrical capacitor. A reaction preventing layer is deposited on the resultant structure. The upper electrode is deposited on the reaction preventing layer. A metal layer is deposited on the upper electrode. The metal layer is patterned to form a capacitor on the cell area and to form a stacked structure in a prescribed peripheral circuit area adjacent to the cell area wherein the reaction preventing layer, the upper electrode and the metal layer are sequentially formed. An interlayer dielectric(14) is formed on the resultant structure. The peripheral circuit area is partially etched to form the first contact for contacting the upper electrode and to form the second contact for contacting the semiconductor substrate or a lower metal interconnection(13) formed on the semiconductor substrate. An upper metal interconnection is formed on the resultant structure.

Description

Method of manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving the resistance between an upper electrode of a capacitor portion and a metal wiring during a process for manufacturing a highly integrated semiconductor device of less than 0.13 kW.

In the case of the cup type capacitor, unlike the capacitor structure of the cylinder type, the upper electrode is deposited on the oxide layer because the oxide layer in the peripheral region is not etched. In addition, in the case of the cup-type capacitor, a tantalum insulating material is used to secure the capacity of the capacitor, and TiN or the like is deposited as a reaction prevention film to suppress a reaction between silicon and tantalum, the upper electrode material. The upper electrode has a structure such as silicon / metal wiring.

The upper electrode is electrically connected by the deposition of metal wires after the contact hole etching. In general, the contact hole for electrical connection of the upper electrode is formed as the contact hole etching is formed for the electrical connection of the silicon substrate or the lower metal wiring. As the degree of integration increases, the height of the capacitor increases, and the height difference between the contact hole for electrically connecting the upper electrode of the capacitor and the contact hole for electrically connecting the silicon substrate or the lower metal wiring increases. .

For this reason, if a metal wiring is deposited after performing a contact hole etching process for electrically connecting the upper electrode, it is difficult to secure stable resistance between the upper electrode and the metal wiring.

In addition, when the formation surface after the subsequent metal wiring process is performed, the contact between the upper electrode of the capacitor and the metal wiring is filled with a side contact (the inside of the contact hole is filled with a metal wiring material, and the upper electrode is formed with the metal wiring material and the side surface of the contact hole. Is in contact). At this time, the contact resistance between the metal wiring and the upper electrode is determined by the contact between the reaction prevention film TiN and the metal wiring.

The contact between the upper electrode and the metal wiring of this type tends to greatly deteriorate the physical properties of the upper electrode surface because the upper electrode opened during the formation of the high step contact is continuously affected by the etching gas. Therefore, the contact resistance between the metal wiring and the upper electrode largely depends on the contact area between the upper electrode materials, whether or not the TiN is cleaned or the interface state (the extent to which the upper electrode is exposed to the etch gas upon contact hole etching). In addition, due to the weak interfacial properties, the resistance rapidly increases due to the formation of hydrogen compounds between interfaces due to H ₂ in the intermetallic dielectric (IMD) oxide film during passivation annealing.

In consideration of these effects, a method of applying an oxide film having low outgassing, such as H ₂ , as an IMD is being used.The upper electrode is formed when a high stepped contact hole is formed by increasing the selectivity between the upper electrode and the oxide film. There have been proposed methods for preventing the opening. However, since the contact resistance between the upper electrode and the metal wiring is determined by the contact between the reaction prevention layer TiN and the metal wiring of the upper electrode, it is very important that the etching is stopped on the upper TiN of the upper electrode when etching the contact hole. If the etching is stopped on the silicon of the upper electrode in some regions, the distribution of resistance between the upper electrode and the metal wiring is very large.

Accordingly, the present invention is to solve the above problems by depositing a metal film on the upper electrode, the electrical connection between the metal wiring and the upper electrode through the metal film to improve the contact resistance between the upper electrode and the metal wiring It is an object of the present invention to provide a method for manufacturing a device.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor structure 12 contact plug

13: lower metal wiring 14, 28: interlayer insulating film

16 lower electrode 18 dielectric film

20: reaction prevention film 22: upper electrode

24 metal film 26 capacitor

30, 32: contact hole 34: upper metal wiring

Forming a lower electrode for forming a capacitor of a cylinder structure on a semiconductor substrate having a cell region and a peripheral circuit region defined therein, forming a dielectric film for forming the capacitor of the cylinder structure, Depositing a reaction layer on the reaction layer, depositing an upper electrode on the reaction layer, and depositing and patterning a metal layer on the upper electrode to form a capacitor on the cell region, and to form a capacitor adjacent to the cell region. Forming a structure in which the reaction prevention film, the upper electrode, and the metal film are sequentially stacked in the peripheral circuit area, forming an interlayer insulating film over the entire structure, and etching a part of the peripheral circuit area to etch the upper part A first contact for contact with an electrode and a semiconductor formed on the semiconductor substrate or the semiconductor substrate; Provides a method for producing a semiconductor device, it characterized in that the pohamneun forming an upper metal line to the first stage and the entire upper structure to form a second contact for contact with the metal wiring.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 1A, a semiconductor structure 10 in which a cell region A and a peripheral circuit region B are defined and a contact plug 12 or a lower metal wiring 13 for connecting with a capacitor or an upper metal wiring is formed. The first interlayer insulating film 14 is deposited on top. A portion of the first interlayer insulating layer 14 of the cell region A is removed to form a cylinder, so that the lower contact plug 12 is exposed. The lower electrode 16 is formed using a conductive material in the cylinder of the cell region A, and the dielectric film 18 is deposited using a tantalum insulating material.

Referring to FIG. 1B, a tantalum-based insulating material is deposited on the entire structure including the cell region A and the peripheral circuit region B to suppress the reaction of the dielectric layer 18. The conductive material is deposited to a thickness such that a cylinder is sufficiently embedded in the reaction prevention film 20, and then planarized to form the upper electrode 22. A metal film 24 is formed on the upper electrode 22 to improve contact resistance between the upper metal wiring and the upper electrode 22, and the reaction prevention film 20, the upper electrode 22, and the metal film 24 are formed. Is formed to form a capacitor 26 in which the metal film 24 is formed on the upper electrode 22 in the cell region A, and the upper electrode 22 for connection with the upper metal wiring in the peripheral circuit region B. A part of (the metal film 24 is formed in the upper part) protrudes.

Specifically, the reaction prevention film 20 is formed using TiN to suppress the reaction between the dielectric film 18, which is a tantalum insulating material, and silicon, which is a conductive material generally used as the upper electrode 22. The thickness of the reaction prevention film 20 is formed so thin that step coverage does not occur. The upper electrode 22 is formed by depositing silicon to a thickness sufficient to fill a cylinder, and then planarizing it by performing chemical mechanical polishing (CMP). The metal film may be formed using tungsten (W), aluminum (Al), titanium (Ti), or TiN to perform physical vapor deposition (PVD) or chemical vapor deposition (CVD). ) Formed on top. When the metal film 240 is deposited by using a PVD process, the Ar or N ₂ gas is deposited using a deposition gas under a voltage of 1 to 20 KW, a deposition pressure of 0.1 to 100 mTorr, and a deposition temperature of 0 to 500 ° C. In the case of deposition using a CVD process, a gas of WF ₆ , titanium-chlorine (Ti-Cl) series, aluminum-chlorine (Al-Cl) series gas under a pressure of 1 to 500 Torr and a deposition temperature of 300 to 800 ° C. Or by using Ti-Alkoxide gas. In the manufacturing of the capacitor 26 having the metal film 24 formed on the upper electrode 22, a buffer oxide etch (BOE) may be used as a pre-cleaning process of the material of the metal film 24. Alternatively, a wet process using Dilute HF (DHF) is performed, or a dry etching process using RF-Etch or reactive plasma is performed.

Referring to FIGS. 1C and 1D, a second interlayer insulating layer 28 is deposited on the entire structure, and then a portion of the second interlayer insulating layer 28 in the peripheral circuit region B is etched to form an upper electrode of the capacitor 26. 22 and the first contact hole 30 for contact between the upper metal wiring 34 and the lower metal wiring 13 and the upper metal wiring 34 of the peripheral circuit region B or the lower silicon substrate (not shown). And a second contact hole 32 for contact between the upper side and the upper metal wiring 34. The upper metal wiring 34 is formed by performing a metal plating process on the entire structure in which the first and second contact holes 30 and 32 are formed.

Specifically, a photoresist layer is coated on the second interlayer insulating layer 28 and then a photolithography process is performed using a mask for forming a contact hole to form a photoresist pattern (not shown). An etching process using the photoresist pattern as an etch mask is performed to remove the second interlayer insulating layer 28 and the metal layer 24 to form a first contact hole 30, and to form the second interlayer insulating layer 28 and the first. The interlayer insulating layer 14 is removed to form the second contact hole 32. In this case, the first and second contact holes 30 and 32 are formed at the same time, the first contact hole 30 and the second contact hole 32 are formed to the same depth by adjusting the etching selectivity, or the first contact. The hole 30 exposes the upper electrode 22 and the second contact hole 32 forms the lower metal wiring 13 or the lower silicon substrate. That is, since the first and second interlayer insulating layers 14 and 28 are formed of an oxide film and the upper electrode 22 is of silicon, an etching process having a high etching selectivity between the oxide film and silicon is performed to perform the first contact hole 30. ) And the depth between the second contact hole 32 can be controlled. Since the first contact hole 30 and the second contact hole 32 are formed at the same time, the upper electrode 22 below the first contact hole 30 may have a thickness of about 100 to 2000 kW when the second contact hole 32 is etched. Is removed.

After the formation of the first and second contact holes 30 and 32, a pre-cleaning process such as a high frequency etching process or a wet etching process using BOE is performed to improve the opening characteristics of the material of the metal wiring 34 before the upper metal wiring 34 is deposited. Conduct. When performing a high frequency etching process, a bias voltage applied to the semiconductor structure 10 by applying a first power of 200 to 600 watts (W) and a second power of 0 to 200 W (Bias Power). Let it be -50 to -200V.

As described above, in the present invention, a metal film is formed on the upper electrode of the capacitor formed in the cell region, and thus the contact between the upper electrode and the upper metal wiring may be made of metal.

Since the contact between the upper electrode and the upper metal wiring is made of metal, the contact resistance between the upper electrode and the upper metal wiring can be improved.

Claims (7)

(a) forming a lower electrode for forming a capacitor of a cylinder structure on a semiconductor substrate in which a cell region and a peripheral circuit region are defined; (b) forming a dielectric film for forming the capacitor of the cylinder structure; (c) depositing a reaction prevention film over the entire structure; (d) depositing an upper electrode on the reaction prevention film; (e) depositing a metal film on the upper electrode and then patterning the capacitor to form a capacitor on the cell region, and in the predetermined peripheral circuit region adjacent to the cell region, the reaction prevention film, the upper electrode and the metal film are sequentially Forming a stacked structure; (f) forming an interlayer insulating film over the entire structure; etching a portion of the peripheral circuit region to form a first contact for contact with the upper electrode and a second contact for contact with the semiconductor substrate or a lower metal wiring formed on the semiconductor substrate; And (h) forming a top metal wiring on the entire structure. The method of claim 1, wherein step (g) And dry etching using a high etching selectivity between the upper electrode and the interlayer insulating layer formed in the peripheral circuit region, thereby simultaneously forming the first contact and the second contact. The method of claim 1, And the metal film is formed on the upper electrode by performing a physical vapor deposition or chemical vapor deposition process using tungsten (W), aluminum (Al), titanium (Ti) or TiN. The method of claim 3, wherein The physical vapor deposition process is a method of manufacturing a semiconductor device characterized in that using the argon (Ar) or N ₂ gas as a deposition gas under a voltage of 1 to 20KW, a deposition pressure of 0.1 to 100mTorr and a deposition temperature of 0 to 500 ℃. . The method of claim 3, wherein The chemical vapor deposition process is WF ₆ , titanium-chlorine (Ti-Cl) -based gas, aluminum-chlorine (Al-Cl) -based gas or Ti-Alkoxide under a pressure of 1 to 500 Torr and deposition temperature of 300 to 800 ℃ A method of manufacturing a semiconductor device, comprising using a gas. The method of claim 1, wherein between step (d) and step (e), A method of manufacturing a semiconductor device, the method comprising: performing wet etching using BOE or DHF, or performing dry etching using high frequency etching or reactive plasma. The method of claim 1, wherein between step (g) and step (h), A high frequency etching process or wet etching using BOE by applying a first power of 200 to 600 watts (W) and a second power of 0 to 200 W so that the bias voltage applied to the semiconductor structure is -50 to -200 V. Method for manufacturing a semiconductor device, characterized in that it further comprises the step of.