KR20040036341A - High Sensivity photodetector using High Electron Mobility Transistor - Google Patents
High Sensivity photodetector using High Electron Mobility Transistor Download PDFInfo
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- 238000005215 recombination Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000011149 active material Substances 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
Description
본 발명은 고전자 이동도 트랜지스터를 이용한 고감도 수광소자에 관한 것으로, 보다 자세하게는 종래의 수광소자로 사용되고 있는 PIN 포토다이오드에 비하여 감도가 우수하고 응답특성이 빠른 고전자 이동도 트랜지스터를 사용하여 수광소자로 활용하며, 게이트 전압을 조절하여 감도의 최적화를 구현한 수광소자에 관한 것이다.The present invention relates to a high-sensitivity light-receiving element using a high electron mobility transistor, and more particularly, to a light-receiving element using a high-electron mobility transistor having excellent sensitivity and fast response characteristics compared to a PIN photodiode used as a conventional light receiving element. The present invention relates to a light-receiving device that implements optimization of sensitivity by adjusting a gate voltage.
수광소자는 빛 에너지를 전기 에너지로 만드는 광전소자로서, 현재 수직형 구조인 PIN 포토다이오드(Positive-Intrinsic-Negative Photodiode, 이하 PIN 포토다이오드)와 수평적 구조의 MSM 포토다이오드(Metal-Semiconductor-Metal Photodioed, 이하 MSM 포토다이오드)가 주로 사용되고 있는데, MSM 포토다이오드는 상용제품화하기 어려운 특성 때문에 주로 PIN 포토다이오드가 사용되고 있다.Light-receiving devices are photoelectric devices that make light energy into electrical energy.Pinitive-Intrinsic-Negative Photodiodes (PIN photodiodes), which are currently vertical, and MSM photodiodes (Metal-Semiconductor-Metal Photodioeds), which are horizontal structures (Hereinafter, MSM photodiode) is mainly used, but the PIN photodiode is mainly used because the MSM photodiode is difficult to commercialize.
도 1은 이러한 종래의 수광소자인 PIN 포토다이오드의 단면도이다. 전극(1) 위에 입사광의 윈도우 역할을 하는 N+ InP(2) 기판이 있고, 상기 InP 기판(2)위에 In0.53Ga0.47As 성장시의 구조적 결함을 최소화하고 평탄화를 위해 InP 완충층(3)이 형성된다. 상기 완충층(3) 위에 진성층 In0.53Ga0.47As 층(4)이 형성되고, 그 위에 P+ In0.53Ga0.47As층(5)이 형성되며, 상기 P+ In0.53Ga0.47As층(5) 위에 표면 및 계면으로부터의 암전류를 최소화 시키기 위한 InGaAsP 층(6)이 형성되어 있다. 그리고 마지막으로 소자 표면 보호 및 표면에서의 전자와 정공의 재결합을 최소화 시키기 위한 절연체인 질화실리콘층(7)이 있는 구조이다.1 is a sectional view of a PIN photodiode as a conventional light receiving element. There is an N + InP (2) substrate serving as a window of incident light on the electrode 1, and an InP buffer layer 3 is formed on the InP substrate 2 for minimizing structural defects during growth of In 0.53 Ga 0.47 As and planarizing it. do. An intrinsic layer In 0.53 Ga 0.47 As layer 4 is formed on the buffer layer 3, a P + In0.53Ga0.47As layer 5 is formed thereon, and a surface on the P + In0.53Ga0.47As layer 5. And an InGaAsP layer 6 for minimizing dark current from the interface. Finally, the silicon nitride layer 7 is an insulator for protecting the device surface and minimizing recombination of electrons and holes on the surface.
이러한 PIN 포토다이오드가 광전류를 발생시키는 원리는 다음과 같다.The principle that the PIN photodiode generates the photocurrent is as follows.
도 2는 종래 PIN 포토다이오드의 P-I-N층들이 접합하기 전의 에너지 밴드 구조를 나타낸 도식도로서, Ec는 전도대 밴드를, Ev는 충만대 밴드, EFp는 P+층의 페르미 레벨, EFn는 N+층의 페르미 레벨을 나타낸다. 도면에 나타난 바와 같이 각 P+ 층과 진성(I)영역층, N+ 층으로서 각 영역의 페르미 에너지 레벨 위치가 모두 다르게 나타나 있다. 페르미 레벨의 위치는 근본적으로 전자 및 정공의 농도에 따라 결정되는데 전자의 농도가 클수록 전도대 밴드(Ec)에 가까워지게 된다.Figure 2 is a schematic diagram showing the energy band structure before the PIN layer of the conventional PIN photodiode bonded, Ec is the conduction band band, Ev is the full band, E Fp is the Fermi level of the P + layer, E Fn is of the N + layer Indicates Fermi level. As shown in the figure, the Fermi energy level positions of the respective regions are different from each other as the P + layer, the intrinsic (I) region layer and the N + layer. The position of the Fermi level is basically determined by the concentration of electrons and holes. The higher the concentration of electrons, the closer to the conduction band band Ec.
도 3은 종래 PIN 포토다이오드의 P-I-N층들이 접합한 후에 형성되는 공간전하밀도를 나타낸 도식도로서, Nd는 n형의 도핑농도를, Na는 p형의 도핑농도를 나타낸다. 각각의 P-I-N층들이 접합을 하게 되면 각각의 페르미 에너지가 다르기 때문에 전기적 평형상태를 유지하도록 이동을 하게 된다. 즉, P영역의 어셉터(accepter)로부터 정공이, N영역의 도너(donor)로부터 전자들이 이동하면서 각각의 영역에 음이온들과 양이온들을 남기게 되는데 이러한 과정에 의해 형성되는 공간전하분포를 나타내는 것이 도 3이다. 이 때에는 또한 두 영역의 공간전하는 입사광에 의해 형성된 전자 및 정공이 외부회로로 이동하게 할 수 있도록 진성층 영역에 내부 전기장을 형성한다.3 is a schematic diagram showing the space charge density formed after the P-I-N layers of the conventional PIN photodiode are bonded, where Nd represents an n-type doping concentration and Na represents a p-type doping concentration. When the P-I-N layers are bonded to each other, the Fermi energy is different so that they move to maintain the electrical equilibrium. That is, holes from the acceptor of the P region and electrons from the donor of the N region leave anions and cations in each region, which shows the space charge distribution formed by this process. 3 At this time, the space charge of the two regions also forms an internal electric field in the intrinsic layer region so that electrons and holes formed by the incident light can move to the external circuit.
도 4는 종래의 PIN 포토다이오드가 일정한 역방향 바이어스 하에서 광자의 흡수를 통해 광전류를 발생시키는 과정을 나타낸 도식도이다. 진성층 영역에서 입사광의 흡수에 의해 생성된 전자(8)와 정공(9)들은 내부 전기장에 의해서 전자(8)는 N+, 정공(9)은 P+ 영역쪽으로 분리, 이동하게 되고 외부회로에 광전류를 출력하게 된다. PIN 구조는 입사광의 대부분이 진성층 영역에서 흡수되도록 설계되는데 구체적으로 응답속도(response time)와 양자효율(quantum efficiency)의 두 요소를 고려해서 최적화 되어진다. 두 요소의 적절한 절충이 필요한데, 진성층 영역이 두꺼워 질수록 더 많은 광자를 흡수하기 때문에 양자효율은 증가시킬 수 있는 반면 응답속도는 느려진다. 대략적으로 진성 영역층의 두께는 응용에 따라 5~50㎛의 두께를 가진다.4 is a schematic diagram illustrating a process in which a conventional PIN photodiode generates photocurrent through absorption of photons under a constant reverse bias. The electrons 8 and the holes 9 generated by the absorption of incident light in the intrinsic layer region are separated and moved to the N + and the holes 9 to the P + region by the internal electric field, and the photocurrent is applied to the external circuit. Will print. The PIN structure is designed to absorb most of the incident light in the intrinsic region. Specifically, the PIN structure is optimized by considering two factors, response time and quantum efficiency. Proper compromise of the two factors is needed, because thicker regions of the intrinsic layer absorb more photons, which can increase quantum efficiency while slower response. The thickness of the intrinsic region layer is approximately 5-50 μm depending on the application.
그러나 상기와 같은 광전류 발생 메커니즘을 가지는 종래의 PIN 포토다이오드 구조에서는 감도가 약 1A/W로서 한계성이 있다.However, in the conventional PIN photodiode structure having the photocurrent generation mechanism as described above, the sensitivity is limited as about 1 A / W.
따라서, 본 발명은 상기와 같은 종래 기술의 제반 단점과 문제점을 해결하기 위한 것으로, 고전자 이동도 트랜지스터 구조를 이용하여 응답 속도가 빠른 고감도 수광소자를 제공하고, 게이트 전압을 조절함으로써 최적의 감도를 얻을 수 있는 수광소자를 제공함에 본 발명의 목적이 있다.Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, to provide a high-sensitivity light-receiving device with a fast response speed by using a high electron mobility transistor structure, and to adjust the gate voltage to the optimum sensitivity It is an object of the present invention to provide a light receiving element that can be obtained.
도 1은 종래의 수광소자인 PIN 포토다이오드의 단면도이다.1 is a cross-sectional view of a PIN photodiode which is a conventional light receiving element.
도 2는 종래 PIN 포토다이오드의 P-I-N층들이 접합하기 전의 에너지 밴드 구조를 나타낸 도식도이다.Figure 2 is a schematic diagram showing the energy band structure before the P-I-N layers of the conventional PIN photodiode bonded.
도 3은 종래 PIN 포토다이오드의 P-I-N층들이 접합한 후에 형성되는 공간전하밀도를 나타낸 도식도이다.3 is a schematic diagram showing the space charge density formed after the P-I-N layers of the conventional PIN photodiode are bonded.
도 4는 종래의 PIN 포토다이오드가 광전류를 발생시키는 과정을 나타낸 도식도이다.4 is a schematic diagram illustrating a process of generating a photocurrent by a conventional PIN photodiode.
도 5는 본 발명에 의한 고전자 이동도 트랜지스터를 이용한 고감도 수광소자의 단면도이다.5 is a cross-sectional view of a high sensitivity light receiving device using a high electron mobility transistor according to the present invention.
도 6은 본 발명에 의한 고전자 이동도 트랜지스터의 광전류 메커니즘을 나타낸 도식도이다.6 is a schematic diagram showing a photocurrent mechanism of a high electron mobility transistor according to the present invention.
도 7은 본 발명에 의한 고전자 이동도 트랜지스터의 광전류 메커니즘을 나타내는 에너지 밴드 구조도이다.7 is an energy band structure diagram illustrating a photocurrent mechanism of a high electron mobility transistor according to the present invention.
도 8은 본 발명에 의한 고전자 이동도 트랜지스터의 감도특성을 나타낸 것이다.8 shows the sensitivity characteristics of the high electron mobility transistor according to the present invention.
도 9는 본 발명에 의한 고전자 이동도 트랜지스터의 게이트 전압에 따른 감도를 나타낸 것이다.9 illustrates the sensitivity according to the gate voltage of the high electron mobility transistor according to the present invention.
((도면의 주요부분에 대한 부호의 설명))((Explanation of symbols for main parts of drawing))
8. 전자 9. 정공8. Electronic 9. Hole
10. 반절연 InP 기판 11. InP 완충층10. Semi-insulated InP substrate 11.InP buffer layer
12. InP/Al0.48In0.52As 초격자층 13. In0.53Ga0.47As 전도층12.InP / Al 0.48 In 0.52 As Superlattice Layer 13.In 0.53 Ga 0.47 As Conductive Layer
14. 2차원 전자채널층 15. 전위장벽층14. Two-dimensional electron channel layer 15. Potential barrier layer
16. Al0.48In0.52As 전자공여층 17. InP 윈도우층16.Al 0.48 In 0.52 As electron donating layer 17.InP window layer
18. 게이트 19. 전극18. Gate 19. Electrode
본 발명의 상기 목적은 전자 이동도가 실리콘에 비해 수백배나 빠른 고전자 이동도 트랜지스터를 수광소자로 활용한 고전자 이동도 트랜지스터를 이용한 고감도 수광소자에 의해 달성된다.The above object of the present invention is achieved by a high sensitivity light receiving device using a high electron mobility transistor utilizing a high electron mobility transistor as a light receiving element several hundred times faster than silicon.
고전자 이동도 트랜지스터는 높은 전자 이동도를 특징으로 하는 고속 동작에 적합한 트랜지스터로서, 슈퍼컴퓨터의 고속 논리 소자나 기억 장치에 주로 GaAs 등의 화합물 반도체를 헤테로 접합해서 그 접합면을 전자가 고속 이동하는 성질을 이용한 초고속 트랜지스터로서, 본 발명에서는 이 소자를 활용하여 감도가 높고 응답특성이 빠른 수광소자로 적용한다.A high electron mobility transistor is a transistor suitable for high-speed operation characterized by high electron mobility. The heterojunction of a compound semiconductor such as GaAs is mainly performed on a high-speed logic element or a storage device of a supercomputer, where electrons move at a high speed. As an ultra-fast transistor using a property, the present invention is applied to a light receiving device having high sensitivity and fast response characteristics by utilizing this device.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 명세서에 첨부된 도면을 참조한 이하 상세한 설명에 의해 보다명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the accompanying drawings.
먼저, 도 5는 본 발명에 의한 고전자 이동도 트랜지스터를 이용한 고감도 수광소자의 단면도이다.First, Figure 5 is a cross-sectional view of a high sensitivity light receiving device using a high electron mobility transistor according to the present invention.
반절연 InP 기판(10) 위에 구조적 결함 및 암전류를 최소화시키기 위하여 형성된 InP완층층(11)과 InP/Al0.48In0.52As 초격자층(12); 상기 InP/Al0.48In0.52As 초격자층 위에 형성된 In0.53Ga0.47As 전도층(13); 상기 전도층 위에 형성되는 2차원 전자채널층(14); 상기 2차원 전자채널층에 존재하는 자유전자들을 국한시키기 위하여 형성된 전위장벽층(15); 상기 전위장벽층 위에 형성된 n형으로 도핑된 Al0.48In0.52As 전자공여층(16); 상기 Al0.48In0.52As 전자공여층 위에 형성된 InP 윈도우층(17); 상기 윈도우층 위에 형성된 게이트(18) 및 상기 전도층 및 전자채널층과 연결되어 있는 전극(19)을 포함하여 이루어져 있다. 그리고, 상기 구조적 결함 및 암전류를 최소화시키기 위하여 형성된 InP완층층(11)과 InP/Al0.48In0.52As 초격자층(12) 및 게이트부(18)는 생략이 가능하다.An InP complete layer 11 and an InP / Al 0.48 In 0.52 As superlattice layer 12 formed on the semi-insulated InP substrate 10 to minimize structural defects and dark currents; An In 0.53 Ga 0.47 As conductive layer formed on the InP / Al 0.48 In 0.52 As superlattice layer; A two-dimensional electron channel layer 14 formed on the conductive layer; A potential barrier layer 15 formed to localize the free electrons present in the two-dimensional electron channel layer; An n-type doped Al 0.48 In 0.52 As electron donating layer 16 formed on the potential barrier layer; An InP window layer 17 formed on the Al 0.48 In 0.52 As electron donating layer; And a gate 18 formed on the window layer and an electrode 19 connected to the conductive layer and the electron channel layer. In addition, the InP complete layer 11, the InP / Al 0.48 In 0.52 As superlattice layer 12, and the gate 18 may be omitted to minimize the structural defects and the dark current.
그리고, 상기 In0.53Ga0.47As 전도층(13)과 n형으로 도핑된 Al0.48In0.52As 전자공여층(16) 사이의 전위장벽층(15)은 도핑하지 않은 Al0.48In0.52As 진성영역이다.The potential barrier layer 15 between the In 0.53 Ga 0.47 As conductive layer 13 and the n-type doped Al 0.48 In 0.52 As electron donating layer 16 is an undoped Al 0.48 In 0.52 As intrinsic region. .
또한 상기 게이트 및 전극의 패턴은 리프트 오프(Lift-off) 공정을 통해 형성된다.In addition, the pattern of the gate and the electrode is formed through a lift-off process.
상기와 같은 구조를 적용한 고전자 이동도 트랜지스터를 이용한 수광소자에추가적으로 사진공정 및 습식 식각공정을 이용하여 메사(mesa)패턴을 형성할 수 있는데, 이러한 메사 기술은 인접한 지역의 위에서 투사하여 원표면의 평면 부분만 남기는 선택적 식각으로 만든 소자 구조로서, MESA 기술은 전기적 활성 물질이 MESA 지역으로 확장되는 것을 막는데 쓰인다.In addition to the light-receiving device using a high electron mobility transistor having the above structure, a mesa pattern can be formed by using a photolithography process and a wet etching process. Such a mesa technique can be projected from an adjacent area to produce a mesa pattern. As a device structure made of selective etching leaving only a planar portion, MESA technology is used to prevent the electrically active material from expanding into the MESA region.
이러한 구조를 지닌 고전자 이동도 트랜지스터의 광전류 메커니즘은 도 6과 도 7의 구조도를 통하여 알 수 있다. 도 6은 본 발명에 의한 고전자 이동도 트랜지스터의 광전류 메커니즘을 나타낸 도식도이다. 입사 광자 혹은 전자기파가 In0.53Ga0.47As 흡수층에서 전자(8)와 정공(9)을 발생시키면서 흡수된다. 생성된 전자는 2차원 전자채널(21)이 존재하는 중성 Al0.48In0.52As/In0.53Ga0.47As 계면으로 이동하는 반면 생성된 정공은 기판방향인 In0.53Ga0.47As 층 중성영역(20)으로 이동하게 된다. 이것은 도 7의 에너지 밴드 구조로 쉽게 설명된다.The photocurrent mechanism of the high electron mobility transistor having such a structure can be seen through the structural diagrams of FIGS. 6 and 7. 6 is a schematic diagram showing a photocurrent mechanism of a high electron mobility transistor according to the present invention. Incident photons or electromagnetic waves are absorbed while generating electrons 8 and holes 9 in the In 0.53 Ga 0.47 As absorption layer. The generated electrons move to the neutral Al 0.48 In 0.52 As / In 0.53 Ga 0.47 As interface in which the two-dimensional electron channel 21 exists, while the generated holes move to the In 0.53 Ga 0.47 As layer neutral region 20 in the substrate direction. Will move. This is easily explained by the energy band structure of FIG.
도 7은 본 발명에 의한 고전자 이동도 트랜지스터의 광전류 메커니즘을 나타내는 에너지 밴드 구조도로서, 각 영역은 n형으로 도핑된 Al0.48In0.52As 전자공여층(22)과 중성 Al0.48In0.52As 전위장벽층(23) 및 2차원 전자채널을 포함하는 In0.53Ga0.47As층(24)이다. Al0.48In0.52As/In0.53Ga0.47As 계면에는 각각의 일함수 차이로부터 기인하는 내부전기장이 존재하는데 광자가 이러한 영역내에서 흡수되어 전자와 정공을 생성시키면 각각 2차원 전자채널(21), In0.53Ga0.47As 중성영역(20)으로 분리 이동하게 된다. 이 영역에서의 포텐셜차는 크기 때문에 일단 그들이 반대방향으로 분리되는 과정에서의 재결합은 무시할 수 있으며 2차원 전도채널로 이동한 전자(8)는 빠른 이동도를 가지고 외부 회로로 흐르는 반면 In0.53Ga0.47As 중성영역으로 이동한 정공(9)은 상대적으로 축적하게 된다. 이렇게 축적된 정공은 중성조건을 만족시키기 위해 외부회로로부터 더 많은 전자들을 유도시킴으로서 큰 광이득율(gain)을 일으키게 한다.7 is an energy band structure diagram showing a photocurrent mechanism of a high electron mobility transistor according to the present invention, in which each region is an n-type doped Al 0.48 In 0.52 As electron donating layer 22 and a neutral Al 0.48 In 0.52 As potential barrier. In 0.53 Ga 0.47 As layer 24 comprising layer 23 and two-dimensional electron channel. At the Al 0.48 In 0.52 As / In 0.53 Ga 0.47 As interface, there is an internal electric field resulting from each work function difference. When photons are absorbed in these regions to generate electrons and holes, the two-dimensional electron channel 21, In 0.53 Ga 0.47 As is moved to the neutral region 20 separately. Since the potential difference in this region is large, recombination once neglected in the process of their separation in the opposite direction is negligible, while electrons (8) traveling in the two-dimensional conduction channel flow to the external circuit with high mobility while In 0.53 Ga 0.47 As The holes 9 moved to the neutral region accumulate relatively. The accumulated holes induce more electrons from the external circuit to satisfy the neutral condition, causing a large gain.
도 8은 상기와 같은 구조 및 광전류 메커니즘을 가지는 고전자 이동도 트랜지스터 수광소자의 감도특성을 나타낸 것이다. 광량이 감소할수록 감도가 현저하게 향상되고, 나노와트 영역의 광량에서는 1000A/W까지 증가됨을 알 수 있다.8 shows the sensitivity characteristics of the high electron mobility transistor light receiving device having the structure and the photocurrent mechanism as described above. Sensitivity is remarkably improved as the amount of light decreases, and the amount of light in the nanowatt region is increased to 1000 A / W.
도 9는 본 발명에 의한 고전자 이동도 트랜지스터의 게이트 전압에 따른 감도를 나타낸 것으로서, 소스-드레인 전압 VDS이 0.5V일 때 게이트 전압 -1.5V±0.5V 범위에서 가장 감도가 우수하였다. 그러나, 본 발명에 따른 실험예인 도 9에 국한되지 아니하고 사용되는 소자의 재질이나 조건에 따라 감도가 변화하므로, 게이트 전압의 적절한 조절을 통해 고전자 이동도 트랜지스터의 감도가 최적화 될 수 있음을 알 수 있다.FIG. 9 illustrates the sensitivity according to the gate voltage of the high electron mobility transistor according to the present invention. When the source-drain voltage V DS is 0.5V, the sensitivity is the highest in the range of -1.5V ± 0.5V. However, the sensitivity of the high electron mobility transistor can be optimized by appropriately adjusting the gate voltage because the sensitivity varies depending on the material and the condition of the device used without being limited to FIG. 9, which is an experimental example according to the present invention. have.
따라서, 본 발명의 고전자 이동도 트랜지스터를 이용한 고감도 수광소자 및 이러한 소자의 게이트 전압의 조절을 통해 최적의 감도를 도출함으로써 기존의 PIN 포토다이오드에 비해 감도가 우수하고, 응답특성이 빠른 고속의 광 검출기를 제공할 수 있다.Therefore, the high sensitivity light-receiving device using the high electron mobility transistor of the present invention and the high-speed light having excellent sensitivity and fast response characteristics compared to the conventional PIN photodiode by deriving the optimum sensitivity by adjusting the gate voltage of the device. A detector can be provided.
Claims (8)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10116979A (en) * | 1996-10-14 | 1998-05-06 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor integrated device |
| JPH114014A (en) * | 1997-06-13 | 1999-01-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor photodetector |
| KR19990021365A (en) * | 1997-08-30 | 1999-03-25 | 김영환 | Manufacturing method of optoelectronic integrated circuit |
| JPH11145441A (en) * | 1997-11-12 | 1999-05-28 | Sumitomo Electric Ind Ltd | Waveguide type photoelectric converting device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10116979A (en) * | 1996-10-14 | 1998-05-06 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor integrated device |
| JPH114014A (en) * | 1997-06-13 | 1999-01-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor photodetector |
| KR19990021365A (en) * | 1997-08-30 | 1999-03-25 | 김영환 | Manufacturing method of optoelectronic integrated circuit |
| JPH11145441A (en) * | 1997-11-12 | 1999-05-28 | Sumitomo Electric Ind Ltd | Waveguide type photoelectric converting device |
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