JPH06101578B2 - Planar heterojunction avalanche photodiode - Google Patents
Planar heterojunction avalanche photodiodeInfo
- Publication number
- JPH06101578B2 JPH06101578B2 JP59054908A JP5490884A JPH06101578B2 JP H06101578 B2 JPH06101578 B2 JP H06101578B2 JP 59054908 A JP59054908 A JP 59054908A JP 5490884 A JP5490884 A JP 5490884A JP H06101578 B2 JPH06101578 B2 JP H06101578B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- junction
- conductivity type
- layer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 14
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 description 12
- 230000031700 light absorption Effects 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 125000005842 heteroatom Chemical group 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 241000981595 Zoysia japonica Species 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electromagnetism (AREA)
- Light Receiving Elements (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は逆バイアス電圧で使用する半導体受光素子に関
し、更に詳しくはいわゆるガードリング効果を有するブ
レーナ型ヘテロ接合半導体受光素子に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor photodetector used with a reverse bias voltage, and more particularly to a brener type heterojunction semiconductor photodetector having a so-called guard ring effect.
（従来技術とその問題点） 現在、光通信用波長域として光ファイバーの伝送損失の
低い１〜1.6μｍ波長域が主流であり、この波長域にお
いて高速かつ高感度特性を有する半導体受光素子として
フォトダイオード（PD）あるいはアバランシフォトダイ
オード（APD）の研究開発が進められている。上記波長
域に感度を有する材料としてGeおよびIn0.53 Ga0.47As
が現在最も研究されているが、Ge−APDは暗電流が多く
従って過剰雑音が大きいという欠点を有している。それ
に代ってIn0.53 Ga0.47AsはInPに格子整合したヘテロ接
合形成が可能であるため、In Ga As層で光吸収によって
発生した電子−正孔キャリアの一方のみをアバランシ層
であるInP層へ輸送してアバランシ増倍させるような構
造を採用することにより、過剰雑音が小さくでき従って
高受信感度の達成が可能である。その構造例は第１図の
如くであり、この構造については既に特願54−39169に
おいて提案されている。n+−InP基板１の上にｎ−InPバ
ッファ層２、n-−In0.53 Ga0.47As層３、ｎ−InP層４、
n-−InP層４′を形成した後、熱拡散あるいはイオン注
入によりｐ型導電領域５を設けてpn接合を形成してい
る。６は反射防止を兼ねた表面保護膜で、７、８は各々
ｐ側電極、ｎ側電極である。かかる構造においては、電
極７−８間に逆バイアス電圧を印加し、空之層をIn Ga
As層３まで伸ばす事によって禁制帯域の狭いIn Ga Asで
光を吸収させ、発生した正孔キャリアを禁制帯域の広い
InP層４内に設けたpn接合まで輸送してアバランシ増倍
を生じさせている。すなわち禁制帯幅の広いInpで電圧
降伏が生じるために、低暗電流受光素子が実現でき、従
って低雑音かつ高受信感度が期待できる。(Prior art and its problems) At present, the wavelength range for optical communication is mainly the wavelength range of 1 to 1.6 μm with low transmission loss of optical fiber, and a photodiode is used as a semiconductor light receiving element having high speed and high sensitivity characteristics in this wavelength range. Research and development of (PD) or avalanche photodiode (APD) is in progress. Ge and In 0.53 Ga 0.47 As are materials with sensitivity in the above wavelength range.
Is currently the most studied, but Ge-APD has the drawback of high dark current and therefore high excess noise. Instead, In 0.53 Ga 0.47 As can form a heterojunction that is lattice-matched to InP, so only one of the electron-hole carriers generated by light absorption in the In Ga As layer is transferred to the InP layer, which is the avalanche layer. By adopting a structure for transporting and performing avalanche multiplication, excess noise can be reduced and therefore high reception sensitivity can be achieved. An example of the structure is as shown in FIG. 1, and this structure has already been proposed in Japanese Patent Application No. 54-39169. On the n + -InP substrate 1, an n-InP buffer layer 2, an n --In 0.53 Ga 0.47 As layer 3, an n-InP layer 4,
After the n -- InP layer 4'is formed, a p-type conductive region 5 is provided by thermal diffusion or ion implantation to form a pn junction. Reference numeral 6 is a surface protective film which also serves as antireflection, and 7 and 8 are a p-side electrode and an n-side electrode, respectively. In such a structure, a reverse bias voltage is applied between the electrodes 7 and 8 and the sky layer is made of In Ga.
By extending to the As layer 3, light is absorbed by In Ga As with a narrow forbidden band, and the generated hole carriers have a wide forbidden band.
It is transported to the pn junction provided in the InP layer 4 to cause avalanche multiplication. That is, since a voltage breakdown occurs in Inp having a wide band gap, a low dark current light receiving element can be realized, and thus low noise and high reception sensitivity can be expected.
しかしながら、第１図に示す構造においては選択的に形
成したpn接合部の正の曲率を有する部分5aに高電界が集
中する為、平坦部5bよりも低い逆バイアス電圧において
電圧降伏が生じ、受光領域に対応する5bの部分で充分に
キャリア増倍が得られないという欠点を有している。そ
こで5a部が負の曲率（ｒＯ）を有し、かつ降伏電圧が
5b部よりも高くなる傾斜型接合を設けた、すなわち第２
図に示すような云わゆるガードリング５′を有する構造
がよく知られている。これはSi−APDあるいはGe−APDの
ように単一の材料から形成される受光素子においては非
常に有効である。しかし、第１図に示したヘテロ接合を
有するAPDに対しては有効ではない。この状況を更に詳
しく説明する。第２図に示すように、第１図の構造にガ
ードリング５′を適用した場合、ガードリング５′の接
合位置が受光領域５のそれよりもIn Ga As層３とInP層４とのヘテロ界面に近接するため、ヘテ
ロ界面に印加される電界強度はは、受光領域５よりもガ
ードリング５′の部分の方が高くなる。従って空之層が
In Ga As層３に達しているとき上述した第１図の場合と
同様、ガードリングの曲率部５′ａにおいてIn Ga As層
の電圧降伏が生じてしまい、受光領域に対応する5bの部
分でのキャリア増倍が充分に行われないという欠点を有
してしまう。すなわち、従来構造では、受光領域で充分
に増倍が得られないうちに電圧降伏が生じてしまうとい
う欠点を有していた。However, in the structure shown in FIG. 1, since the high electric field concentrates on the portion 5a having a positive curvature of the selectively formed pn junction, voltage breakdown occurs at a reverse bias voltage lower than that of the flat portion 5b, and It has a drawback that carrier multiplication cannot be sufficiently obtained in the portion 5b corresponding to the region. Therefore, the 5a part has a negative curvature (rO), and the breakdown voltage is
Providing a graded joint that is higher than part 5b, ie the second
A structure having what is called a guard ring 5'as shown in the figure is well known. This is very effective in a light receiving element formed of a single material such as Si-APD or Ge-APD. However, it is not effective for the APD having the heterojunction shown in FIG. This situation will be described in more detail. As shown in FIG. 2, when the guard ring 5 ′ is applied to the structure of FIG. 1, the junction position of the guard ring 5 ′ is higher than that of the light receiving region 5 in the In Ga As layer 3 and the InP layer 4. Since it is close to the interface, the electric field strength applied to the hetero interface is higher in the guard ring 5 ′ than in the light receiving region 5. Therefore, the sky layer
When reaching the In Ga As layer 3, as in the case of FIG. 1 described above, the voltage breakdown of the In Ga As layer occurs in the curvature portion 5′a of the guard ring, and at the portion 5b corresponding to the light receiving region. However, there is a drawback in that the carrier multiplication is not sufficiently performed. That is, the conventional structure has a drawback that voltage breakdown occurs before multiplication is sufficiently obtained in the light receiving region.
（発明の目的） 本発明はこのような従来の欠点を除去せしめ、ガードリ
ングにおいて電圧降伏が生じる以前に、受光領域で充分
なキャリア増倍による電圧降伏が生じるヘテロ接合を用
いた半導体受光素子を提供することにある。(Object of the Invention) The present invention eliminates such a conventional defect and provides a semiconductor light receiving element using a heterojunction in which a voltage breakdown due to sufficient carrier multiplication occurs in the light receiving region before the voltage breakdown occurs in the guard ring. To provide.
（発明の構成） 本発明のプレーナ型ヘテロ接合アバランシェフォトダイ
オードは少なくともEg1なる禁制帯幅を有する第１導電
型の光吸収のための半導体層、該光吸収層の上に積層さ
れたEg2（ただしEg2＞Eg1）なる禁制帯幅を有する第１
導電型アバランシェ増倍のための半導体層を有し、該ア
バランシェ増倍層中に急峻な階段型pn接合（第１のpn接
合とする）フロントを与える、不純物濃度の十分高い第
２導電型の第１領域、該第２導電型第１領域の外周縁に
おける第１導電型アバランシェ増倍層との境界を与える
曲率を有する部分を、リング状に囲んだ第２導電型の第
２の領域、該リング状第２導電型第２領域の外側周縁部
における第１導電型アバランシェ増倍層との境界を与え
る領域を更にリング状に囲んだ第２導電型の第３領域が
設けられて、第２導電型第２領域及び第２導電型第３領
域は第１導電型アバランシェ増倍層との境界において傾
斜型pn接合（それぞれ第２、第３のpn接合とする）を与
える事を特徴とし、更に、第２導電型第２領域のpn接合
フロントの表面からの深さは第２導電型第１領域及び第
２導電型第３領域の深さよりも深いことを特徴とする。(Structure of the Invention) The planar heterojunction avalanche photodiode of the present invention comprises a semiconductor layer for light absorption of the first conductivity type having a forbidden band width of at least Eg 1 , and Eg 2 laminated on the light absorption layer. The first with a forbidden band width (where Eg 2 > Eg 1 )
A second conductivity type having a sufficiently high impurity concentration, which has a semiconductor layer for conductivity type avalanche multiplication, and provides a steep step type pn junction (first pn junction) front in the avalanche multiplication layer. A second region of the second conductivity type in which a first region, a portion having a curvature that provides a boundary with the first conductivity type avalanche multiplication layer in the outer peripheral edge of the second region of the second conductivity type is surrounded by a ring. A third region of the second conductivity type is further provided, which further surrounds a region of the outer peripheral portion of the second region of the ring-shaped second conductivity type that provides a boundary with the avalanche multiplication layer of the first conductivity type in a ring shape. The second-conductivity-type second region and the second-conductivity-type third region are characterized by providing inclined pn junctions (second and third pn junctions, respectively) at the boundary with the first-conductivity-type avalanche multiplication layer. , Further, from the surface of the pn junction front of the second region of the second conductivity type The depth is deeper than the depth of the second conductivity type first region and the second conductivity type third region.
（発明の詳細な説明） 本発明は上述の構成により従来の欠点を解決した。すな
わち受光領域である第１のpn接合とがードリングである
第２のpn接合から構成される第２図の構造では、第２の
pn接合が第１のpn接合よりもヘテロ界面に近接するため
第２のpn接合の曲率部５′ａにおける電圧降伏が生じる
ために均一な高アバランシェ増倍層特性が得られなかっ
たが、第２のpn接合を囲むように第２のpn接合よりも浅
く位置する本発明の第３のpn接合を設けることにより、
第２のpn接合曲率部５′ａの曲率を負にすることができ
（ｒＯ）従って第２のpn接合と第３のpn接合の降伏電
圧を第１のpn接合部のそれよりも高く設定でき均一な高
アバランシェ増倍特性が得られる。(Detailed Description of the Invention) The present invention has solved the conventional drawbacks by the above-mentioned configuration. That is, in the structure of FIG. 2 in which the first pn junction which is the light receiving region and the second pn junction which is a drain,
Since the pn junction is closer to the hetero interface than the first pn junction, voltage breakdown occurs at the curved portion 5'a of the second pn junction, and uniform high avalanche multiplication layer characteristics cannot be obtained. By providing the third pn junction of the present invention which is located shallower than the second pn junction so as to surround the second pn junction,
The curvature of the second pn junction curvature portion 5'a can be made negative (rO). Therefore, the breakdown voltage of the second pn junction and the third pn junction is set higher than that of the first pn junction portion. As a result, uniform high avalanche multiplication characteristics can be obtained.
（実施例） 以下第１図、第２図と同様InP/In Ga Asヘテロ接合APD
について実施例を用いてより詳細に説明するが、他のヘ
テロ接合、例えばAl Ga As/Ga As、Al Ga Sb/Ga Sb等に
ついても全く同様であることは容易に理解される。(Examples) InP / In Ga As heterojunction APD similar to FIGS. 1 and 2 below
Examples will be described in more detail with reference to Examples, but it is easily understood that other heterojunctions such as Al Ga As / Ga As and Al Ga Sb / Ga Sb are exactly the same.
第３図は、本発明による受光素子の一実施例である。FIG. 3 shows an embodiment of the light receiving element according to the present invention.
n+−InP基板１上に、ｎ−InPバッファ層２を１μｍ厚
に、３〜５×1015cm-3キャリア濃度のｎ−In0.53 Ga
0.47As層３を3.5μｍ厚に、波長1.3μｍ相当のIn Ga As
P層３′を0.3μｍ厚に、１〜２×1016cm-3キャリア濃度
のｎ−InP層４を1.5μｍ厚に、１〜５×1015cm-3キャリ
ア濃度のn-−InP層４′を２μｍ厚に順次形成した後、C
dの熱拡散法により階段型の第１のpn接合５を、Beのイ
オン注入法により傾斜型の第２及び第３のpn接合５′、
５″を各々形成した。On the n + -InP substrate 1, an n-InP buffer layer 2 having a thickness of 1 μm and a carrier concentration of n-In 0.53 Ga of 3 to 5 × 10 15 cm −3 is formed.
0.47 As layer 3 with a thickness of 3.5 μm and In Ga As with a wavelength of 1.3 μm
The P layer 3 'to 0.3μm thick, the 1~2 × 10 16 cm -3 n- InP layer 4 of the carrier concentration in 1.5μm thickness, of 1~5 × 10 15 cm -3 carrier concentration n - -InP layer After sequentially forming 4'to a thickness of 2 μm, C
The step-type first pn junction 5 is formed by the thermal diffusion method of d, and the inclined second and third pn junctions 5 ′ are formed by the Be ion implantation method.
5 ″ each was formed.
第２と第３のpn接合５′、５″は各々、Beイオンの加速
エネルギーを変えることによって（第２は100KV、第３
は60KV加速）、その接合深さを調整した。The second and third pn junctions 5 ′ and 5 ″ are each formed by changing the acceleration energy of Be ions (the second is 100 KV, the third is
60KV acceleration), the junction depth was adjusted.
第３図に示す構造により、第２のpn接合曲率部５′ａの
曲率が第２図の場合と違って負になる（ｒＯ）ため、
第２のpn接合の降伏電圧が、従来の第２図の場合よりも
高くなる。更に第３のpn接合は、第２のpn接合よりもヘ
テロ界面から離れているため、第３のpn接合曲率部５″
ａにおける電圧降伏は、第２図における曲率部５′ａよ
りも高くかつ第１のpn接合の受光領域に対応する5b部よ
りも高くすることができる。従って受光領域に対応する
第１のpn接合部5bにおけるキャリア増倍を充分に行うこ
とができる。Because of the structure shown in FIG. 3, the curvature of the second pn junction curvature portion 5'a becomes negative (rO) unlike the case of FIG.
The breakdown voltage of the second pn junction becomes higher than that in the conventional case of FIG. Furthermore, since the third pn junction is farther from the hetero interface than the second pn junction, the third pn junction curved portion 5 ″ is formed.
The voltage breakdown at a can be higher than that of the curved portion 5'a in FIG. 2 and higher than that of the portion 5b corresponding to the light receiving region of the first pn junction. Therefore, carrier multiplication in the first pn junction 5b corresponding to the light receiving region can be sufficiently performed.
（発明の効果） 本発明による第３図の構造で作製したInP/In Ga Asヘテ
ロ接合APDの増倍特性は第４図に示す如くであり、第２
および第３のpn接合から成るガードリング部よりも第１
のpn接合から成る受光領域におけるキャリア増倍が大き
い状況が実現された。このときの最大増倍率は50倍程度
であり、従来の第２図の構造を用いた場合の10倍程度よ
りも良好な結果を得た。(Effect of the invention) The multiplication characteristics of the InP / In Ga As heterojunction APD manufactured by the structure of FIG. 3 according to the present invention are as shown in FIG.
And the guard ring portion formed of the third pn junction
The situation has been realized in which the carrier multiplication is large in the light-receiving region consisting of the pn junction. The maximum multiplication factor at this time is about 50 times, which is better than about 10 times when the conventional structure of FIG. 2 is used.
以上、本発明によれば、第１のpn接合フロント平坦部よ
りも高い降伏電圧のガードリングを形成でき、受光領域
における均一なアバランシェ高増倍特性が得られる利点
を有している。As described above, according to the present invention, it is possible to form a guard ring having a breakdown voltage higher than that of the first pn junction front flat portion, and to obtain uniform avalanche high multiplication characteristics in the light receiving region.
第１図、第２図は従来のヘテロ接合半導体受光素子の断
面図であり、第３図は本発明のヘテロ接合半導体受光素
子を示す図である。 第４図は本発明の効果の一例で、増倍特性を示してい
る。 図において、１は半導体基板、２は１と同種の半導体バ
ッファ層、３は禁制帯幅の小さい光吸収層、３′は３と
４との中間の禁制帯幅を有する半導体層４は禁制帯幅の
大きいアバランシ増倍層、４′は４と同種で４よりもキ
ャリア濃度の低い半導体層、５、５′、５″は各々第１
のpn接合、第２のpn接合、第３のpn接合、5a、５′ａ、
５″ａはその接合の曲率部、5bは接合の平坦部、６は表
面保護膜、７、８は各々pn側電極、ｎ側電極である。1 and 2 are cross-sectional views of a conventional heterojunction semiconductor photodetector, and FIG. 3 is a diagram showing a heterojunction semiconductor photodetector of the present invention. FIG. 4 shows an example of the effect of the present invention and shows the multiplication characteristic. In the figure, 1 is a semiconductor substrate, 2 is a semiconductor buffer layer of the same type as 1, 3 is a light absorption layer having a small forbidden band width, 3'is a semiconductor layer 4 having a forbidden band width between 3 and 4, and a forbidden band. The avalanche multiplication layer having a large width, 4'is a semiconductor layer of the same type as 4 and having a carrier concentration lower than 4, 5, 5 ', 5 "is the first
Pn junction, second pn junction, third pn junction, 5a, 5'a,
Reference numeral 5 "a is a curved portion of the junction, 5b is a flat portion of the junction, 6 is a surface protective film, 7 and 8 are pn side electrodes and n side electrodes, respectively.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 杉本 喜正 東京都港区芝５丁目33番１号 日本電気株 式会社内 (56)参考文献 特開 昭56−58286（ＪＰ，Ａ) 特開 昭58−30164（ＪＰ，Ａ) 特開 昭58−157177（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yoshimasa Sugimoto 5-33-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation (56) References JP-A-56-58286 (JP, A) JP-A-SHO 58-30164 (JP, A) JP-A-58-157177 (JP, A)
Claims (1)
導電型の光吸収のための半導体層、該光吸収層の上に積
層されたEg2（ただしEg2＞Eg1）なる禁制帯幅を有する
第１導電型のアバランシェ増倍のための半導体層を有
し、該アバランシェ増倍層中に急峻な階段型pn接合（第
１のpn接合とする）フロントを与える不純物濃度の十分
高い第２導電型の第１領域、該第２導電型第１領域の外
周縁における第１導電型アバランシェ増倍層との境界を
与える曲率を有する部分を、リング状に囲んだ第２導電
型の第２領域、該リング状第２導電型第２領域の外側周
縁部における第１導電型アバランシェ増倍層との境界を
与える領域を更にリング状に囲んだ第２導電型の第３領
域が設けられて、第２導電型第２領域及び第２導電型第
３領域は第１導電型アバランシェ増倍層との境界におい
て傾斜型pn接合（それぞれ第２、第３のpn接合とする）
を与えることを特徴とし、更に、第２導電型第２領域の
pn接合フロントの表面からの深さは第２導電型第１領域
及び第２導電型第３領域の深さよりも深いことを特徴と
するプレーナ型ヘテロ接合アバランシェフォトダイオー
ド。1. A first having a forbidden band width of at least Eg 1 .
A conductive type semiconductor layer for absorbing light, and a semiconductor layer for avalanche multiplication of the first conductive type having a forbidden band width of Eg 2 (where Eg 2 > Eg 1 ) laminated on the light absorbing layer. A first region of the second conductivity type having a sufficiently high impurity concentration for providing a steep step type pn junction (referred to as a first pn junction) front in the avalanche multiplication layer, and the second conductivity type first region. A second conductive type second region in which a portion having a curvature that gives a boundary with the first conductive type avalanche multiplication layer in the outer peripheral edge of the region is surrounded in a ring shape, and outside the ring-shaped second conductive type second region A third region of the second conductivity type is further provided, which surrounds a region that provides a boundary with the avalanche multiplication layer of the first conductivity type in the peripheral portion and further surrounds in a ring shape. The three regions have a graded pn junction at the boundary with the first conductivity type avalanche multiplication layer. It is the second, the third pn junction)
Of the second region of the second conductivity type.
A planar heterojunction avalanche photodiode characterized in that the depth from the surface of the pn junction front is deeper than the depths of the second conductivity type first region and the second conductivity type third region.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59054908A JPH06101578B2 (en) | 1984-03-22 | 1984-03-22 | Planar heterojunction avalanche photodiode |
| US06/713,669 US4651187A (en) | 1984-03-22 | 1985-03-19 | Avalanche photodiode |
| DE8585103299T DE3567128D1 (en) | 1984-03-22 | 1985-03-21 | Avalanche photodiode and its manufacturing method |
| CA000477076A CA1261450A (en) | 1984-03-22 | 1985-03-21 | Avalanche photodiode with double guard ring |
| EP85103299A EP0159544B1 (en) | 1984-03-22 | 1985-03-21 | Avalanche photodiode and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59054908A JPH06101578B2 (en) | 1984-03-22 | 1984-03-22 | Planar heterojunction avalanche photodiode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60198786A JPS60198786A (en) | 1985-10-08 |
| JPH06101578B2 true JPH06101578B2 (en) | 1994-12-12 |
Family
ID=12983695
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59054908A Expired - Lifetime JPH06101578B2 (en) | 1984-03-22 | 1984-03-22 | Planar heterojunction avalanche photodiode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06101578B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6390868A (en) * | 1986-10-03 | 1988-04-21 | Nec Corp | Manufacture of semiconductor photodetector |
| JP2573201B2 (en) * | 1987-02-26 | 1997-01-22 | 株式会社東芝 | Method for forming diffusion layer of semiconductor device |
| JPH02248081A (en) * | 1989-03-22 | 1990-10-03 | Toshiba Corp | Avalanche photodiode and manufacture thereof |
| CA2396325C (en) | 2001-09-06 | 2010-03-30 | Sumitomo Electric Industries, Ltd. | Zn1-xmgxsyse1-y pin photodiode and zn1-xmgxsyse1-y avalanche-photodiode |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54101278A (en) * | 1978-01-26 | 1979-08-09 | Nec Corp | Manufacture for semiconductor device |
| JPS54102876A (en) * | 1978-01-30 | 1979-08-13 | Mitsubishi Electric Corp | Manufacture for planer type semiconductor device |
| JPS5642385A (en) * | 1979-09-12 | 1981-04-20 | Nec Corp | Hetero-structure semiconductor device |
| JPS5658286A (en) * | 1979-10-18 | 1981-05-21 | Nippon Telegr & Teleph Corp <Ntt> | Forming method for guard ring of avalanche photodiode |
| JPS5830164A (en) * | 1981-08-17 | 1983-02-22 | Nippon Telegr & Teleph Corp <Ntt> | Avalanche photodiode and manufacture thereof |
| JPS58157177A (en) * | 1982-03-15 | 1983-09-19 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1984
- 1984-03-22 JP JP59054908A patent/JPH06101578B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60198786A (en) | 1985-10-08 |
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