KR20040034225A - Elastic buffer for keeping frame synchronization and method for detecting clock difference using algorithm of the same - Google Patents

Abstract

PURPOSE: An elastic buffer for maintaining frame synchronization and a method for detecting a clock difference between nodes using the same are provided to minimize the loss of data by maintaining a state of frame synchronization. CONSTITUTION: An elastic buffer for maintaining frame synchronization includes a FIFO memory(100), a write address increment part(300), and a read address increment part(200). The FIFO memory(100) inputs data to a write address according to a write signal, output read address data according to a read signal, and have the storage capacity corresponding to integer times of two super frames. The write address increment part(300) increases a write address as much as 1 according to the write signal. The read address increment part(200) increases a read address as much as 1 according to the read signal. One of the write address increment part(300) and the read address increment part(200) shifts the write addresses or the read addresses corresponding to a half of a memory size of the FIFO memory before the FIFO memory is in an empty state of data or a full state of data.

Description

Elastic buffer that maintains frame synchronization and detection method of clock deviation between nodes using same {ELASTIC BUFFER FOR KEEPING FRAME SYNCHRONIZATION AND METHOD FOR DETECTING CLOCK DIFFERENCE USING ALGORITHM OF THE SAME}

The present invention relates to an elastic buffer that maintains frame synchronization and a method of detecting a clock deviation between nodes using the same. Specifically, a frame synchronization that minimizes data loss by controlling an address before a buffer becomes empty or empty due to clock deviation is provided. An elastic buffer and a method for detecting a clock deviation between nodes using the same are provided.

In general, in order to transmit and receive accurate information between systems that process voice and data, synchronization between systems of a transmitter and a receiver must be performed.

Ideally, network synchronization means that all transmission and switching systems in a network are operated at the same clock, but there is a problem that it is very difficult to operate at the same clock in a network configuration. The reason is that even when the same frequency is used due to clock timing jitter, transmission delay, and the mechanical and ambient environment of the clock generator itself, frequency stability differences between clock sources of both systems are generated. At this time, there was a problem that the information that was transmitted could not be received correctly and the information was excessively lost.

Therefore, the present invention aims to minimize the occurrence of data errors by continuously maintaining the network synchronization state even though there are some clock deviations during system operation.

1 is a diagram showing the structure of a frame and a super frame.

2 is a block diagram showing a configuration of an elastic buffer according to an embodiment of the present invention.

3 is a view showing the operation of the elastic buffer according to an embodiment of the present invention.

Figure 4 is a view comparing the error interval according to the conventional method and the embodiment of the present invention.

5 is a graph comparing the BER performance according to the conventional method and the embodiment of the present invention.

6 is a block diagram showing a 15-bit missing, repetitive detection method according to an embodiment of the present invention.

*** Explanation of symbols for the main parts of the drawing ***

100: cover memory section 200: lead address increasing section

210: first latch 220: second latch

230: address comparator 240: next lead address operation circuit

250,330: Modulo 960 operation circuit 300: Light address increase unit

310: third latch 320: +1 operation circuit

500, 700: sequence generator circuit 510: register

600: memory 610: first memory part

620: second memory unit 630: third memory unit

In order to achieve the above object, an embodiment of the present invention inputs data to a write address according to application of a write signal, outputs data of the read address according to application of a read signal, and stores an integer multiple of two super frame sizes. An encapsulated memory unit; A write address increasing unit configured to increase the write address by one according to the application of the write signal; And a read address increasing unit configured to increase the read address by one according to the application of the read signal, wherein any one of the write address increasing unit and the read address increasing unit is the data immediately before the empty memory unit. An elastic buffer for maintaining frame synchronization is provided by moving a write address or a read address by a size corresponding to half of the size of the target memory unit.

The storage capacity of the covered memory section is an integer multiple of 960 bits.

The write address increasing unit and the read address increasing unit perform a modulo 960 operation or an integer multiple operation of the modulo 960 such that the write address and the read address always represent an address in the target memory unit.

The write address increasing unit includes a first latch for storing a write address until a write signal is applied, and the read address increasing unit includes a second latch for storing a read address until a read signal is applied.

The difference between the two addresses is calculated by comparing the read address with the write address. When the difference between the two addresses is in the range of -2 to 2, the write address or the read address is moved by the size corresponding to half of the size of the covered memory unit.

In addition, an embodiment of the present invention comprises the steps of transmitting the data known to the receiver at the transmitting end to the receiving end having the elastic buffer of claim 1 using a sequence generating circuit; Generating data from the receiving end to the sequence generating circuit by 15 bits faster than the data transmitted from the transmitting end; It provides a method for detecting a clock deviation between nodes comprising the step of comparing the received data and the generated data at the receiving end to detect the omission or repetition of the frame.

In addition, an embodiment of the present invention comprises the steps of repeatedly transmitting the 8-bit cyclic repetitive code to the receiving end having the elastic buffer of claim 1; And a clock deviation detection method between nodes, which detects a period of the cyclic repetition code at a receiving end and determines that a frame is missed or repetitive when temporarily irregular.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 shows a structure of a frame and a super frame.

The multiplexing trunk line connecting nodes is 1.024Mbps, 32 channel capacity, and uses the first bit of each frame as FSW (Frame Sync. Word) to check and maintain frame synchronization. Each frame consists of 32 bits and it takes 32ms to transmit one frame.

The FSW is repeated every 15 frames, and the FSW value of each frame is 0000111011 00101, respectively. The 15 frames in which the FSW repeats are collectively called a super frame.

Since the FSW is repeated in units of 15 frames, repeating or dropping frames in units of 15 frames is not a problem from the viewpoint of maintaining frame synchronization. The contents of the data may be somewhat altered as 15 frames are repeated or omitted, but it is inevitable due to the difference in clocks, and the bit error rate is deteriorated.

The existing elastic buffer has a first in first out (FIFO) structure, and when the elastic buffer is cleared to full or empty, the frame synchronization is reset. The process is necessary. This required an FSW scan of several hundred bits. During hundreds of frame times during which frame synchronization was reestablished, the frames were not matched, causing severe data errors. Therefore, when the frame synchronization is lost, a burst error occurs.

2 illustrates a block diagram of an elastic buffer according to an embodiment of the present invention.

The elastic buffer is installed at each node to receive data therethrough.

In an exemplary embodiment, the elastic buffer includes a first in first out (FIFO) memory unit 100, a read address increasing unit 200, and a write address increasing unit 300.

The read address increasing unit 200 includes a first latch 210, a second latch 220, an address comparator 230, a next read address calculation circuit 240, and a modulo 960 calculation circuit 250.

The write address increasing unit 300 also includes a third latch 310, a +1 operation circuit 320, and a modulo 960 operation circuit 330.

The read address increasing unit 200 and the write address increasing unit 300 increase the respective addresses according to the application of the read signal and the write signal.

The detailed functions of each component are as follows.

In the embodiment of the present invention, the PIpo memory unit 100 is composed of dual port random access memory (RAM) having different read and write paths. Data is input to the write address by the write signal, and data is output from the read address by the read signal.

The write signal Wr is a command signal for writing data to the RAM. It is also used to latch the next write address.

The read Rd signal is a command signal for reading data in the RAM. It is used to latch the next read address (Rd Address) and to latch the current write address.

The first latch 210 is a memory for latching, storing, and outputting a next read address. Assume that it has a value of 0 at reset.

The second latch 220 is a memory that latches a write address into a read signal to store and output the write address. Assume that it has a value of 3 at reset.

The third latch 310 is a memory for latching, storing, and outputting the next write address. It has a value of 3 at reset.

The +1 calculation circuit 320 is a calculation circuit for increasing the read address by one.

The address comparator 230 is an operation circuit that compares the read address with the write address stored in the second latch 220. The read address is compared with the write address, and a small value is subtracted from a large value to determine whether or not the difference is in the range of -2 to +2.

As a result of the comparison in the address comparator 230, if the next read address is -2 to +2, the next read address is calculated as 'the current read address +481', otherwise the value is read as the 'current read address +1'. Calculate The value of the next read address is stored and output in the first latch 210 by the next write signal.

The modulo 960 arithmetic circuits 250 and 330 are arithmetic circuits that convert a value greater than 960 (or a value less than 0) into a value between 0 and 959. Ultimately, the read address and write address values are suppressed to vary between 0 and 959.

The operation of the elastic buffer is as follows.

In FIG. 2, the first latch 210 initially stores '0' as the read address, the third latch 310 stores '3' as the write address, and the second latch 220 also has '3'. Is saving. Since the output of the first latch 210 and the output of the second latch 220 are initially set to '0' and '3', the address comparator outputs the determination result as 'other'. The next write address calculation circuit 240 calculates the next write address as 'write address + 1 (= 3 + 1 = 4)' by the output of 'other'.

Initially, only write signals come in to store more than a certain level of input data in RAM. Initially storing about 256 bits of input data, the write address is incrementally increased by every write signal from 4 to 258. After the 256-bit input time has elapsed, the read signal is input. In the meantime, since there was no read signal, the read address did not increase but remained at zero. After that, the read address gradually increased like the write address by the read signal. If the write signal is also regularly input to the read signal 1 once, the write address and the read address are maintained at a constant interval (about 256). At this time, the address comparator 230 outputs only 'other'.

However, when the periods of the read signal and the write signal are different from each other, there is a change in the interval between the write address and the read address, and the case of 'write address-read address = 0, +1, +2, -1, -2', etc. occurs. Done. In this case, the address is controlled to increase the next read address by +481 instead of +1. When the next read address jumps by +481 and increases, data of the read address skipped by one super frame is read, and data of exactly one super frame amount is repeatedly transmitted or lost. After that, the normal super frame is transmitted again. The jump point of the address need not be exactly the start or end point of the super frame. Even if you jump at any point in the middle of a super frame, you jump to the very point of the previous or subsequent super frame so that the two incomplete super frames merge to maintain a full 480-bit super frame. Not only considering 'write address-read address = +1 or -1', but also considering +2, -2, etc. is for safety design purposes. That is, this is to prepare for the case where two or three read signals are generated in one write signal cycle or vice versa due to jitter (clock shake). The range can be set to an appropriate range according to the operating environment of the elastic buffer.

FIG. 3 shows the operation when the elastic buffer according to the embodiment of the present invention is empty or full.

3A shows the case where the elastic buffer is empty.

The elastic buffer stores data of the first and second super frames.

The write address is located at the last address of the second super frame and is in a state where the data of the third super frame is to be overwritten at the position where the data of the first super frame is written. However, since the period of the read signal is earlier than the period of the write signal, the read address is slightly separated from the write address, so that the data of the second super frame is almost read. If the read address is not controlled, the read address will read the data of the first super frame ahead of the write address if time passes.

According to the exemplary embodiment of the present invention, the read address is moved by 480 bits, which is the size of the super frame, to read the data of the second super frame again. The data of the second super frame is repeatedly output but the frame synchronization is maintained.

3B shows a case where the elastic buffer is full.

The elastic buffer stores data of the first super frame and the part of the zero and second super frames.

The data of the second super frame is almost overwritten at the position where the data of the 0th super frame has been written, and the read address is located at the last address of the 0th super frame, and the data of the first super frame is about to be read. to be. If the read address is not controlled, the write signal period is faster than the read signal period, so that the write address is slightly separated from the read address, so that the write address may overtake the read address if time passes. Therefore, the data of the third super frame is overwritten on the first super frame, so that the third super frame is read instead of the first super frame.

According to the exemplary embodiment of the present invention, the read address is shifted by 480 bits, which is the size of the super frame, to skip the first super frame and read the data of the second super frame. The data of the first super frame is missing, but the data thereafter is normally kept in frame synchronization.

Although the elastic buffer of the above-described embodiment has proposed a method of moving the read address, the same result can be obtained by moving the write address. In this case, it will be understood by those skilled in the art that a block diagram corresponding to the "lead" and the "light" are interchanged in the block diagram of FIG. 2.

Figure 4 shows the repetition period of the error interval and error interval in the conventional method and the improved method according to the present invention.

4A shows an error section in the conventional method.

In the conventional method, assuming that the clock deviation between two nodes is constant at 10 ^-5 (10 Hz at 1 MHz), a clock difference occurs about 10 bits per second when data is transmitted and received between the two nodes, and the allowable capacity of the elastic buffer is increased. After the time of filling, the elastic buffer must be cleared, and then the inter-node link must detect the FSW again to align the time slot of the channel.

In order to know the time taken to synchronize the BSW (Bose-Chaudhuri-Hocquenghem) block of the FSW resynchronizer and the Common Chanel Signaling (CCS) channel, the clock skew between the two nodes is artificially applied and then the node uses the CCS channel. Measures the Bit Error Ratio (BER) performance. CCS is a common channel used for signaling (signal processing such as connecting or disconnecting calls) by using digitally multiplexed signals and assigning numbers and names to time slots. The BCH is a method of encoding, adding data to a message of an original size to distinguish whether an error has occurred on a transmission path, and partially recovering an error. BCH is divided into blocks, and it is BCH block synchronization that correctly recognizes the location.

When the elastic buffer is 512 bits, inferred from the BER measurement results, the time required for total resynchronization for FSW synchronization and BCH block synchronization is estimated to be about 20 ms. That is, about 20,000 bits (= 0.02 [sec] * 1,000,000 [bps]) of data are lost each time for resynchronization upon buffer clearing according to the clock deviation.

If the buffer capacity is 1000 bits, the buffer is cleared every 50 seconds when 500 bits, which is half of the buffer capacity, are filled, and 20,000 bits are filled with error data. Half of the error data may be accidental, so 10,000 bits are an error. Since 10,000 bits out of 50 Mbits of 50 seconds of transmission data are errors, the BER can be expected to be 2.0 * 10 ^-4 (10,000 / 50 * 10 ⁶ ).

Since the elastic buffer is about 512 bits, about half of the 1000 bits of the buffer currently assumed, the buffer clear period is about half and error occurs twice, resulting in a BER of about 4.0 * 10 ^-4 .

4B illustrates an error section according to an embodiment of the present invention.

If the clock difference between the two nodes is 10 ^-5 under the same conditions as before, the difference is accumulated by 10 bits per second, and every 48 seconds when 480 bits are accumulated, one super frame (15 frames = 480 bits) is acquired. Repeated transmission or missing. Since frame synchronization is maintained, only the BCH block synchronization of the CCS channel needs to be matched. If the time required for BCH synchronization is estimated to be 3 ms, 3000 bits (= 0.003 [sec] * 1,000,000 [bps]) of data will be lost. Half of that 1,500 bits of data is considered an error.

In the embodiment of the present invention, since 1,500 bits of the 48 Mbits of data transmitted for 48 seconds are an error, the BER becomes 3.1 * 10 ⁻⁵ , using a conventional 1000-bit elastic buffer having a similar buffer capacity. It can be seen that the BER performance is better than the BER 2.0 * 10 ⁻⁴ .

Looking at the performance improvement when using the elastic buffer according to an embodiment of the present invention by comparing the BER performance according to the embodiment of the present invention with the conventional BER performance as follows.

5 is a graph comparing the BER performance of the conventional method and the improved method according to an embodiment of the present invention.

The dotted line on the graph represents the BER according to the clock deviation in the conventional method, and the solid line represents the BER according to the clock deviation in the case of the improved method.

In the conventional method, the size of the elastic buffer is converted into 1000 bits to represent a BER when data is lost for 20 ms when the buffer is cleared, and the BER curve according to data loss of 3 ms when the buffer is cleared is shown for the improved method.

Point A represents BER = 2.0 * 10 ⁻⁴ and point B represents BER = 3.1 * 10 ⁻⁵ . Therefore, it can be seen that the improved method has about 1/7 fewer errors than the conventional method having similar buffer capacity, and thus has good BER performance.

By using this improved elastic buffer design technique and observing the reception form of data in the data channel within the frame, the clock deviation between both nodes can be measured.

Fig. 6 shows a structure of missing and repeated detection of frames for measuring clock deviation.

By establishing a communication channel between two nodes and transmitting a data pattern known to the receiver at the transmitter, it is possible to find a time when 15 bits of the pattern are repeatedly transmitted or missing. Since one user's call channel is 1 bit in one frame, if 15 frames constituting the super frame are missing or repeated, the call channel is repeated and missing 15 bits like FSW. By recording the period in which 15 bits are repeatedly transmitted or missing, the clock difference between the two nodes can be measured.

In the 15-bit missing and repetitive detection configuration diagram of FIG. 6, the receiving end is provided with a sequence generating circuit 500 for outputting data to the memory 600 having a 45-bit storage capacity.

The sequence generating circuit 500 preferably includes at least five registers 510 and generates a sequence by an XOR (exclusive OR) operation. The memory 600 includes a first memory unit 610, a second memory unit 620, and a third memory unit 630 each having a size of 15 bits. The data generated by the sequence generator 500 is stored while sequentially moving from the first memory unit 610 to the third memory unit 630.

The sequence generating circuit 500 of the receiving end compares the data received from the transmitting end with the data stored in the memory 600 of the receiving end, and adjusts the clock until the same pattern as 15 bits of the second memory unit 620 matches. The synchronization is performed 15 bits faster than the sequence generating circuit 700 of the transmitting end.

Therefore, when the same data as the data currently received in the second memory unit 620 is stored, the past data is stored in the third memory unit 630 and the future data is stored in the first memory unit 610. When the comparison result is accumulated every 15 bits, if it is normal, the 15 bits of the second memory unit 620 and the receiving 15 bits are consistently matched with each other, and if the 15 bits are suddenly missing, the 15 of the first memory unit 610 If the bit is matched with the previous 15 bits, the bit is matched with the 15 bits of the third memory unit 630.

Once repetition or omission of 15 bits is detected, the detected time is recorded, and the clock of the sequence generation circuit 500 is adjusted to adjust the received data and the 15 bits of the second memory unit 620 again. That is, in the previous example, if 15 bits are repeated and missing every 48 seconds, the clock deviation is 10 ^-5 , and if 15 bits are repeated and missing every 24 seconds, the clock deviation is 2 * 10. ^-5 . That is, the detection period and the clock deviation are inversely related.

15-bit missing / repeated detection using Cyclic Permutable Codeword (CPC) detection is also possible. The CPC transmits 8 bits repeatedly. The sender limits the CPC to the minimum number of repetitions that can be detected by the receiver, and repeatedly transmits regular CPCs such as '0', '1' ... '9'. If it is recognized or the CPC detection period is temporarily irregular, for example, 0.48 ms delay, it can be determined that the 15-bit repetition, omission.

Measuring the relative stability of the clock remotely is important for network synchronization management in addition to the convenience of the measurement.

Many details are set forth in the foregoing description, but they should be construed as preferred embodiments rather than limiting the scope of the invention. Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the claims and the equivalents of the claims.

According to the embodiment of the present invention, the following effects can be obtained.

First, frame synchronization is maintained even under poor clock quality to minimize data loss.

Second, the read and write address control algorithm is relatively simple, so the burden of circuit design is small.

Third, it is possible to remotely measure the clock difference between the transmitting and receiving nodes with a sequence generating circuit that detects a 15-bit missing or repetition.

Claims (8)

A PPI memory unit for inputting data to a write address according to the application of the write signal and outputting data of the read address according to the application of the read signal and having an integer multiple of two super frame sizes; A write address increasing unit configured to increase the write address by one according to the application of the write signal; And A read address increasing unit configured to increase the read address by one according to the application of the read signal, Any one of the write address increasing unit and the read address increasing unit moves the write address or the read address by a size corresponding to half of the size of the covered memory unit when the data of the covered memory unit is immediately before empty or full. Elastic buffer to keep the frame synchronized. The elastic buffer of claim 1, wherein the storage capacity of the encapsulated memory unit is an integer multiple of 960 bits. 2. The frame synchronization according to claim 1, wherein the write address increasing unit and the read address increasing unit perform modulo 960 operations such that the write address and the read address always represent an address in the covered memory unit. Elastic buffer. 2. The second latch of claim 1, wherein the write address increasing unit includes a first latch for storing a write address until a write signal is applied, and the read address increasing unit stores a read address until a read signal is applied. Elastic buffer for maintaining frame synchronization, characterized in that it comprises a. The read address of claim 1, wherein the difference between the two addresses is calculated by comparing the read address with the write address. An elastic buffer for maintaining frame synchronization, characterized by moving a read address. Transmitting data known to the receiver by the transmitting end to the receiving end having the elastic buffer of claim 1 using a sequence generating circuit; Generating data from the receiving end to the sequence generating circuit by 15 bits faster than the data transmitted from the transmitting end; A method for detecting a clock deviation between nodes including comparing received data and generated data at a receiving end to detect a missing or repeated frame. Repeatedly transmitting an 8-bit cyclic repetition code to a receiving end having the elastic buffer of claim 1; And And detecting a period of the cyclic repetition code at a receiving end and determining that a frame is missed or repetitive when temporarily irregular. 8. The method of claim 7, wherein when the cycle of the cyclic repetition code is delayed by 0.48 ms, it is determined that 15 bits are missing or repeated.