KR20040022605A - Method of manufacturing a transistor in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a transistor of a semiconductor device is provided to easily generate tunneling current caused by hot electrons and improve an operation speed and an electrical characteristic by minimizing a gap between a gate electrode and a silicide layer. CONSTITUTION: A silicon-on-insulator(SOI) substrate(110) is prepared in which a stack structure composed of a gate oxide layer and a gate electrode is formed as a predetermined pattern. An insulation layer spacer(140) is formed on the sidewall of the gate electrode. The SOI substrate under the insulation layer spacer is exposed. A metal layer is formed in a source/drain region including the lower portion of the insulation layer spacer. The silicon component of the source/drain region is reacted with the metal component of the metal layer to form a silicide layer of a Schottky junction structure so that a source/drain(150) is formed.

Description

Method of manufacturing a transistor in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor of a semiconductor device, and more particularly, to a method of manufacturing a transistor of a semiconductor device having a Schottky Barrier-MOSFET structure using a silicide bonded to a semiconductor substrate and a Schottky junction as a source and a drain. .

Generally, a transistor of a semiconductor device is manufactured by forming a gate electrode on a semiconductor substrate and then performing an ion implantation process to form a source / drain on the semiconductor substrate at both edges of the gate electrode.

The transistor manufacturing method is also applied to the manufacturing process of ultrafine semiconductor devices having a design rule of 0.1 um. However, when the transistor is manufactured by the above method in an ultrafine process having a design rule of 0.1 μm, the following problems may occur.

The first problem is that it is difficult to control the junction depth of the source / drain. In the process of injecting an impurity to form a source / drain on the semiconductor substrate at the gate electrode edge and then performing heat treatment for activation, the short channel effect (SCE) is diffused simultaneously in the depth direction and the channel direction. ) Is difficult to suppress. To control this, impurities are diffused using Rapid Thermal Processing (RTP), Laser Annealing, and Solid Phase Diffusion (SPD), but the source / It is difficult to reduce the depth of the drain junction below 10 nm.

Second, there is a problem that the saturation current decreases because the depth of the junction becomes shallower and the area decreases when the degree of integration of the device increases.

Third, in order to activate the impurity implanted to form the source and drain, a heat treatment process should be performed at a high temperature of 800 ° C. or higher, in which case there is a difficulty in applying a metal gate.

The last problem is the possibility of soft error at the bonding interface and the presence of floating body effects.

In order to solve this problem, a transistor may be formed by a Schottky Barrier (SB) -MOSFET device manufacturing method in which a metal silicide layer is formed on a source / drain region to form a source / drain. This method may reduce the source / drain resistance while essentially eliminating the source / drain doping problem, and may omit the high temperature heat treatment process necessarily performed when the source / drain is formed by the ion implantation process. On the other hand, in the future, the metal gate application to meet the low power / high speed of the device will be able to demonstrate the flexibility of the mutual technology. However, the structure and process optimization have not yet been established for the manufacturing process of the semiconductor device using this method, and thus the ultra-low efficiency of the Schottky Barrier Height, which has a great influence on the device characteristics, has been achieved. There is a need to optimize the microdevice manufacturing process.

When the source / drain is formed by using the Schottky barrier, it has advantages such as being compatible in the process of applying the metal gate while suppressing the short channel effect and lowering the junction resistance.

The conventional method of manufacturing a Schottky barrier-MOSFET is to form a metal layer on the entire upper portion of the semiconductor substrate on which the gate electrode and the source / drain are formed, react the silicon component with the metal component by a heat treatment process, and then react with the metal component by a selective wet etching process. Is formed to form a source / drain while forming a silicide layer having a Schottky junction structure in the source / drain region. In this case, the silicide is performed because the process is performed while the insulating layer spacer is formed on the sidewall of the gate electrode for electrical insulation. A gap is generated between the layer as well as the source / drain and the gate electrode.

The gap between the silicide layer and the gate electrode prevents the generation of the through current caused by the hot electrons, thereby reducing the driving current as a whole, thereby lowering the operating speed of the device. Problems arise.

On the other hand, even after starting from the over-etched structure after forming the insulating film spacer, a gap is likely to occur between the bottom of the gate electrode and the interface between the silicide and silicon after forming the silicide. In order to minimize the gap, depositing a large amount of metal and increasing the heat treatment time for the silicide reaction may move the interface of the silicide layer to the lower side of the gate electrode to reduce the gap, but it may cause excessive burden and contamination problems during selective wet etching. Most likely.

Accordingly, in order to solve the above problem, the present invention forms an insulating film spacer on the sidewall of the gate electrode, exposes the semiconductor substrate under the insulating film spacer, forms a metal layer, and reacts the silicon component of the source / drain region with the metal component of the metal layer. By forming the silicide layer and the source / drain of the Schottky junction structure up to the lower edge of the gate electrode, the gap between the gate electrode and the silicide layer is minimized to easily generate a tunneling current by the hot electron and thereby the device It is an object of the present invention to provide a method for manufacturing a transistor of a semiconductor device that can improve the operation speed and electrical characteristics of the.

1A to 1E are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.

2A through 2E are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device in accordance with another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110, 210: SOI substrate 111, 211: insulating layer

112, 212: single crystal silicon layer 113: etching surface

120, 220: tunnel oxide film 130, 230: conductive layer, gate

140, 240: insulating film spacer

150, 250: silicide layer, source / drain

According to an aspect of the present invention, there is provided a method of fabricating a transistor of a semiconductor device, the method including: providing an SOI substrate having a gate oxide film and a gate electrode stacked in a predetermined pattern; forming an insulating film spacer on sidewalls of the gate electrode; Exposing the SOI substrate, forming a metal layer in a source / drain region including a lower portion of the insulating film spacer, and reacting a silicon component of the source / drain region with a metal component of the metal layer to form a silicide layer having a Schottky junction structure. Forming a source and a drain.

In the above description, the insulating film spacer may be formed by any one of a first process of forming an insulating film on the entire upper part and performing a dry etching process and a second process of oxidizing the surface of the gate electrode and then performing a dry etching process. It features.

The SOI substrate under the insulating film spacer is exposed by a selective silicon etching process to etch the SOI substrate by a predetermined thickness, and the selective silicon etching process etches the SOI substrate by a thickness corresponding to 20 to 50% of the thickness of the insulating film spacer. It is characterized in that the implementation. In addition, the selective silicon etching process is carried out while supplying HCl and H ₂ at a pressure of 10 to 500 Torr and a temperature of 750 to 950 ℃, wherein the supply flow rate of HCl is 0.1 to 1 slm, the supply flow rate of H ₂ Is 1 to 10 slm.

Meanwhile, the SOI substrate under the insulating film spacer is exposed by a cleaning process for etching the lower portion of the insulating film spacer. At this time, the cleaning process is characterized in that for 60 to 300 seconds while supplying the H ₂ gas at a pressure of 0.1 to 10 Torr and the temperature of 700 to 900 ℃, characterized in that the supply flow rate of H ₂ gas is 0.5 to 50 slm do.

The method may further include performing an ex-situ and an in-situ cleaning process after exposing the SOI substrate under the insulating layer spacer and before forming the metal layer.

Ex-situ cleaning process is characterized in that the wet bath using a HF solution, the HF solution is characterized in that the deionized water: HF is a mixture of 50: 1 to 500: 1 ratio. Meanwhile, before performing the cleaning process using the HF solution, the organic material on the surface of the SOI substrate is removed for 60 to 600 seconds using a solution in which deionized water and sulfuric acid are mixed 1: 1.

The in-situ cleaning process is carried out in the equipment in which the metal layer is to be formed, characterized in that the vacuum cleaning for 60 to 300 seconds at a temperature of 650 to 750 ℃ and ultra-high vacuum of 10 ^-8 Torr or less. In addition, the in-situ cleaning process is performed in the equipment on which the metal layer is to be formed, and proceeds with a hydrogen baking process for 60 to 300 seconds while supplying 0.5 to 50 slm of H ₂ at a pressure of 0.1 to 10 Torr and a temperature of 700 to 900 ° C. It is characterized by.

The silicide layer is characterized in that the metal layer is formed on the entire upper portion of the insulating layer so that only the source / drain region is exposed, and then the silicon component reacts with the metal component so as to be in the source / drain region only. The silicide layer is also formed on the gate electrode.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, like reference numerals refer to like elements.

1A to 1E are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, a gate oxide layer 120 and a conductive layer 130 are sequentially formed on a silicon on insulator (SOI) substrate 110 having an insulating layer 111 at a predetermined depth.

At this time, in order to optimize the manufacturing process of the ultra-small Schottky barrier-MOSFET, it is essential to use an SOI substrate because leakage current should be prevented as much as possible. The SOI substrate 110 is generally formed by forming a buried oxide (BOX) with an insulating layer 111 on the underlying silicon and then bonding the single crystal silicon 112 to each other. The conductive layer 130 may be formed of polycrystalline silicon.

Referring to FIG. 1B, the conductive layer 130 and the gate oxide layer 120 are patterned by an etching process using a gate mask. As a result, a gate including the patterned conductive layer 130 is formed. In this case, the patterning process is performed by applying a reactive ion etching (RIE) method.

Referring to FIG. 1C, an insulating film spacer 140 is formed on sidewalls of the gate 130. The insulating layer spacer 140 is formed by forming an insulating layer (not shown) on the entire upper part and then leaving the insulating layer only on the sidewall of the gate 130 by the RIE process.

As another method of forming the insulating film spacer 140, the surface of the gate 130 is oxidized by a thermal oxidation process, and then the gate layer 130 is removed while the oxide layer on the gate 130 is removed by the RIE process. The insulating film spacer 140 is formed in such a manner that the oxide layer remains only on the side surface of the insulating film. In this case, in order to form the insulating film spacer 140 by the oxidation process, the surface of the gate 130 needs to be oxidized. Therefore, in the patterning process of FIG. 1B, the patterning process is performed such that the gate 130 is patterned to a wider width than the target width. Is carried out. Although the thermal oxidation process is a high temperature process, there is an advantage that the gate 130 can be formed in a narrower width than the limit allowed by the exposure equipment.

Referring to FIG. 1D, a surface of the SOI substrate 110 is etched by a predetermined thickness by performing a selective silicon etching process. On the other hand, the selective silicon etching process is performed so that the SOI substrate 110 is etched by a thickness corresponding to 20 to 50% of the thickness of the insulating film spacer 140. By the selective silicon etching process, the surface of the SOI substrate 110 is etched to the surface of the SOI substrate 110 under the insulating film spacer 140, thereby exposing the surface of the SOI substrate 110 under the insulating film spacer 140. In this case, it can be seen that the etching surface of the lower portion of the insulating film spacer 140 is in the (111) direction.

The selective silicon etching process is carried out while supplying HCl and H ₂ at a pressure of 10 to 500 Torr and a temperature of 750 to 950 ° C., the supply flow rate of HCl is set to 0.1 to 1 slm, and the supply flow rate of H ₂ is 1 to 1. Set it to 10slm. Meanwhile, when the selective silicon etching process is performed under the above conditions, the surface of the SOI substrate 110 may be etched to obtain the effect of in-situ cleaning.

Referring to FIG. 1E, after forming a metal layer (not shown) on the source / drain region including the insulating layer spacer 140, a Schottky junction structure is formed by reacting a silicon component of the source / drain region with a metal component of the metal layer. The silicide layer is formed to form the source and drain 150. Then, the metal layer remaining without reacting with the silicon component is removed by a wet etching process.

In this case, since the metal layer is formed under the insulating layer spacer 140, the source / drain 150 is formed under the insulating layer spacer 140 to minimize the gap between the gate 130 and the source / drain 150. As a result, the tunneling current generated by the hot electron is easily generated, thereby improving the operation speed and the electrical characteristics of the transistor.

In the above, the metal layer may be formed on the entire upper portion of the insulating layer (not shown) to expose only the source / drain regions before the metal layer is formed, and the silicon and metal components may react with each other to form only the source / drain regions. have. In addition, the metal layer is formed on the gate 130, so that the silicide layer 160 is also formed on the gate electrode 130, thereby improving electrical characteristics.

Meanwhile, after etching the surface of the SOI substrate 110 by the selective silicon etching process in FIG. 1D, an ex-situ cleaning process is performed before the conductive layer is formed to remove the natural oxide layer and form a metal layer. In-situ cleaning process may be performed in the equipment for improving the deposition characteristics of the metal layer.

In the above, the ex-situ cleaning process is performed using a HF solution in a wet bath, the HF solution is a deionized water (HF) solution in which the ratio of deionized water: HF is 50: 1 to 500: 1 It is preferable to use as. At this time, before the cleaning process using the HF solution, the sulfuric acid is removed from the SOI substrate surface for 60 to 600 seconds using a sulfuric acid solution diluted 1: 1 in deionized water, the surface of the SOI substrate 110 A hydrogen passivation layer (not shown) may be formed in 90% or more.

On the other hand, the in-situ cleaning process is carried out in the equipment to form a metal layer, the vacuum cleaning for 60 to 300 seconds at a temperature of 650 to 750 ℃ and ultra-high vacuum of 10 ^-8 Torr or less, or a pressure of 0.1 to 10 Torr And hydrogen bake for 60 to 300 seconds while supplying 0.5 to 50 slm of H ₂ at a temperature of 700 to 900 ° C.

Through the above-described process, a transistor having a Schottky barrier-MOSFET structure is manufactured.

Hereinafter, as another method of minimizing the gap between the gate and the source / drain, the bottom of the insulating film spacer is etched to expose the SOI substrate under the insulating film spacer, and then a silicide layer is formed to form a source / drain. Let's explain.

2A through 2E are cross-sectional views illustrating a method of fabricating a transistor in a semiconductor device according to another embodiment of the present invention.

Since the process illustrated in FIGS. 2A to 2C proceeds in the same manner as the method described with reference to FIGS. 1A to 1C, a description thereof will be omitted.

Referring to FIG. 2D, the lower surface of the insulating film spacer 240 is etched by a cleaning process to expose the surface of the SOI substrate 210 under the insulating film spacer 240.

The cleaning process is performed for 60 to 300 seconds while supplying H ₂ gas at a pressure of 0.1 to 10 Torr and a temperature of 700 to 900 ° C., and the supply flow rate of H ₂ gas is set to 0.5 to 50 slm.

When the cleaning process is performed under the above conditions, etching is performed on the entire surface of the insulating film spacer 240, but due to defects and bonding surfaces present at the interface between the insulating film spacer 240 and the SOI substrate 210. Etching is actively performed under the insulating film spacer 240 in contact with the SOI substrate 210. As a result, an under cut phenomenon of the insulating film spacer 240 occurs, and a lower portion of the insulating film spacer 240 is etched to expose the surface of the SOI substrate 210 under the insulating film spacer 240. In addition, when the cleaning process is performed under the above conditions, the lower portion of the insulating film spacer 240 may be etched to obtain the effect of in-situ cleaning.

Referring to FIG. 2E, a silicide layer is formed in the same manner as described in FIG. 1E to form a source / drain. Similarly, since the silicide layer 250 is formed while the lower portion of the insulating layer spacer 240 is etched to expose the surface of the SOI substrate 210 under the insulating layer spacer 240, the source / drain 250 and the gate 230 are formed. The gap between them can be minimized.

In addition, before forming the silicide layer, an ex-situ cleaning process and an in-situ cleaning process may be performed by the same method as described with reference to FIG. 1E to improve process reliability and device electrical characteristics.

When the transistor of the semiconductor device is manufactured by the above-described method, the following effects can be obtained.

Firstly, the gap between gate and source / drain can be minimized to easily generate through current caused by hot electrons, thereby preventing the driving current from decreasing, thereby improving the operation speed of the device and reducing power consumption. have.

Second, the in-situ cleaning effect can be simultaneously obtained through a selective silicon etching process or a cleaning process exposing the SOI substrate under the insulating film spacer, and the damage can be minimized, thereby improving process reliability.

Third, when the above process is applied, a Schottky barrier-MOSFET can be manufactured by thinly depositing a metal layer, thereby reducing the burden on the wet etching process of removing the remaining metal layer without reacting and minimizing the metal contamination problem. can do.

Claims (17)

Providing an SOI substrate in which a stacked structure of a gate oxide film and a gate electrode is formed in a predetermined pattern; Forming an insulating film spacer on sidewalls of the gate electrode; Exposing the SOI substrate under the insulating film spacer; Forming a metal layer on a source / drain region including a lower portion of the insulating film spacer; And forming a silicide layer having a Schottky junction structure by reacting the silicon component of the source / drain region with the metal component of the metal layer to form a source and a drain. The method of claim 1, wherein the insulating film spacer comprises at least one of a first step of performing a dry etching process after forming an insulating film over the entire surface, and a second process of performing a dry etching process after oxidizing the surface of the gate electrode. A transistor manufacturing method of a semiconductor device, characterized in that formed in the step. The method of claim 1, wherein the SOI substrate under the insulation spacer is exposed by a selective silicon etching process of etching the SOI substrate by a predetermined thickness. The method of claim 3, wherein the selective silicon etching process is performed so that the SOI substrate is etched by a thickness corresponding to 20 to 50% of the thickness of the insulating film spacer. The method of claim 3, wherein the selective silicon etching process is performed while supplying HCl and H ₂ at a pressure of 10 to 500 Torr and a temperature of 750 to 950 ° C. 6. The method of claim 5, wherein the supply flow rate of HCl is 0.1 to 1 slm, and the supply flow rate of H ₂ is 1 to 10 slm. The method of claim 1, wherein the SOI substrate under the insulating layer spacer is exposed by a cleaning process of etching the lower portion of the insulating layer spacer. The method of claim 7, wherein the cleaning process is performed for 60 to 300 seconds while supplying H ₂ gas at a pressure of 0.1 to 10 Torr and a temperature of 700 to 900 ° C. 9. The method of claim 8, wherein the supply flow rate of the H ₂ gas is 0.5 to 50 slm. The semiconductor device transistor of claim 1, further comprising performing an ex-situ and an in-situ cleaning process after exposing the SOI substrate under the insulating film spacer and before forming the metal layer. Manufacturing method. The method of claim 10, wherein the ex-situ cleaning process is performed using a HF solution in a wet bath. The method of claim 11, wherein the HF solution is a solution in which deionized water: HF is mixed at a ratio of 50: 1 to 500: 1. The method of claim 11, wherein before the cleaning process using the HF solution, the organic material on the surface of the SOI substrate is removed for 60 to 600 seconds using a 1: 1 mixed solution of deionized water and sulfuric acid. Method for manufacturing a transistor of a semiconductor device. The method of claim 10, wherein the in-situ cleaning process is performed in the equipment on which the metal layer is to be formed, and vacuum cleaning for 60 to 300 seconds at a temperature of 650 to 750 ℃ and ultra-high vacuum of 10 ^-8 Torr or less A transistor manufacturing method of a semiconductor device, characterized in that. The method of claim 10, wherein the in-situ cleaning process is performed in the equipment on which the metal layer is to be formed, for 60 to 300 seconds while supplying 0.5 to 50 slm of H ₂ at a pressure of 0.1 to 10 Torr and a temperature of 700 to 900 ° C. A method of manufacturing a transistor of a semiconductor device, characterized in that it is carried out by a hydrogen baking process. The method of claim 1, wherein the silicide layer forms the metal layer over the entire surface of the silicide layer so that only the source / drain regions are exposed, and then reacts the silicon component with the metal component to form only the source / drain regions. A transistor manufacturing method of a semiconductor device, characterized in that. The method of claim 1 or 16, wherein the metal layer is formed on the gate electrode, and the silicide layer is formed on the gate electrode.