TWI642116B - A method of manufacturing a semiconductor device - Google Patents

Abstract

The method of fabricating a semiconductor device includes the steps of: providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer having a first opening, the first opening exposing a portion of the substrate; removing the exposed substrate a portion for forming a recess in the substrate, the recess having a bottom and a sidewall; wherein the first n-type dopant is doped at the bottom and sidewall of the recess via the first opening to form a hole barrier surrounding the recess a bottom and a sidewall; and forming a p-type epitaxial layer in the recess.

Description

Method of fabricating a semiconductor component

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a power semiconductor device.

Insulated gate bipolar transistors (IGBTs) are widely used in transportation, home appliances, power engineering, aviation, military, etc. because of their high frequency and high current. In recent years, various new processes and new technologies for insulated gate bipolar transistors have emerged, making the performance of insulated gate bipolar transistors more perfect and excellent.

However, since the current process methods use a doping process, it is necessary to calculate the diffusion rate of the n-type dopant and the p-type dopant under different temperature environments to produce the desired n-type doping thickness and p-type doping. Mixed thickness. Because of the need to precisely control the diffusion thickness of the n-type dopant and the p-type dopant, the difficulty of the process is improved. Therefore, there is an urgent need to improve and simplify the process to increase production efficiency and yield.

In one aspect of the disclosure, a method of fabricating a semiconductor device includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer having a first opening, the first opening exposing a substrate a portion of the material; removing the exposed portion of the substrate to form a recess in the substrate, the recess having a bottom and a sidewall; and doping the first n-type dopant at the bottom and sidewall of the recess via the first opening, To form a hole barrier layer, the hole barrier layer surrounds the bottom and sidewalls of the groove; and a p-type epitaxial layer is formed in the groove.

According to one or more embodiments of the present disclosure, the substrate includes a p-type doped layer, an n-type buffer layer, and an n-type drift layer, wherein the n-type buffer layer is between the p-type doped layer and the n-type drift layer.

According to one or more embodiments of the present disclosure, the doping concentration of the hole barrier layer is from about 1×10 ¹⁵ to about 5×10 ¹⁹ cm ⁻³ .

In accordance with one or more embodiments of the present disclosure, doping the first n-type dopant at the bottom and sidewalls of the trench via the first opening comprises using ion implantation or plasma ion infiltration.

According to one or more embodiments of the present disclosure, after forming the p-type epitaxial layer in the recess, the thickness of the hole barrier layer is less than or equal to 3 μm.

In accordance with one or more embodiments of the present disclosure, the grooves have a depth of from about 1 [mu]m to about 10 [mu]m.

According to one or more embodiments of the present disclosure, after the p-type epitaxial layer is formed in the recess, the planarization of the p-type epitaxial layer is further included, wherein the planarizing the p-type epitaxial layer comprises removing the p-type epitaxial layer. Part and patterning the mask layer to expose the surface of the substrate, the surface of the hole barrier layer, and the surface of the p-type epitaxial layer; forming a gate oxide layer covering the surface of the substrate and being electrically a surface of the hole barrier layer and a surface of the p-type epitaxial layer; forming a patterned gate layer on the gate oxide layer, wherein the patterned gate layer has a second opening, the second opening is located on the p-type epitaxial layer; Doping a second n-type dopant in the p-type epitaxial layer via the second opening to form a plurality of n-type source regions; forming an interlayer dielectric layer covering the patterned gate layer; after forming the interlayer dielectric layer Forming a p-type doped region in the p-type epitaxial layer, and the p-type doped region is located between the n-type source regions; and forming an electrode layer on the p-type doped region and the interlayer dielectric layer, and Type doped regions are in contact.

According to one or more embodiments of the present disclosure, planarizing the p-type epitaxial layer includes removing a portion of the p-type epitaxial layer using a chemical mechanical polishing process; removing the patterned mask layer to expose the substrate; forming sacrificial oxide The layer covers the p-type epitaxial layer and the substrate; and the sacrificial oxide layer is removed.

According to one or more embodiments of the present disclosure, after forming the p-type epitaxial layer in the recess, the method further includes removing the mask layer; forming a sacrificial oxide layer covering the substrate and the p-type epitaxial layer; forming a sacrificial oxide layer Thereafter, a plurality of n-type source regions are formed in the p-type epitaxial layer, the n-type source regions are in contact with the sacrificial oxide layer; a p-type doped region is formed in the p-type epitaxial layer, and the p-type doped region is located Between these n-type source regions; after forming the p-type doping region, the sacrificial oxide layer is removed, and the n-type source regions in the substrate, the hole barrier layer, and the p-type epitaxial layer are exposed and p a doped region; forming a gate oxide layer covering the substrate, the hole barrier layer, and the n-type source region and the p-type doped region in the p-type epitaxial layer; forming a patterned gate layer on the gate oxide layer The patterned gate layer has a second opening, and the second opening is located above the p-type doping region and the n-type source regions.

Making a semiconductor element according to one or more embodiments of the present disclosure The method further includes forming an interlayer dielectric layer over the patterned gate layer; and forming an electrode layer on the p-type doped region and the interlayer dielectric layer and contacting the p-type doped region.

According to one or more embodiments of the present disclosure, after forming the interlayer dielectric layer to cover the gate layer, a portion of the n-type source region is exposed.

100‧‧‧Substrate

110‧‧‧p-type doped layer

120‧‧‧n type buffer layer

130‧‧‧n type drift layer

140‧‧‧ patterned mask layer

150‧‧‧first opening

160‧‧‧ Groove

162‧‧‧ bottom

164‧‧‧ side wall

170‧‧‧ hole barrier

180‧‧‧p type epitaxial layer

210, 310‧‧‧ Sacrificial oxide layer

220, 320‧‧‧ gate oxide layer

230, 330‧‧‧ patterned gate layer

240, 340‧‧‧ second opening

250, 260, 350, 360‧‧‧n type source regions

270, 370‧‧‧p-type doped region

280, 380‧‧ ‧ interlayer dielectric layer

290, 390‧‧‧ electrode layer

300‧‧‧ gate structure

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. Detailed description of the drawings is as follows: FIG. 1 illustrates a process for fabricating a semiconductor device in accordance with certain embodiments of the present disclosure. FIG. 2 is a cross-sectional view of a semiconductor element in a process of fabricating a semiconductor device in accordance with some embodiments of the present disclosure; and FIG. 3 is a cross-sectional view of the semiconductor device in accordance with the present disclosure. Some embodiments, a cross-sectional view of a semiconductor element in a stage in a process of fabricating a semiconductor device; and FIG. 4 is a cross-sectional view of a semiconductor device in a stage in a process of fabricating a semiconductor device in accordance with certain embodiments of the present disclosure. 5 is a cross-sectional view of a semiconductor device in a stage in a process of fabricating a semiconductor device in accordance with some embodiments of the present disclosure; and FIG. 6 illustrates a process of fabricating a semiconductor device in accordance with certain embodiments of the present disclosure. A cross-sectional view of a semiconductor component in one stage; and FIGS. 7A-7E illustrate a process of fabricating a semiconductor device in accordance with certain embodiments of the present disclosure A cross-sectional view of a semiconductor element stages; 8A-8E are cross-sectional views of semiconductor components at various stages in the fabrication of semiconductor devices in accordance with certain embodiments of the present disclosure.

The following disclosure provides many different embodiments, or examples, to construct different features of the subject matter provided. Specific examples of the components and arrangements described below are intended to simplify the disclosure. These are of course only examples and their purpose is not to be construed as limiting. For example, the dimensions of the components are not limited by the scope or value disclosed, but may depend on the process conditions and/or desired characteristics of the components. Furthermore, the description in which the first feature is formed on or over the second feature includes an embodiment in which the first feature and the second feature are in direct contact, and other features are included between the first feature and the second feature, such that An embodiment in which a feature and a second feature are not in direct contact. For simplicity and clarity, different features may be arbitrarily drawn to different sizes.

Furthermore, spatially relative terms such as "beneath", "below", "lower", "above", "upper" And the like, for ease of description of the relationship between the elements or features and other elements or features illustrated in the drawings. Spatially relative terms, in addition to the directions depicted in the figures, also encompass different orientations of the components in use or operation. The instrument can be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative description used herein can be interpreted as such.

1-8F are schematic cross-sectional views showing semiconductor elements in different process stages in accordance with various embodiments of the present invention. First, please refer to the first The figure provides a substrate 100. In some embodiments, the substrate 100 includes a p-type doped layer 110, an n-type buffer layer 120, and an n-type drift layer 130. The material of the substrate 100 may comprise silicon, silicon carbide or other suitable materials.

Thereafter, a patterned mask layer 140 is formed on the substrate 100. The patterned mask layer 140 has a first opening 150 that exposes a portion of the substrate 100. In some embodiments, the patterned mask layer 140 is formed on the n-type drift layer 130. In some embodiments, the material of the patterned mask layer 140 can comprise ceria, other oxides, or other suitable materials.

Referring to FIG. 2, the exposed portion of the substrate 100 is removed to form the recess 160 in the substrate 100. The groove 160 has a bottom 162 and a side wall 164. In some embodiments, the exposed portion of substrate 100 can be removed using a suitable process, such as dry etching or wet etching. In certain embodiments, where the substrate 100 comprises tantalum, the depth of the grooves 160 is from about 1 [mu]m to about 10 [mu]m. In certain embodiments, where the substrate 100 comprises tantalum carbide, the depth of the grooves 160 is from about 1 [mu]m to about 3 [mu]m. Notably, in some embodiments, the patterned mask layer 140 acts as a mask in an etch process that removes exposed portions of the substrate 100.

Next, referring to FIG. 3, the first n-type dopant is doped at the bottom 162 and the sidewall 164 of the recess 160 via the first opening 150 to form the hole barrier layer 170. In some embodiments, the hole barrier layer 170 surrounds the bottom 162 and sidewalls 164 of the recess 160. In certain embodiments, the first n-type dopant can comprise nitrogen (Nitrogen) or phosphorous or arsenic. In some embodiments, doping the first n-type dopant can comprise using an ionic implantation or a plasma ion implant immersion. In some embodiments, the first n-type dopant has a doping concentration of from about 1 x 10 ¹⁵ cm ^-3 to about 5 x 10 ¹⁹ cm ^-3 .

Next, referring to FIG. 4, a p-type epitaxial layer 180 is formed in the recess 160. In some embodiments, forming the p-type epitaxial layer 180 can be accomplished using a suitable process, such as selective epitaxial growth. Since epitaxy is more difficult to form on the oxide, the patterned mask layer 140 can be utilized such that the p-type epitaxial layer 180 is formed in the recess 160. It should be noted that since the process of forming the p-type epitaxial layer 180 needs to be performed in a high temperature environment, the high temperature environment can diffuse the first n-type dopant of the hole barrier layer 170, so that the hole barrier layer 170 The thickness is thickened. By increasing the thickness of the hole barrier layer 170 by the environment in which the p-type epitaxial layer 180 is formed, the process can be simplified without additionally performing a warming process to diffuse the first n-type dopant of the hole barrier layer 170. In some embodiments, after forming the p-type epitaxial layer 180, the thickness of the hole blocking layer 170 may be less than or equal to 3 μm. In some embodiments in which the substrate 100 comprises tantalum, the hole barrier layer 170 can have a thickness of from about 0.5 [mu]m to about 3 [mu]m. In some embodiments in which the substrate 100 comprises tantalum carbide, the thickness of the hole barrier layer 170 may be less than or equal to 0.5 μm.

Referring to FIG. 5, after the p-type epitaxial layer 180 is formed, a chemical-mechanical polishing (CMP) is performed to planarize the p-type epitaxial layer 180. It should be noted that in some embodiments, after planarizing the p-type epitaxial layer 180 by a chemical mechanical polishing process, the p-type Lei near the patterned mask layer 140 is limited by the chemical mechanical polishing process itself. The portion of the layer 180 still has an uneven surface.

Next, referring to FIG. 6, the patterned mask layer 140 is removed to expose the surface of the substrate 100, the surface of the hole barrier layer 170, and the surface of the p-type epitaxial layer 180. In some embodiments, after this step, the p-type epitaxial layer 180 has an uneven surface on both sides. Embodiments of the present invention also provide a planarization method for planarizing uneven surfaces on both sides of the p-type epitaxial layer 180, as described in the following FIGS. 7A-7B and 8A-8C. In some embodiments, removing the patterned mask layer 140 can be accomplished in a suitable manner, such as a dry etch process or a wet etch process.

According to some embodiments of the present invention, the process illustrated in FIGS. 7A-7E can be applied to a semiconductor device including a germanium substrate 100, and after performing the process illustrated in FIG. 6, performing the processes shown in FIGS. 7A-7E Process. In FIG. 7A, a sacrificial oxide layer 210 is formed on the substrate 100. It is to be noted that the sacrificial oxide layer 210 is conformally formed on the substrate 100, that is, the uneven surface on both sides of the p-type epitaxial layer 180 originally in FIG. 6 is oxidized. In addition, since the sacrificial oxide layer 210 is formed in a high temperature environment, the high temperature environment can also diffuse the p-type dopant of the p-type epitaxial layer 180 into the substrate 100 such that the thickness of the p-type epitaxial layer 180 increase. By increasing the thickness of the p-type epitaxial layer 180 by the environment in which the sacrificial oxide layer 210 is formed, the process of the process can be reduced without additionally performing a warming process to diffuse the p-type dopant of the p-type epitaxial layer 180. In some embodiments, the material of the sacrificial oxide layer 210 can be a tantalum oxide such as hafnium oxide (SiO ₂ ).

Referring to FIG. 7B, the sacrificial oxide layer 210 is removed to planarize the surface of the p-type epitaxial layer 180, and the substrate 100, the hole barrier layer 170, and the p-type epitaxial layer 180 are exposed. It is worth noting that the sacrificial oxide layer 210 is removed. Thereafter, the uneven surface on the p-type epitaxial layer 180 is also removed. Still further, in some embodiments, the surface of the p-type epitaxial layer 180 is coplanar with the surface of the substrate 100.

Referring to FIG. 7C, a gate oxide layer 220 is formed on the substrate 100, the hole barrier layer 170, and the p-type epitaxial layer 180, wherein the gate oxide layer 220 covers the surface of the substrate 100 and the hole barrier layer 170. The surface and the surface of the p-type epitaxial layer 180. In some embodiments, the material of the gate oxide layer 220 can be a tantalum oxide such as hafnium oxide (SiO ₂ ). In some embodiments, the gate oxide layer 220 can be formed using a thermal oxidation process or a deposition process.

Referring to FIG. 7D, a patterned gate layer 230 is formed on the gate oxide layer 220. The patterned gate layer 230 has a second opening 240 above the p-type epitaxial layer 180. Then, a second n-type dopant is doped in the p-type epitaxial layer 180 via the second opening 240 to form an n-type source region 250 and an n-type source region 260 in the p-type epitaxial layer 180. In some embodiments, the n-type source region 250 and the n-type source region 260 are formed by first doping a second n-type dopant into the p-type epitaxial layer 180, and then performing an annealing process to make the second The n-type dopant diffuses. In some embodiments, both edges of the second opening 240 are aligned with the n-type source region 250 and the n-type source region 260, respectively. In some embodiments, both the n-type source region 250 and the n-type source region 260 are in contact with the gate oxide layer 220. In some embodiments, the material of the patterned gate layer 230 can be, for example, a polysilicon. In some embodiments, the gate oxide layer 220 may be formed by first forming a gate layer (not shown), and then an etching process may be performed to remove a portion of the gate layer to form a second opening 240 to form a patterned gate. Polar layer 230. In some embodiments, forming the second opening 240 can be accomplished using dry etching or wet etching. In a certain In some embodiments, the second n-type dopant may comprise phosphorum or arsenic.

Referring to FIG. 7E, an interlayer dielectric layer 280 is formed to cover the patterned gate layer 230, wherein the interlayer dielectric layer 280 also covers a portion of the gate oxide layer 220. In one embodiment, a dielectric layer (not shown) is first blanket deposited, and then a photolithography process is performed to form an interlayer dielectric layer 280. It is worth noting that during the etching process, a portion of the gate oxide layer 220 is also removed, and a portion of the n-type source region 250, a portion of the n-type source region 260, and a portion of the p-type Lei are exposed. Crystal layer 180. Still further, the edges of the interlayer dielectric layer 280 are aligned with the edges of the gate oxide layer 220.

After the interlayer dielectric layer 280 is formed, a p-type doped region 270 is formed in the p-type epitaxial layer 180, wherein the p-type doped region 270 is located between the n-type source region 250 and the n-type source region 260. In some embodiments, the p-type doped region 270 is formed by first doping a p-type dopant into the p-type epitaxial layer 180 and then performing an annealing process. After the interlayer dielectric layer 280 is formed, the annealing process of the p-type epitaxial layer 180 is performed to facilitate planarization and smoothing of the interlayer dielectric layer 280. In some embodiments, the p-doped region 270 is formed using an ion implantation process.

Then, as shown in FIG. 7E, an electrode layer 290 is formed on the interlayer dielectric layer 280 and the p-type doping region 270, wherein the electrode layer 290 is in contact with the p-type doping region 270. Still further, the electrode layer 290 is also in contact with a portion of the n-type source region 250 and a portion of the n-type source region 260. In some embodiments, the material of electrode layer 290 is a metal.

According to some embodiments of the present invention, the process illustrated in FIGS. 8A-8E can be applied to a semiconductor device in which the substrate 100 comprises tantalum carbide. In some embodiments, after the process illustrated in FIG. 6 is performed, the process illustrated in FIGS. 8A-8E is performed. Referring to FIG. 8A, a sacrificial oxide layer 310 is formed on the substrate 100. The sacrificial oxide layer 310 is conformally formed on the substrate 100, that is, the uneven surface on both sides of the p-type epitaxial layer 180 originally in FIG. 6 is oxidized. Since the sacrificial oxide layer 310 is formed in a high-temperature environment, the p-type dopant of the p-type epitaxial layer 180 can be diffused into the substrate 100 in a high-temperature environment, so that the thickness of the p-type epitaxial layer 180 is increased. . By diffusing the p-type dopant by the high temperature environment in which the sacrificial oxide layer 310 is formed, the thickness of the p-type epitaxial layer 180 is increased, and the process of the process can be reduced without additionally performing a heating process such as annealing. In some embodiments, the material of the sacrificial oxide layer 310 can be a tantalum oxide such as hafnium oxide (SiO ₂ ). Notably, in embodiments where the substrate comprises tantalum carbide, the thickness of the sacrificial oxide layer is less than the thickness of the sacrificial oxide layer of the embodiment in which the substrate comprises tantalum.

Referring to FIG. 8B, an n-type source region 350 and an n-type source region 360 are formed in the p-type epitaxial layer 180. In some embodiments, the n-type source region 350 and the n-type source region 360 are in contact with the sacrificial oxide layer 310. In FIG. 8B, a p-type doping region 370 is also formed in the p-type epitaxial layer 180. In some embodiments, p-doped region 370 is disposed between n-type source region 350 and n-type source region 360. In some embodiments, p-type doped region 370 is in contact with sacrificial oxide layer 310. In some embodiments, the p-doped region 270 is formed using an ion implantation process. Since the surface property at a high temperature is unstable in the semiconductor element in which the substrate 100 contains tantalum carbide, it is necessary to control the process temperature and time more accurately. If there are multiple temperature changes in the process, it will increase the difficulty of the process, so it can be performed after doping the second n-type dopant and the p-type dopant. Fire process to reduce the difficulty of the process.

Referring to FIG. 8C, the sacrificial oxide layer 310 is removed to expose the substrate 100, the hole barrier layer 170, the p-type epitaxial layer 180, the n-type source region 350, the n-type source region 360, and the p-type doping. Area 370. After the sacrificial oxide layer 310 is removed, the uneven surface on the p-type epitaxial layer 180 is also removed to planarize the surface of the p-type epitaxial layer 180.

Referring to FIG. 8D, the gate oxide layer 320 is formed to cover the n-type source region 350, the n-type source region 360, and the p-type doping region in the substrate 100, the hole barrier layer 170, and the p-type epitaxial layer 180. 370. In some embodiments, the gate oxide layer 320 can be formed using a thermal oxidation process or a deposition process. In some embodiments, the material of the gate oxide layer 320 can be a tantalum oxide such as hafnium oxide (SiO ₂ ).

As shown in FIG. 8D, after the gate oxide layer 320 is formed, a patterned gate layer 330 is formed on the gate oxide layer 320. The patterned gate layer 330 has a second opening 340 that is above the p-type epitaxial layer 180. In more detail, the second opening 340 is located above the n-type source region 350, the n-type source region 360, and the p-type doping region 370. It should be noted that in some embodiments, the two edges of the second opening 340 are respectively aligned with the n-type source region 350 and the n-type source region 360, respectively. In some embodiments, n-type source region 350, n-type source region 360, and p-type doped region 370 are all in contact with gate oxide layer 320. In some embodiments, the material of the patterned gate layer 330 can be, for example, a polysilicon. In some embodiments, the gate oxide layer 320 may be formed by first forming a gate layer (not shown), and then an etching process may be performed to remove a portion of the gate layer to form a second opening 240 to form a patterned gate. Polar layer 230. In some embodiments, the shape The second opening 240 can be achieved using dry etching or wet etching.

Referring to FIG. 8E, an interlayer dielectric layer 380 is formed to cover the patterned gate layer 330, wherein the interlayer dielectric layer 380 also covers a portion of the gate oxide layer 320. In one embodiment, a dielectric layer (not shown) is first blanket deposited, and then a photolithography process is performed to form an interlayer dielectric layer 380. It is worth noting that during the etching process, a portion of the gate oxide layer 320 is also removed, and a portion of the n-type source region 350, a portion of the n-type source region 360, and the p-type doped region are exposed. 370. Still further, the edges of the interlayer dielectric layer 380 are aligned with the edges of the gate oxide layer 320.

After the interlayer dielectric layer 380 is formed, the electrode layer 390 is formed on the interlayer dielectric layer 380 and the p-type doping region 370, wherein the electrode layer 390 is in contact with the p-type doping region 370. Still further, electrode layer 390 is also in contact with a portion of n-type source region 350 and a portion of n-type source region 360. In some embodiments, the material of electrode layer 390 is a metal.

Referring to FIG. 8E , an embodiment of the present invention also provides a semiconductor device structure including a substrate 100 , a p-type epitaxial layer 180 , a hole barrier layer 170 , and a gate structure 300 . The p-type epitaxial layer 180 is embedded in the substrate 100. The hole barrier layer 170 is located in the substrate 100 and surrounds the p-type epitaxial layer 180. In some embodiments, the p-type epitaxial layer 180 includes an n-type source region 350, an n-type source region 360, and a p-type doping region 370, wherein the p-type doping region 370 is located in the n-type source region 350 and Between the n-type source regions 360. The gate structure 300 is located on the substrate 100 and the p-type epitaxial layer 180. In some embodiments, the gate structure 300 includes a patterned gate layer 330 and a gate oxide layer 320, wherein the patterned gate layer 330 is disposed on the gate oxide layer 320. In some implementations In the example, a portion of the n-type source region 350 and a portion of the n-type source region 360 are in contact with the gate oxide layer 320. In some embodiments, the substrate 100 includes a p-type doped layer 110 , an n-type buffer layer 120 , and an n-type drift layer 130 , wherein the n-type buffer layer 120 is between the p-type doped layer 110 and the n-type drift layer 130 . .

In some embodiments, the semiconductor device structure further includes an interlayer dielectric layer 380 and an electrode layer 390. An interlayer dielectric layer 380 covers the patterned gate layer 330. In some embodiments, the interlayer dielectric layer 380 also covers a portion of the gate oxide layer 320. In some embodiments, electrode layer 390 is in contact with p-type doped region 370.

The fabrication method and structure provided by the embodiments of the present invention can be applied to various semiconductor elements, such as power semiconductor elements. In more detail, the fabrication method and structure provided by the embodiments of the present invention can be applied to an insulated gate bipolar transistor (IGBT). In addition, the process provided by the embodiment of the present invention may also be used for a semiconductor element including a substrate of tantalum or tantalum carbide, but is not limited thereto.

Certain embodiments have been described in detail in the embodiments of the invention, but other embodiments are also possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.

The embodiments of the present invention have been disclosed in the above embodiments, and are not intended to limit the disclosure. Anyone skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection disclosed is subject to the definition of the scope of the patent application.

Claims (11)

A method of fabricating a semiconductor device, comprising: providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer having a first opening exposing a portion of the substrate; removing the exposed a portion of the substrate to form a recess in the substrate, the recess having a bottom and a sidewall; wherein the bottom and the sidewall are doped with a first n-type via the first opening a dopant to form a hole barrier layer surrounding the bottom and the sidewall of the recess; and forming a p-type epitaxial layer in the recess. The method of fabricating a semiconductor device according to claim 1, wherein the substrate comprises a p-type doped layer, an n-type buffer layer and an n-type drift layer, wherein the n-type buffer layer is located in the p-type doped layer Between the n-type drift layers. The method of fabricating a semiconductor device according to claim 1, wherein the hole barrier layer has a doping concentration of 1 × 10 ^{15 -} 5 × 10 ¹⁹ cm ^-3 . A method of fabricating a semiconductor device according to claim 1, wherein doping the first n-type dopant at the bottom and the sidewall of the recess via the first opening comprises using ion implantation or plasma ion infiltration. The method of fabricating a semiconductor device according to claim 1, wherein the thickness of the hole barrier layer is less than or equal to 3 μm after the p-type epitaxial layer is formed in the recess. A method of fabricating a semiconductor device according to claim 1, wherein the recess has a depth of from about 1 μm to about 10 μm. The method of fabricating a semiconductor device according to claim 1, after forming the p-type epitaxial layer in the recess, further comprising: planarizing the p-type epitaxial layer, wherein planarizing the p-type epitaxial layer comprises Removing a portion of the p-type epitaxial layer and the patterned mask layer to expose a surface of the substrate, a surface of the hole barrier layer, and a surface of the p-type epitaxial layer; forming a gate An oxide layer covering the surface of the substrate, the surface of the hole barrier layer, and the surface of the p-type epitaxial layer; forming a patterned gate layer on the gate oxide layer, wherein the patterned gate The layer has a second opening on the p-type epitaxial layer; a second n-type dopant is doped in the p-type epitaxial layer via the second opening to form a plurality of n-type source regions; An inter-layer dielectric layer covers the patterned gate layer; after forming the interlayer dielectric layer, a p-type doped region is formed on the p-type epitaxial layer, and the p-type doped region is located at the n-type source Between the polar regions; and forming an electrode layer on the p-type doped region and the interlayer dielectric layer, and in contact with the p-type doped region. The method of fabricating a semiconductor device according to claim 7, wherein planarizing the p-type epitaxial layer comprises: removing a portion of the p-type epitaxial layer using a chemical mechanical polishing process; removing the patterned mask layer, And exposing the substrate; forming a sacrificial oxide layer covering the p-type epitaxial layer and the substrate; and removing the sacrificial oxide layer. The method for fabricating a semiconductor device according to claim 1, after forming the p-type epitaxial layer in the recess, further comprising: removing the mask layer; forming a sacrificial oxide layer covering the substrate and the p a type of epitaxial layer; after forming the sacrificial oxide layer, forming a plurality of n-type source regions in the p-type epitaxial layer, the n-type source regions are in contact with the sacrificial oxide layer; and the p-type epitaxial layer Forming a p-type doped region, and the p-type doped region is located between the n-type source regions; after forming the p-type doped region, removing the sacrificial oxide layer to expose the substrate a hole barrier layer, the n-type source regions and the p-type doped region in the p-type epitaxial layer; forming a gate oxide layer covering the substrate, the hole barrier layer, and the p-type The n-type source regions and the p-type doped regions in the epitaxial layer; and forming a patterned gate layer on the gate oxide layer, wherein the patterned gate layer has a second opening The p-type doped region and the n-type source regions are above. The method of fabricating a semiconductor device according to claim 9, further comprising: forming an interlayer dielectric layer covering the patterned gate layer; and forming an electrode layer on the p-type doped region and the interlayer dielectric layer, And contacting the p-type doping region. The method of fabricating a semiconductor device according to claim 10, after forming the interlayer dielectric layer to cover the gate layer, exposing a portion of the n-type source region.