KR20040021037A - semiconductor device - Google Patents
semiconductor device Download PDFInfo
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- KR20040021037A KR20040021037A KR1020020052471A KR20020052471A KR20040021037A KR 20040021037 A KR20040021037 A KR 20040021037A KR 1020020052471 A KR1020020052471 A KR 1020020052471A KR 20020052471 A KR20020052471 A KR 20020052471A KR 20040021037 A KR20040021037 A KR 20040021037A
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- bridge
- contact plate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4007—Shape of bonding interfaces, e.g. interlocking features
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40095—Kinked
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
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- H—ELECTRICITY
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8434—Bonding interfaces of the connector
- H01L2224/84345—Shape, e.g. interlocking features
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/84385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Computer Hardware Design (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로, 더욱 상세하게 설명하면 반도체 다이와 접촉 플레이트 사이를 전기적으로 연결하는 브릿지가 자기 정렬되고, 그 브릿지의 이탈을 방지할 수 있는 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of self-aligning a bridge connecting electrically between a semiconductor die and a contact plate and preventing the bridge from being separated.
일반적으로 반도체 패키지는 반도체 다이를 전기적으로 연결해주고, 밀봉 포장을 해주어 반도체 다이가 외부의 화학적, 기계적 환경으로부터 보호받을 수 있도록 하여 반도체 다이가 제 기능을 수행할 수 있도록 한 것을 말한다.In general, a semiconductor package electrically connects a semiconductor die and seals the packaging so that the semiconductor die can be functioned by protecting the semiconductor die from external chemical and mechanical environments.
이러한 반도체 패키지는 매우 다양한 종류가 있으며, 여기서는 첨부된 도1a 및 도1b를 참조하여 종래의 한 반도체 패키지를 설명한다. 상기 첨부된 도1a는 종래 반도체 패키지에 이용된 다이패드, 접촉 플레이트 및 브릿지를 도시한 평면도이고, 도1b는 반도체 패키지를 도시한 단면도이다.There are a wide variety of such semiconductor packages, and a conventional semiconductor package will be described with reference to FIGS. 1A and 1B. 1A is a plan view illustrating a die pad, a contact plate, and a bridge used in a conventional semiconductor package, and FIG. 1B is a cross-sectional view illustrating a semiconductor package.
도시된 바와 같이 종래의 반도체 패키지(100')는 대략 사각판 형태로서 일측에 업셋 영역(102')과 리드(104')가 연결된 다이패드(106')와, 상기 다이패드(106')의 상면에 솔더(108')로 접착된 반도체 다이(110')와, 상기 반도체 다이(110')의 상면에 역시 솔더(108')로 고정되고 일측에는 다운셋된 돌기부(112')가 형성된 브릿지(116')와, 상기 브릿지(116')의 돌기부(112')가 결합 및 고정되도록 양측에 절개부(130')가 형성되고, 일측에는 리드(124')가 형성된 접촉 플레이트(126')와, 상기 다이패드(106'), 반도체 다이(110'), 브릿지(116') 및 접촉 플레이트(126')가 몰딩되되 상기 다이패드(106') 및 접촉 플레이트(126')에 형성된 리드(124')는 외부로 돌출 및 노출되도록 하는 몰딩 컴파운드(128')로 이루어져 있다.As shown in the drawing, the semiconductor package 100 'has a substantially rectangular plate shape, and has a die pad 106' having an upset region 102 'and a lead 104' connected to one side thereof, and a shape of the die pad 106 '. A bridge having a semiconductor die 110 ′ bonded to the upper surface of the semiconductor die 110 ′ and a protrusion 112 ′ fixed to the upper surface of the semiconductor die 110 ′ with the solder 108 ′ and downset on one side thereof. 116 'and cutouts 130' are formed at both sides to couple and fix the protrusion 112 'of the bridge 116', and a contact plate 126 'having a lead 124' formed at one side thereof. And a lead formed on the die pad 106 'and the contact plate 126' by molding the die pad 106 ', the semiconductor die 110', the bridge 116 ', and the contact plate 126'. 124 'consists of a molding compound 128' that protrudes and is exposed to the outside.
이러한 반도체 패키지(100')의 제조 방법은 통상 다이패드(106')와 접촉 플레이트(126')가 일체로 형성된 리드프레임(도시되지 않음)을 이용하는데 다음과 같은 단계로 이루어진다.The method of manufacturing the semiconductor package 100 'generally uses a lead frame (not shown) in which the die pad 106' and the contact plate 126 'are integrally formed.
리드프레임의 다이패드(106')에 솔더(108')를 이용하여 반도체 다이(110')를 고정시키는 단계와, 상기 반도체 다이(110')와 접촉 플레이트(126')를 상부에서 브릿지(116')로 임시 연결하는 단계와, 상기 브릿지(116')와 접촉된 반도체 다이(110') 및 접촉 플레이트(126')에 솔더(108')를 리플로우(reflow)하여 상기 브릿지(116')가 반도체 다이(110') 및 접촉 플레이트(126')에 완전 고정되도록 하는 단계와, 상기 다이패드(106'), 접촉 플레이트(126'), 반도체 다이(110') 및 브릿지(116')를 몰딩 컴파운드(128')로 몰딩하는 단계와, 상기 리드프레임에서 반도체 다이(110') 및 접촉 플레이트(126')에 연결된 리드(104')(124')의 단부를 컷팅하는 단계로 이루어져 있다.Fixing the semiconductor die 110 'using a solder 108' to the die pad 106 'of the leadframe, and connecting the semiconductor die 110' and the contact plate 126 'from the top of the bridge 116. Temporary connection to the "), and reflow the solder 108 'to the semiconductor die 110' and the contact plate 126 'in contact with the bridge 116' to bridge the 116 '. The die pad 106 ', the contact plate 126', the semiconductor die 110 ', and the bridge 116' to be fully secured to the semiconductor die 110 'and the contact plate 126'. Molding into molding compound 128 'and cutting the ends of leads 104' and 124 'connected to semiconductor die 110' and contact plate 126 'in the leadframe.
그러나, 이러한 종래의 반도체 패키지는 제조 공정중 반도체 다이와 접촉 플레이트를 브릿지로 연결 및 고정하는 단계에서 솔더의 리플로우시에 상기 브릿지의위치가 변경되는 문제가 있다. 즉, 상기 브릿지의 다운셋 돌기부가 비록 접촉 플레이트의 절개부에 결합되기는 하지만, 솔더 리플로우시에 상기 솔더의 유동성으로 인하여 반도체 다이 상면에 위치되는 브릿지의 위치가 틀어지고 이에 따라 브릿지의 연결 불량이 다량으로 발생하는 문제가 있다. 더불어, 상기 솔더의 리플로우시에 상기 브릿지의 다운셋된 돌기부가 접촉 플레이트의 절개부에서 상부 및 수평 방향으로 움직여 결국 브릿지가 접촉 플레이트에서 이탈되는 현상도 발생한다.However, such a conventional semiconductor package has a problem in that the position of the bridge is changed during the reflow of solder in the step of connecting and fixing the semiconductor die and the contact plate with the bridge during the manufacturing process. That is, although the downset protrusion of the bridge is coupled to the cutout of the contact plate, the position of the bridge located on the upper surface of the semiconductor die is shifted due to the fluidity of the solder during solder reflow, thereby resulting in poor connection of the bridge. There is a problem that occurs in large quantities. In addition, when the solder reflows, the downset protrusion of the bridge moves upwardly and horizontally at the cutout of the contact plate, and thus the bridge is detached from the contact plate.
본 발명은 상기와 같은 종래의 문제를 해결하기 위해 안출한 것으로, 본 발명의 목적은 반도체 다이와 접촉 플레이트 사이를 전기적으로 연결하는 브릿지가 자기 정렬되고, 그 브릿지가 이탈되는 현상을 억제할 수 있는 반도체 패키지를 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above conventional problems, and an object of the present invention is to provide a semiconductor capable of suppressing a phenomenon in which a bridge electrically connecting between a semiconductor die and a contact plate is self-aligned and the bridge is separated. To provide a package.
도1a는 종래 반도체 패키지에 이용된 다이패드, 접촉플레이트 및 브릿지를 도시한 평면도이고, 도1b는 그 반도체 패키지를 도시한 단면도이다.FIG. 1A is a plan view showing a die pad, a contact plate, and a bridge used in a conventional semiconductor package, and FIG. 1B is a cross-sectional view showing the semiconductor package.
도2a는 본 발명에 의한 반도체 패키지에 이용된 다이패드, 접촉플레이트 및 브릿지를 도시한 평면도이고, 도2b는 그 반도체 패키지를 도시한 단면도이다.Fig. 2A is a plan view showing a die pad, a contact plate, and a bridge used in the semiconductor package according to the present invention, and Fig. 2B is a sectional view showing the semiconductor package.
도3a는 본 발명에 의한 반도체 패키지에 이용된 다이패드, 접촉플레이트 및 브릿지를 도시한 평면도이고, 도3b는 그 반도체 패키지를 도시한 단면도이다.Fig. 3A is a plan view showing a die pad, a contact plate and a bridge used in the semiconductor package according to the present invention, and Fig. 3B is a sectional view showing the semiconductor package.
도4a는 본 발명에 의한 반도체 패키지에 이용된 다이패드, 접촉플레이트 및 브릿지를 도시한 평면도이고, 도4b는 그 반도체 패키지를 도시한 단면도이다.4A is a plan view showing a die pad, a contact plate, and a bridge used in the semiconductor package according to the present invention, and FIG. 4B is a sectional view showing the semiconductor package.
도5a는 본 발명에 의한 반도체 패키지에 이용된 다이패드, 접촉플레이트 및 브릿지를 도시한 평면도이고, 도5b는 그 반도체 패키지를 도시한 단면도이다.Fig. 5A is a plan view showing a die pad, a contact plate and a bridge used in the semiconductor package according to the present invention, and Fig. 5B is a sectional view showing the semiconductor package.
-도면중 주요 부호에 대한 설명-Description of the main symbols in the drawings
200~500; 본 발명에 의한 반도체 패키지202; 업셋 영역200-500; A semiconductor package 202 according to the present invention; Upset area
204; 리드206; 다이패드204; Lead 206; Die pad
208; 솔더210; 반도체 다이208; Solder 210; Semiconductor die
212; 제1다운셋 영역214; 제2다운셋 영역212; First downset area 214; Second downset area
216; 브릿지218; 그루브216; Bridge218; Groove
222; 업셋 영역224; 리드222; Upset area 224; lead
226; 접촉 플레이트228; 몰딩 컴파운드226; Contact plate 228; Molding Compound
상기한 목적을 달성하기 위해 본 발명에 의한 반도체 패키지는 사각판 형태로서 일측에 업셋 영역과 리드가 연결된 다이패드와, 상기 다이패드의 상면에 솔더로 고정된 반도체 다이와, 상기 반도체 다이의 상면에 솔더로 고정되고 일측에는 하향 절곡된 제1다운셋 영역이 형성되고, 상기 제1다운셋 영역의 양측부에는 상기 제1다운셋 영역보다 더 하향절곡된 제2다운셋 영역이 형성된 브릿지와, 상기 브릿지의 제1다운셋 영역이 일측의 상면에 고정되도록 고정부가 형성되고, 타측에는 리드가 형성된 접촉 플레이트와, 상기 다이패드, 반도체 다이, 브릿지 및 접촉 플레이트가 몰딩되되, 상기 다이패드 및 접촉 플레이트에 형성된 리드는 외부로 돌출및 노출되도록 하는 몰딩 컴파운드로 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention has a die plate in which a upset region and a lead are connected to one side in a rectangular plate shape, a semiconductor die fixed with solder on an upper surface of the die pad, and a solder on an upper surface of the semiconductor die. A bridge having a first downset region fixed to and downwardly bent at one side, and a second downset region bent downwardly than the first downset region at both sides of the first downset region; A fixing part is formed to fix the first downset area of the upper surface of one side, and a contact plate on which the lead is formed and the die pad, the semiconductor die, the bridge, and the contact plate are molded, and formed on the die pad and the contact plate. The lid is made of a molding compound that protrudes and is exposed to the outside.
여기서, 상기 접촉 플레이트의 상면에 형성된 고정부는 그루브(groove), 코이닝(coining) 또는 상부로 업셋된 영역중 어느 하나일 수 있다.Herein, the fixing part formed on the upper surface of the contact plate may be any one of a groove, coining, or an upset area.
또한, 상기 고정부의 양측부에는 상기 브릿지의 제2다운셋 영역가 결합될 수 있도록 절개부가 더 형성될 수 있다.In addition, a cutout may be further formed at both sides of the fixing part so that the second downset area of the bridge may be coupled.
이와 같이 하여 본 발명에 의한 반도체 패키지에 의하면 브릿지에는 서로 다른 하향절곡 각도를 갖는 제1다운셋 영역 및 제2다운셋 영역이 형성되고, 상기 제1업셋 영역이 결합되어 움직이지 않도록 접촉 플레이트에는 그루브, 코이닝 또는 상부로 업셋된 영역이 형성됨으로써, 솔더 리플로우에 의해 브릿지를 접촉 플레이트에 완전 고정시 자기 정렬되도록 함과 동시에 브릿지의 위치 이탈 현상도 억제하게 된다.In this manner, according to the semiconductor package according to the present invention, the bridge is formed with a first downset region and a second downset region having different downward bend angles, and the contact plate is grooved so that the first upset region is coupled and not moved. By forming a coined or upset region, the solder reflow allows self-alignment when the bridge is fully fixed to the contact plate, and at the same time suppresses the dislocation of the bridge.
더불어, 상기 접촉 플레이트에는 그루브, 코이닝 또는 상부로 업셋된 영역 외에도 절개부가 형성된 경우에는 브릿지의 제2다운셋 영역이 상기 절개부에 결합됨으로써, 브릿지의 자기 정렬 작용은 더욱 극대화되고 또한 브릿지의 이탈 현상도 더욱 적극적으로 방지할 수 있다.In addition, when the cutout is formed in the contact plate in addition to the groove, coining, or upset area, the second downset area of the bridge is coupled to the cutout, thereby maximizing self-alignment of the bridge and also leaving the bridge. The phenomenon can be prevented more actively.
이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.
도2a를 참조하면 본 발명에 의한 반도체 패키지(200)에 이용된다이패드(206), 접촉 플레이트(226) 및 브릿지(216)의 평면도가 도시되어 있고, 도2b를 참조하면 그 반도체 패키지(200)의 단면도가 도시되어 있다.Referring to FIG. 2A, a plan view of the pad 206, the contact plate 226, and the bridge 216 used in the semiconductor package 200 according to the present invention is shown. Referring to FIG. 2B, the semiconductor package 200 is illustrated. A cross-sectional view of is shown.
도시된 바와 같이 본 발명에 의한 반도체 패키지(200)는 사각판 형태로서 일측에 업셋 영역(202)과 리드(204)가 연결된 다이패드(206)와, 상기 다이패드(206)의 상면에 솔더(208)로 고정된 반도체 다이(210)와, 상기 반도체 다이(210)의 상면에 솔더(208)로 고정되고 일측에는 하향 절곡된 제1다운셋 영역(212)이 형성되고, 상기 제1다운셋 영역(212)의 양측부에는 상기 제1다운셋 영역(212)보다 더 하향절곡된 제2다운셋 영역(214)이 형성된 브릿지(216)와, 상기 브릿지(216)의 제1다운셋 영역(212)이 일측의 상면에 고정되도록 고정부가 형성되고, 타측에는 업셋 영역(222) 및 리드(224)가 형성된 접촉 플레이트(226)와, 상기 다이패드(206), 반도체 다이(210), 브릿지(216) 및 접촉 플레이트(226)가 몰딩되되, 상기 다이패드(206) 및 접촉 플레이트(226)에 형성된 리드(204)(224)는 외부로 돌출 및 노출되도록 하는 몰딩 컴파운드(228)로 이루어져 있다.As shown, the semiconductor package 200 according to the present invention has a die plate 206 having an upset region 202 and a lead 204 connected to one side thereof in a rectangular plate shape, and a solder (upper surface) of the die pad 206. A semiconductor die 210 fixed by 208 and a first downset region 212 fixed to a top surface of the semiconductor die 210 by solder 208 and bent downward on one side thereof are formed. On both sides of the area 212, a bridge 216 having a second downset area 214 bent downward than the first downset area 212, and a first downset area of the bridge 216 ( A fixing part is formed to fix the upper surface 212 to one side, and the contact plate 226 having the upset region 222 and the lead 224 formed on the other side, the die pad 206, the semiconductor die 210, and the bridge ( 216 and the contact plate 226 are molded, the leads 204 and 224 formed in the die pad 206 and the contact plate 226 protrude outwards and And a molding compound 228 that is exposed.
여기서, 상기 접촉 플레이트(226)의 상면에 형성된 고정부는 단면상 대략 역삼각 모양으로 움푹 들어간 다수의 그루브(218)(groove)일 수 있으며, 상기 브릿지(216)의 제1다운셋 영역(212)의 단부는 상기 그루브(218)에 결합되어 수평 방향으로의 이탈이 억제된다. 물론, 상기 브릿지(216)의 제1다운셋 영역(212)과 상기 그루브(218)의 완전한 고정은 솔더(208)로 이루어진다.Here, the fixing portion formed on the upper surface of the contact plate 226 may be a plurality of grooves 218 (groove) recessed in a substantially inverted triangle shape in cross-section, the first downset area 212 of the bridge 216 An end portion is coupled to the groove 218 to suppress the deviation in the horizontal direction. Of course, the complete fixing of the first downset region 212 and the groove 218 of the bridge 216 is made of solder 208.
도3a를 참조하면 본 발명에 의한 다른 반도체 패키지(300)에 이용된 다이패드(306), 접촉 플레이트(326) 및 브릿지(316)의 평면도가 도시되어 있고, 도3b를 참조하면 그 반도체 패키지(300)의 단면도가 도시되어 있다. 여기서는 대부분의 구성이 상기 도2a 및 도2b에 도시된 반도체 패키지(200)와 유사하므로 그 차이점만을 설명하면 다음과 같다.Referring to FIG. 3A, a plan view of a die pad 306, a contact plate 326, and a bridge 316 used in another semiconductor package 300 according to the present invention is shown. Referring to FIG. 3B, the semiconductor package ( A cross-sectional view of 300 is shown. Here, since most configurations are similar to the semiconductor package 200 illustrated in FIGS. 2A and 2B, only the differences will be described below.
도시된 바와 같이 접촉 플레이트(326)의 상면에 형성된 고정부는 단면상 대략 사각 모양으로 움푹 파인 하나의 코이닝(318)(coining)일 수 있으며, 상기 브릿지(316)의 제1다운셋 영역(312)은 상기 코이닝(318)에 결합되어 수평 방향으로의 이탈이 억제된다. 상기 코이닝(318)은 통상 가압 기구에 의한 압착으로 형성될 수 있다.As shown, the fixing portion formed on the upper surface of the contact plate 326 may be a single coining 318 (coining) recessed in a substantially rectangular shape in cross-section, the first downset area 312 of the bridge 316 Is coupled to the coining 318 to suppress deviation in the horizontal direction. The coining 318 may be generally formed by pressing by a pressing mechanism.
도4a를 참조하면 본 발명에 의한 다른 반도체 패키지(400)에 이용된 다이패드(406), 접촉 플레이트(426) 및 브릿지(416)의 평면도가 도시되어 있고, 도4b를 참조하면 그 반도체 패키지(400)의 단면도가 도시되어 있다. 여기서는 대부분의 구성이 상기 도2a 및 도2b에 도시된 반도체 패키지(200)와 유사하므로 그 차이점만을 설명하면 다음과 같다.Referring to FIG. 4A, a plan view of a die pad 406, a contact plate 426, and a bridge 416 used in another semiconductor package 400 according to the present invention is shown. Referring to FIG. 4B, the semiconductor package ( A cross-sectional view of 400 is shown. Here, since most configurations are similar to the semiconductor package 200 illustrated in FIGS. 2A and 2B, only the differences will be described below.
도시된 바와 같이 접촉 플레이트(426)의 상면에 형성된 고정부는 상부로 업셋(up set)된 영역(418)일 수 있으며, 상기 브릿지(416)의 제1다운셋 영역(412)은 상기 업셋된 영역(418)에 의해 수평 방향으로의 이탈이 억제된다. 상기 업셋은 통상 포밍(forming) 기구에 의한 폼(form)으로 형성될 수 있다.As shown, the fixing part formed on the upper surface of the contact plate 426 may be an area 418 that is upset to the top, and the first downset area 412 of the bridge 416 is the upset area. Deviation to the horizontal direction is suppressed by 418. The upset may be formed in a form usually by a forming mechanism.
도5a를 참조하면 본 발명에 의한 다른 반도체 패키지(500)에 이용된 다이패드(506), 접촉 플레이트(526) 및 브릿지(516)의 평면도가 도시되어 있고, 도5b를 참조하면 그 반도체 패키지(500)의 단면도가 도시되어 있다. 여기서는 대부분의 구성이 상기 도3a 및 도3b에 도시된 반도체 패키지(300)와 유사하므로 그 차이점만을 설명하면 다음과 같다.Referring to FIG. 5A, a plan view of a die pad 506, a contact plate 526, and a bridge 516 used in another semiconductor package 500 according to the present invention is shown. Referring to FIG. 5B, the semiconductor package ( A cross-sectional view of 500 is shown. Here, since most configurations are similar to the semiconductor package 300 illustrated in FIGS. 3A and 3B, only the differences will be described below.
도시된 바와 같이 접촉 플레이트(526)의 상면에 형성된 고정부는 하나의 코이닝(518)(coining)과, 상기 코이닝(518)의 양측에 형성된 절개부(530)일 수 있다. 여기서, 상기 코이닝(518)에는 브릿지(516)의 제1다운셋 영역(512)이 결합되고, 상기 절개부(530)에는 브릿지(516)의 제2다운셋 영역(514)이 결합됨으로서, 상기 브릿지(516)의 수평 방향에 대한 이탈을 더욱 적극적으로 억제하게 된다.As illustrated, the fixing part formed on the upper surface of the contact plate 526 may be one coining 518 and a cutout 530 formed on both sides of the coining 518. Here, the first downset region 512 of the bridge 516 is coupled to the coining 518, and the second downset region 514 of the bridge 516 is coupled to the cutout 530. The departure of the bridge 516 in the horizontal direction is more actively suppressed.
이러한 본 발명에 의한 반도체 패키지(200)(여기서는 도2b에 도시된 반도체 패키지를 중심으로 설명함)는 통상 다이패드(206)와 접촉 플레이트(226)가 일체로 형성된 리드프레임(도시되지 않음)을 이용한다. 물론, 상기 리드프레임중 접촉 플레이트(226)의 상면에는 브릿지(216)의 제1다운셋 영역(212)이 고정될 수 있도록, 고정부가 형성되며 이는 그루브(218)(groove), 코이닝(318)(coining) 또는 상부로 업셋된 영역(418)중 어느 하나일 수 있다. 더불어, 상기 고정부의 양측부에는 상기 브릿지(216)의 제2다운셋 영역(214)이 결합될 수 있도록 절개부(530)가 더 형성될 수 있다.The semiconductor package 200 according to the present invention (which will be described with reference to the semiconductor package shown in FIG. 2B) will typically include a lead frame (not shown) in which the die pad 206 and the contact plate 226 are integrally formed. I use it. Of course, a fixing part is formed on the upper surface of the contact plate 226 of the lead frame so that the first downset area 212 of the bridge 216 may be fixed, which is a groove 218 or a coining 318. It may be either coining or upset region 418. In addition, cutouts 530 may be further formed at both sides of the fixing part so that the second downset area 214 of the bridge 216 may be coupled.
한편, 상기 브릿지(216)는 일측에 하향 절곡된 제1다운셋 영역(212)이 형성되고, 상기 제1다운셋 영역(212)의 양측부에는 상기 제1다운셋 영역(212)보다 더하향절곡된 제2다운셋 영역(214)이 형성된 것을 이용하며, 이러한 브릿지(216) 및 접촉 플레이트(226)의 모든 특징은 이미 설명했음으로 더 이상의 설명은 생략한다.Meanwhile, the bridge 216 has a first downset area 212 bent downward on one side thereof, and is further downwardly disposed on both sides of the first downset area 212 than the first downset area 212. The curved second downset region 214 is used, and all the features of the bridge 216 and the contact plate 226 have already been described, and thus, further description is omitted.
또한, 이러한 구조의 브릿지(216) 및 접촉 플레이트(226) 등을 이용한 본 발명에 의한 반도체 패키지(200)의 제조 방법 역시 리드프레임의 다이패드(206)에 솔더(208)를 이용하여 반도체 다이(210)를 고정시키는 단계와, 상기 반도체 다이(210)와 접촉 플레이트(226)를 상부에서 브릿지(216)로 임시 연결하는 단계와, 상기 브릿지(216)와 접촉된 반도체 다이(210) 및 접촉 플레이트(226)에 솔더(208)를 리플로우(reflow)하여 상기 브릿지(216)가 반도체 다이(210) 및 접촉 플레이트(226)에 완전 고정되도록 하는 단계와, 상기 다이패드(206), 접촉 플레이트(226), 반도체 다이(210) 및 브릿지(216)를 몰딩 컴파운드(228)로 몰딩하는 단계와, 상기 리드프레임에서 다이패드(206) 및 접촉 플레이트(216)에 연결된 리드(204)(224)의 단부를 컷팅하는 단계로 이루어져 있다.In addition, the method of manufacturing the semiconductor package 200 according to the present invention using the bridge 216 and the contact plate 226 having such a structure also uses a semiconductor die (using a solder 208 on the die pad 206 of the lead frame). Fixing the 210, temporarily connecting the semiconductor die 210 and the contact plate 226 from the top to the bridge 216, and the semiconductor die 210 and the contact plate in contact with the bridge 216. Reflowing the solder 208 to 226 such that the bridge 216 is fully secured to the semiconductor die 210 and the contact plate 226, and wherein the die pad 206, the contact plate ( 226, molding the semiconductor die 210 and the bridge 216 into the molding compound 228, and the leads 204 and 224 connected to the die pad 206 and the contact plate 216 in the leadframe. Cutting the ends.
여기서, 상기 브릿지(216)의 제1다운셋 영역(212)은 상기 접촉 플레이트(226)의 고정부 즉, 그루브(218), 코이닝(318), 상부로 업셋된 영역(418)에 결합된 채 솔더(208)가 리플로우됨으로써 완전 고정될 수 있다. 또한, 상기 고정부의 양측에 절개부(530)가 형성되었을 경우에는 상기 절개부(530)에 브릿지(216)의 제2다운셋 영역(214)이 결합됨으로서, 솔더(208)의 리플로우시에 브릿지(216)의 자기 정렬 효과를 극대화하고 또한 브릿지(216)의 위치 이탈을 더욱 적극적으로 억제하게 된다.Here, the first downset region 212 of the bridge 216 is coupled to the fixing portion of the contact plate 226, that is, the groove 218, the coining 318, the region 418 upwardly upset. Can be completely fixed by reflowing the solder 208. In addition, when the cutouts 530 are formed at both sides of the fixing part, the second downset region 214 of the bridge 216 is coupled to the cutouts 530 to reflow the solder 208. The self-alignment effect of the bridge 216 is maximized and the positional deviation of the bridge 216 is more actively suppressed.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만, 본 발명은 이것으로만 한정되는 것은 아니며 본 발명의 범주와 사상을 벗어나지 않는 범위내에서 여러가지로 변경된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modifications may be made without departing from the scope and spirit of the present invention.
이와 같이 하여 본 발명에 의한 반도체 패키지에 의하면 브릿지에는 서로 다른 하향절곡 각도를 갖는 제1다운셋 영역 및 제2다운셋 영역이 형성되고, 상기 제1업셋 영역이 결합되어 움직이지 않도록 접촉 플레이트에는 그루브, 코이닝 또는 상부로 업셋된 영역과 같은 고정부가 형성됨으로써, 솔더 리플로우에 의해 브릿지를 접촉 플레이트에 완전 고정시 자기 정렬되도록 함과 동시에 브릿지의 위치 이탈 현상도 억제할 수 있는 효과가 있다.In this manner, according to the semiconductor package according to the present invention, the bridge is formed with a first downset region and a second downset region having different downward bend angles, and the contact plate is grooved so that the first upset region is coupled and not moved. By forming a fixing part such as a coining or upwardly upset region, self-alignment when the bridge is completely fixed to the contact plate by solder reflow has an effect of suppressing the positional deviation of the bridge.
더불어, 상기 접촉 플레이트에는 그루브, 코이닝 또는 상부로 업셋된 영역 외에도 절개부가 형성된 경우에는 브릿지의 제2다운셋 영역이 상기 절개부에 결합됨으로써, 브릿지의 자기 정렬 작용은 더욱 극대화되고 또한 브릿지의 이탈 현상도 더욱 적극적으로 방지할 수 있는 효과가 있다.In addition, when the cutout is formed in the contact plate in addition to the groove, coining, or upset area, the second downset area of the bridge is coupled to the cutout, thereby maximizing self-alignment of the bridge and also leaving the bridge. The phenomenon can also be prevented more actively.
Claims (3)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013075108A1 (en) * | 2011-11-18 | 2013-05-23 | Texas Instruments Incorporated | Two level leadframe with upset ball bonding surface and device package |
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| KR920017219A (en) * | 1991-02-08 | 1992-09-26 | 아오이 죠이치 | Semiconductor device and manufacturing method of semiconductor device and tape carrier |
| KR930703703A (en) * | 1990-12-19 | 1993-11-30 | 토마스 에이. 멀바니 | Integrated circuit die-lead frame connection assembly system |
| KR20000020859U (en) * | 1999-05-14 | 2000-12-15 | 마이클 디. 오브라이언 | structure for lead frame in semiconductor package |
| KR20020018618A (en) * | 2000-08-31 | 2002-03-08 | 가네꼬 히사시 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930703703A (en) * | 1990-12-19 | 1993-11-30 | 토마스 에이. 멀바니 | Integrated circuit die-lead frame connection assembly system |
| KR920017219A (en) * | 1991-02-08 | 1992-09-26 | 아오이 죠이치 | Semiconductor device and manufacturing method of semiconductor device and tape carrier |
| KR20000020859U (en) * | 1999-05-14 | 2000-12-15 | 마이클 디. 오브라이언 | structure for lead frame in semiconductor package |
| KR20020018618A (en) * | 2000-08-31 | 2002-03-08 | 가네꼬 히사시 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2013075108A1 (en) * | 2011-11-18 | 2013-05-23 | Texas Instruments Incorporated | Two level leadframe with upset ball bonding surface and device package |
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