KR20040013974A - Method for forming dual damascene pattern - Google Patents
Method for forming dual damascene pattern Download PDFInfo
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- KR20040013974A KR20040013974A KR1020020047127A KR20020047127A KR20040013974A KR 20040013974 A KR20040013974 A KR 20040013974A KR 1020020047127 A KR1020020047127 A KR 1020020047127A KR 20020047127 A KR20020047127 A KR 20020047127A KR 20040013974 A KR20040013974 A KR 20040013974A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
Abstract
Description
본 발명은 이중 다마신 패턴(dual damascene pattern) 형성 방법에 관한 것으로, 특히, 메탈 라인(metal line)을 형성하기 위해 절연체에 이중 다마신 패턴을 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a dual damascene pattern, and more particularly, to a method of forming a dual damascene pattern on an insulator to form a metal line.
반도체가 고집적화 되어 구리 등 새로운 메탈을 이용한 배선 형성 방법이 등장함에 따라 새로운 배선 기술로서 하부 배선과 상부 배선을 전기적으로 연결하는 비아 콘택(via contact)과 상부 배선을 동시에 형성하는 소위 이중 다마신 기술이 그 해법으로 대두되었다.As semiconductors have been highly integrated and new methods of forming wires using copper, such as copper, have emerged, a new wiring technology, a so-called double damascene technology that simultaneously forms a via contact and an upper wiring that electrically connects the lower wiring and the upper wiring, has been developed. It was the solution.
도 1a 내지 도 1d는 종래의 기술에 따른 이중 다마신 패턴 형성 방법을 공정 단계별로 나타낸 순서도이다.1A to 1D are flowcharts illustrating a method of forming a dual damascene pattern according to the related art according to a process step.
먼저, 도 1a와 같이 하부 메탈(7) 위에 비아 콘택 식각 시의 에치 스톱층(etch stop layer)(3-1)을 형성한다. 표면에 절연막(2)을 형성한다. 표면에 트렌치 식각(trench etch) 시의 에치 스톱층(3-2)를 형성한다. 표면에 절연막(2)를 형성하여 이중 다마신 패턴 형성에 필요한 모든 층을 완성한다. 표면에 포토 레지스트(Photo Resist : PR)(1-1)를 코팅(coating)하고 노광 및 현상 공정을 통해 패터닝(patterning)한다.First, as shown in FIG. 1A, an etch stop layer 3-1 at the time of via contact etching is formed on the lower metal 7. The insulating film 2 is formed on the surface. An etch stop layer 3-2 during trench etch is formed on the surface. An insulating film 2 is formed on the surface to complete all the layers necessary for forming the double damascene pattern. Photoresist (PR) (1-1) is coated on the surface and patterned through exposure and development processes.
패터닝된 포토 레지스트(1-1)를 에치 마스크(etch mask)로 사용하여 도 1b와 같이 불필요한 절연막(2) 및 에치 스톱층(3-2)을 제거하여 비아 콘택(4)을 형성한다. 포토 레지스트(1-1)를 제거한다.By using the patterned photoresist 1-1 as an etch mask, the unnecessary insulating layer 2 and the etch stop layer 3-2 are removed as shown in FIG. 1B to form the via contact 4. The photoresist 1-1 is removed.
비아 콘택(4)에 도 1c와 같이 포토 레지스트나 ARC(Anti-Reflective Coating)(5)로 매립한다. 표면 양측에 트렌치 식각 용 포토 레지스트(1-2)를 패터닝한다. 상기 비아 콘택(4)의 매립은 후 공정에서 트렌치 형성을 위한 식각 시 비아 콘택(4)의 프로파일(profile)을 유지하는데 이용된다. 비아 콘택(4)에 포토 레지스트를 매립할 경우 이후 트렌치 식각용 포토 레지스트 패턴의 형성을 위하여 에치백으로 소정 두께의 포토 레지스트를 제거하는 공정이 요구된다. 반면, 비아 콘택(4)에 ARC(5)를 매립할 경우 그 상부에 바로 포토 레지스트를 코팅하여 트렌치 식각용 마스크 포토 레지스트 패턴을 형성할 수 있는 장점이 있다.The via contact 4 is filled with photoresist or ARC (Anti-Reflective Coating) 5 as shown in FIG. 1C. The photoresist for trench etching (1-2) is patterned on both sides of the surface. The filling of the via contact 4 is used to maintain the profile of the via contact 4 during etching for trench formation in a later process. When the photoresist is buried in the via contact 4, a process of removing the photoresist having a predetermined thickness with an etch back is required to form a photoresist pattern for trench etching. On the other hand, when the ARC 5 is buried in the via contact 4, the photoresist may be coated directly on the via contact 4 to form a mask photoresist pattern for trench etching.
식각 공정을 수행하여 도 1d 와 같이 트렌치(6)를 형성한다. 트렌치 식각 용 포토 레지스트(1-2)를 제거한다. 이 과정에서 비아 콘택(4) 상부의 프로파일을 유지하는 것이 중요하다. 또한 트렌치(6)의 코너 부분의 프로파일을 유지하는 것 또한 상당히 중요하다. 매립된 ARC(5)를 제거한다. 비아 콘택(4) 영역의 에치 스톱층(3-1)을 제거하여 완전한 비아 콘택을 형성한다. 이때, 비아 콘택(4)을 채우고 있는 물질이 보텀 코너 부분에서 완전히 제거되지 않아 저항 상승의 문제를 야기할 수 있다.An etching process is performed to form the trenches 6 as shown in FIG. 1D. Remove the trench resist photoresist 1-2. In this process, it is important to maintain the profile on the top of the via contact 4. It is also of great importance to maintain the profile of the corner portion of the trench 6. The embedded ARC 5 is removed. The etch stop layer 3-1 in the via contact 4 region is removed to form a complete via contact. At this time, the material filling the via contact 4 may not be completely removed at the bottom corner portion, which may cause a problem of resistance increase.
이와 같은 종래의 기술에 있어서는 에치 스톱층(3-1, 3-2)으로 실리콘 나이트라이드, 실리콘 카바이드 계열 등이 있는데 이와 같은 물질은 유전율이 절연막(2)으로 사용된 옥사이드(oxide)보다 높아 이중 다만신과 카퍼를 이용한 메탈 라인 형성의 단점으로 지적되고 있다.In such a conventional technique, the etch stop layers 3-1 and 3-2 include silicon nitride and silicon carbide. Such materials have a higher dielectric constant than oxide used as the insulating film 2. However, it has been pointed out as a disadvantage of metal line formation using a thinner and a copper.
상기한 바에 의하여 안출된 본 발명은, 질화물의 선택적 식각을 통해 이중 다마신 패턴을 형성하는 이중 다마신 패턴 형성 방법을 제공하는 데 그 목적이 있다.The present invention devised as described above is an object of the present invention to provide a dual damascene pattern forming method of forming a dual damascene pattern through selective etching of nitride.
도 1a 내지 도 1d는 종래의 기술에 따른 이중 다마신 패턴 형성 방법을 공정 단계별로 나타낸 순서도,1a to 1d is a flow chart showing a step-by-step process for forming a dual damascene pattern according to the prior art,
도 2a 내지 도 5b는 본 발명에 따른 이중 다마신 패턴 형성 방법을 공정 단계별로 나타낸 순서도로, 도 2a 및 도 2b는 트렌치 형성을 나타내는 도면, 도 3a 및 도 3b는 트렌치에 질화물을 채운 후 평탄화 형성울 나타내는 도면, 도 4a 및 도 4b는 비아 콘택 형성을 나타내는 도면, 도 5a 및 도 5b는 이중 다마신 패턴 형성을 나타내는 도면.2A to 5B are flow charts illustrating the step-by-step method of forming a dual damascene pattern according to the present invention. FIGS. 2A and 2B illustrate trench formation. FIGS. 4A and 4B show via contact formation, and FIGS. 5A and 5B show dual damascene pattern formation.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1 : 하부 메탈 2 : 에치 스톱층1: lower metal 2: etch stop layer
3 : 절연체 4, 4-1 : 포토 레지스트3: insulator 4, 4-1: photoresist
5 : 트렌치 6 : 질화물5: trench 6: nitride
7 : 비아 콘택7: Via contact
이하, 첨부된 도면을 참조하여 본 발명에 따른 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 5b는 본 발명에 따른 이중 다마신 패턴 형성 방법을 공정 단계별로 나타낸 순서도이다.2A through 5B are flowcharts illustrating a method of forming a dual damascene pattern according to the present invention.
도 2a 및 도 2b는 트렌치 형성을 나타내는 도면으로, 하부 메탈(1) 표면에 비아 콘택 식가 시 에치 스톱 기능을 수행할 에치 스톱층(2)을 형성한다. 상기 에치 스톱층(2)은 실리콘 카바이드 계열의 물질로 500 내지 1000Å의 두께로 이루어진다. 표면에 산화막 등의 절연체(3)를 형성한다. 트렌치 식각용 마스크를 이용하여 표면에 포토 레지스트(4)를 선택적으로 패터닝한다. 드라이 에치(dry etch)를 실시하여 절연치(3) 상측에 트렌치(5)를 형성한다. 상기 드라이 에치 시 CF 계열의 가스와 O2, CO, Ar 등의 가스를 조합한 플라즈마를 사용한다.2A and 2B illustrate trench formation, forming an etch stop layer 2 on the lower metal 1 surface to perform an etch stop function when a via contact is eaten. The etch stop layer 2 is made of silicon carbide-based material and has a thickness of 500 to 1000 mm 3. An insulator 3 such as an oxide film is formed on the surface. The photoresist 4 is selectively patterned on the surface by using a trench etching mask. Dry etch is performed to form the trench 5 above the insulated teeth 3. In the dry etching, a plasma using a combination of a CF-based gas and gases such as O 2, CO, and Ar is used.
도 3a 및 도 3b는 트렌치에 질화물을 채운 후 평탄화 형성울 나타내는 도면으로, 플라즈마를 이용한 실리콘 질화물 형성 기법으로 트렌치(5)에 질화물(6)을 채운다. 상기 질화물(6)을 이용하는 이유는 옥사이드 계열의 절연막(3)과 질화물(6)과의 높은 선택비를 이용하여 이 후 공정에서 잔존하는 질화물(6)을 완전히 제거하기 위해서이다. CMP(chemical mechanical polishing, 화학적 기계적 연마) 기법이나 에치백 기술을 이용하여 트렌치(5)를 채우고 있는 질화물(6)을 평탄화한다. 평탄화를 하는 이유는 이후 비아 콘택 에치를 위한 포토 레지스트 패턴을 안정적으로 형성하기 위해서이다.3A and 3B are diagrams showing planarization after filling the trenches with nitrides. The nitrides 6 are filled with the trenches 5 by a silicon nitride forming technique using plasma. The reason for using the nitride 6 is to completely remove the nitride 6 remaining in a subsequent process by using a high selectivity between the oxide-based insulating film 3 and the nitride 6. The nitride 6 filling the trench 5 is planarized by using a chemical mechanical polishing (CMP) technique or an etch back technique. The reason for the planarization is to stably form a photoresist pattern for via contact etch.
도 4a 및 도 4b는 비아 콘택 형성을 나타내는 도면으로, 비아 콘택용 마스크를 이용하여 표면에 포토 레지스트(4-1) 패터닝한다. 드라이 에치하여 비아 콘택(7)을 형성한다. 상기 비아 콘택을 형성할 때 실리콘 카바이드 계열의 에치 스톱층(2)은 에치하지 않는다. 상기 비아 콘택 식각은 CF 계열의 가스와 O2, CO, Ar, N2 등의 가스를 혼합한 플라즈마를 사용한다.4A and 4B illustrate via contact formation, in which a photoresist 4-1 is patterned on a surface by using a mask for via contact. Dry etching is performed to form the via contact 7. When forming the via contact, the silicon carbide etch stop layer 2 is not etched. The via contact etching uses a plasma mixed with a CF-based gas and gases such as O 2, CO, Ar, and N 2.
도 5a 및 도 5b는 이중 다마신 패턴 형성을 나타내는 도면으로, 등방성 식각의 특성을 지니고 있는 CDE(chemical dry etch) 기술을 사용하여 트렌치(5)를 채우고 있는 질화물(6)을 제거한다. 즉, 질화물(6)과 절연체(3)의 선택비가 높은 NF3나 CF4 또는 SF6 계열의 가스를 사용하는 CDE로 트렌치(5) 측벽에 잔존하는 질화물(6)을 등방성 식각으로 깨끗이 제거한다. 상기 기술은 플라즈마의 형성과 드라이 에치가 같은 공간(챔버)에서 이루어지는 일반적은 드라이 에치와는 달리 플라즈마의 형성과 식각이 진행되는 공간이 달라 에천트인 라디칼이 유도관을 통해 웨이퍼에 전달됨으로써 등방성 식각의 특성을 지니게 된다. CF4, NF3, SF6 같은 F 라디컬을 발생시킬 수 있는 가스와 O2가스의 혼합 가스를 이용하는 것이 일반적이다. 하부 메탈(1)과의 콘택을 형성하기 위해 CF 계열의 가스와 O2, CO, N2, Ar 가스와의 혼합 가스를 이용한 플라즈마하에서 비아 콘택(7) 영역의 에치 스톱층(2)을 식각함으로써 하부 메탈(1)과의 콘택을 형성한다.5A and 5B illustrate the formation of a dual damascene pattern, in which the nitride 6 filling the trench 5 is removed using a chemical dry etch (CDE) technique having isotropic etching. That is, the nitride 6 remaining on the sidewalls of the trench 5 is removed by isotropic etching with CDE using NF 3, CF 4, or SF 6 series gas having a high selectivity between the nitride 6 and the insulator 3. Unlike the general dry etch in which plasma formation and dry etch are performed in the same space (chamber), the technique differs in the space in which plasma formation and etching proceed, so that radicals, which are etchant, are transferred to the wafer through an induction tube, thereby achieving isotropic etching. Have characteristics. It is common to use a mixed gas of a gas capable of generating F radicals such as CF4, NF3, SF6 and O2 gas. By etching the etch stop layer 2 in the via contact 7 region under plasma using a mixture of CF-based gas and O 2, CO, N 2, Ar gas to form a contact with the lower metal 1, A contact with the metal 1 is formed.
본 발명은 CF4, NF3, SF6 처럼 플루오린 라디컬(fluorine radical)을 생산하는 가스를 이용한 등방성 식각은 질화물과 옥사이드의 선택비가 약 100:1까지 이르게 되어 기 형성된 트렌치나 비아 콘택의 옥사이드 프로파일에 변화를 초래하지 않는다. 또한 비아 퍼스트(via first)에서 처럼 포토 레지스트나 ARC로 비아를 매립하지 않기 때문에 비아 보텀부에 잔존하는 유기물로 인한 문제를 근본적으로 해결할 수 있다. 그리고 상, 하부 메탈 라인의 절연체인 옥사이드 중간부에 질화물을 사용하지 않기 때문에 질화물이 지닌 고유전율로 인한 문제를 해결할 수 있다.According to the present invention, the isotropic etching using fluorine radicals such as CF4, NF3, and SF6 results in a selectivity of nitride and oxide up to about 100: 1, thus changing the oxide profile of the formed trench or via contact. Does not cause. In addition, since the via is not filled with photoresist or ARC as in the via first, the problem caused by the organic matter remaining in the via bottom part can be fundamentally solved. And since nitride is not used in the middle portion of the oxide, which is an insulator of the upper and lower metal lines, the problem due to the high dielectric constant of the nitride can be solved.
이상에서 설명한 바와 같이, 본 발명은 질화물(6)과 절연체(3)로 사용된 옥사이드의 높은 선택비를 이용한 CDE 기법을 이용하여 트렌치 퍼스트(trench first)에 해당하는 이중 다마신 패턴 형성 방법으로 트렌치(5)와 비아 콘택(7)을 형성하는 옥사이드의 프로파일을 그대로 유지한다. 특히, 비아 콘택(7) 개구의 프로파일을 변화시키지 않는다. 절연체(3) 사이에 높은 유전율을 지닌 에치 스톱층이 없기 때문에 유전율의 변화가 없다. 형성된 비아 콘택(7)에 포토 레지스트 등의 유기고분자 물질을 채우지 않기 때문에, 비아 콘택(7)의 보텀에 잔존하는 포토 레지스트 등으로 인한 문제가 근본적으로 방지된다.As described above, the present invention is a trench with a double damascene pattern formation method corresponding to trench first using a CDE technique using a high selectivity of oxide used as the nitride (6) and the insulator (3). The profile of the oxide forming the via contact 7 with (5) is maintained as it is. In particular, the profile of the via contact 7 opening is not changed. There is no change in permittivity because there is no etch stop layer with high permittivity between insulators 3. Since the formed via contact 7 is not filled with an organic polymer material such as a photoresist, a problem due to the photoresist or the like remaining at the bottom of the via contact 7 is fundamentally prevented.
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