KR20040012207A - Method for fabricating thin film transistor - Google Patents
Method for fabricating thin film transistor Download PDFInfo
- Publication number
- KR20040012207A KR20040012207A KR1020020045650A KR20020045650A KR20040012207A KR 20040012207 A KR20040012207 A KR 20040012207A KR 1020020045650 A KR1020020045650 A KR 1020020045650A KR 20020045650 A KR20020045650 A KR 20020045650A KR 20040012207 A KR20040012207 A KR 20040012207A
- Authority
- KR
- South Korea
- Prior art keywords
- source
- forming
- thin film
- film transistor
- drain electrode
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000010409 thin film Substances 0.000 title abstract description 16
- 239000011347 resin Substances 0.000 claims abstract description 17
- 229920005989 resin Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 238000002425 crystallisation Methods 0.000 claims abstract description 9
- 230000008025 crystallization Effects 0.000 claims abstract description 9
- 238000000137 annealing Methods 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 6
- 238000005224 laser annealing Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 239000010408 film Substances 0.000 description 34
- 239000002184 metal Substances 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000005499 laser crystallization Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02686—Pulsed laser beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
Abstract
Description
본 발명은 박막 트랜지스터 제조 방법에 관한 것으로, 보다 상세하게는 드레인 고전계에 의한 오프 상태의 높은 누설 전류를 감소시킬 수 있는 박막 트랜지스터 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a thin film transistor capable of reducing high leakage current in an off state caused by a drain high field.
도 1은 종래 기술에 따른 코플라나 타입 박막 트랜지스터의 제조 방법을 설명하기 위한 공정단면도이다.1 is a cross-sectional view illustrating a method of manufacturing a coplanar thin film transistor according to the related art.
종래 기술에 따른 코플라나 타입 박막 트랜지스터의 제조 방법은, 도 1a에 도시된 바와 같이, 유리 등의 절연 기판(100)상에 비정질 실리콘막(미도시)을 형성한 다음, 상기 비정질 실리콘막을 포함한 기판 전체에 대하여 레이저 빔을 조사하여 상기 비정질 실리콘을 결정화시킨다.In the method of manufacturing a coplanar thin film transistor according to the related art, an amorphous silicon film (not shown) is formed on an insulating substrate 100 such as glass, as shown in FIG. 1A, and then a substrate including the amorphous silicon film. The amorphous silicon is crystallized by irradiating a laser beam over the whole.
이어, 도 1b에 도시된 바와 같이, 포토리쏘그라피 공정에 의해 상기 결정화된 실리콘막을 식각하여 아일랜드 타입의 액티브층(102)을 형성한다.Subsequently, as shown in FIG. 1B, the crystallized silicon film is etched by a photolithography process to form an island type active layer 102.
그런 다음, 도 1c에 도시된 바와 같이, 상기 액티브층(102)을 포함한 기판 전면에 제 1금속막(미도시)을 형성한 다음, 포토리소그라피 공정에 의해 상기 제 1금속막을 식각하여 액티브층(102) 상에 게이트 전극(110)을 형성한다.Next, as shown in FIG. 1C, a first metal film (not shown) is formed on the entire surface of the substrate including the active layer 102, and then the first metal film is etched by a photolithography process. The gate electrode 110 is formed on the 102.
이 후, 상기 게이트 전극(110)을 마스크로 하고 상기 기판 전면에 이온 도핑(미도시)을 실시하고 도핑된 이온을 활성화하는 공정을 진행하여 저항성 접촉층(미도시)을 형성한다. 이때, 상기 게이트 전극(110)은 상기 액티브층에 이온이 침투하는 것을 방지하는 이온 스타퍼(Ion-stopper)의 역할을 하게 된다.Thereafter, the gate electrode 110 is used as a mask, and an ohmic doping (not shown) is performed on the entire surface of the substrate, and the doped ions are activated to form an ohmic contact layer (not shown). In this case, the gate electrode 110 serves as an ion stopper to prevent ions from penetrating into the active layer.
이어, 상기 게이트 전극(110)을 포함한 기판 전면에 절연막(112)을 형성하고 나서, 포토리쏘그라피 공정에 의해 상기 절연막(112)을 식각하여 액티브층(102)의 저항성 접촉층을 노출시키는 각각의 개구부(미도시)를 형성한다.Subsequently, after the insulating film 112 is formed on the entire surface of the substrate including the gate electrode 110, the insulating film 112 is etched by a photolithography process to expose the ohmic contact layer of the active layer 102. An opening (not shown) is formed.
그런 다음, 상기 개구부를 포함한 기판 전면에 제 2금속막(미도시)을 형성하고 나서, 포토리쏘그라피 공정에 의해 상기 개구부를 덮는 소오스/드레인전극(116)(114)을 형성한다.Then, a second metal film (not shown) is formed on the entire surface of the substrate including the opening, and then source / drain electrodes 116 and 114 covering the opening are formed by a photolithography process.
상기 다결정 실리콘을 이용한 코플라나 타입 박막 트랜지스터 제작 시, 상기 드레인 전극과 근접한 부분의 액티브 채널에서 발생하는 공핍영역에서 상기 폴리실리콘의 그레인 내부 및 그레인경계(grain boundary)에 존재하는 많은 트랩들로 인해서 전자-전공쌍의 전계방출이 쉽게 일어난다.In the fabrication of a coplanar thin film transistor using the polycrystalline silicon, electrons are generated due to a large number of traps in the grain boundary and grain boundaries of the polysilicon in the depletion region occurring in the active channel adjacent to the drain electrode. -Emission of field pairs occurs easily.
따라서, 매우 큰 누설전류가 흘러서 액정패널의 화질이 저하되며, 장시간 소자를 구동할 경우 실리콘 원자간의 약한 결합이 끊어지거나 수소와 결합하고 있는 실리콘원자의 댕글링본드 결합에서 수소가 분리되어 소자의 전기적 특성이 열화되는 문제가 발생한다.Accordingly, the image quality of the liquid crystal panel is degraded due to a very large leakage current, and when the device is driven for a long time, the weak bond between silicon atoms is broken, or hydrogen is separated from the dangling bond bond of the silicon atom that is bonded with hydrogen, thereby causing the electrical There is a problem of deterioration of characteristics.
또한, 레이저로 빛을 조사하는 공정에서 기판 전체에 대하여 균일한 조사가 어렵다. 레이저가 강하게 조사되는 부분은 결정화되는 깊이가 커지고 약하게 조사되는 부분은 결정화되는 층이 얇아진다.In the process of irradiating light with a laser, it is difficult to uniformly irradiate the entire substrate. The portion to which the laser is strongly irradiated increases the depth of crystallization, and the portion to which the laser is irradiated becomes thinner.
결과적으로 결정화가 많이되는 부분에 형성되는 스위칭소자와 적게되는 부분에 형성되는 스위칭소자의 특성이 달라 표시되는 화상에 얼룩이 발생되기도 한다.As a result, the characteristics of the switching element formed in the portion where crystallization is large and the switching element formed in the portion where the crystallization is large may be different, resulting in unevenness in the displayed image.
따라서, 이러한 누설 전류를 감소시키기 위해 제안된 엘디디(LDD:Lightly Dopde Drain), 옵셋(offset) 등의 구조 등이 제안되지만, 상기 구조들을 공정 및 마스크 수가 추가되며, 이에 따라 폴리 실리콘 박막 트랜지스터 제조 시 제조 비용 상승되는 문제점이 있었다.Therefore, the proposed structures such as LDD (Lightly Dopde Drain), offset (offset), etc. have been proposed to reduce the leakage current. There was a problem that the manufacturing cost rises.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 코플라나 타입 박막 트랜지스터 구조가 가지는 드레인 고전계에 의한 오프 상태의 높은 누설 전류를 감소시킬 수 있는 박막 트랜지스터 제조 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a thin film transistor manufacturing method capable of reducing high leakage current in an off state due to a drain high field of a coplanar type thin film transistor structure. have.
도 1은 종래 기술에 따른 코플라나 타입 박막 트랜지스터의 제조 방법을 설명하기 위한 공정단면도.1 is a process cross-sectional view for explaining a method for manufacturing a coplanar type thin film transistor according to the prior art.
도 2a 내지 도 2d는 본 발명에 따른 스태거드 타입 박막 트랜지스터의 제조 방법을 설명하기 위한 공정단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a staggered thin film transistor according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
200. 절연 기판 202.204. 소오스/드레인 전극200. Insulated substrate 202.204. Source / drain electrodes
206. 오믹곤택층 210, 211. 레진막 패턴206. Ohmic hard contact layer 210, 211. Resin film pattern
212. 다결정 실리콘막 214. 게이트 절연막212.Polycrystalline silicon film 214. Gate insulating film
216. 게이트 전극 Dv. 수직 옵셋영역216. Gate electrode Dv. Vertical offset area
Dh. 수평 옵셋영역Dh. Horizontal offset area
상기 목적을 달성하기 위한 본 발명의 박막 트랜지스터 제조 방법은, 절연 기판 상에 소오스/드레인 전극 및 상기 소오스/드레인 전극 상에 오믹콘택층을 형성하는 단계와, 오믹콘택층을 포함한 소오스/드레인 전극 사이의 공간에 잔류되는 레진막 패턴을 형성하는 단계와, 레진막 패턴에 어닐 공정을 실시하여 레진막 패턴을 볼록한 곡선 형태로 형성하는 단계와, 결과의 기판 전면에 다결정 실리콘막을 형성하고 결정화하는 단계와, 결정화된 실리콘막 상에 게이트 절연막을 형성하는 단계와, 게이트 절연막 상에 게이트 전극을 형성하는 단계를 포함한 것을 특징으로 한다.A thin film transistor manufacturing method of the present invention for achieving the above object, the step of forming a source / drain electrode and an ohmic contact layer on the source / drain electrode on an insulating substrate, between the source / drain electrode including an ohmic contact layer Forming a resin film pattern remaining in the space of the resin, performing an annealing process on the resin film pattern, forming the resin film pattern in a convex curve shape, and forming and crystallizing a polycrystalline silicon film on the entire surface of the resulting substrate; And forming a gate insulating film on the crystallized silicon film, and forming a gate electrode on the gate insulating film.
상기 어닐 공정은 적외선, 레이저 및 전자파 중 어느 하나를 이용하는 것이 바람직하다.The annealing process preferably uses any one of infrared rays, lasers, and electromagnetic waves.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 스태거드 타입 박막 트랜지스터의 제조 방법을 설명하기 위한 공정단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a staggered thin film transistor according to the present invention.
본 발명에 따른 스태거드 타입 박막 트랜지스터의 제조 방법은, 도 2a에 도시된 바와 같이, 유리 등의 절연 기판(200) 상에 제 1금속막(미도시) 및 불순물이도핑된 비정질 실리콘막(n+/p+ a-Si)(미도시)을 차례로 형성한 후, 포토리쏘그라피 공정에 의해 상기 막들을 식각하여 소오스/드레인 전극(204)(202) 및 소오스/드레인 전극(204)(202) 상부에 오믹콘택층(206)을 각각 형성한다.In the method of manufacturing a staggered thin film transistor according to the present invention, as shown in FIG. 2A, an amorphous silicon film (not shown) and an impurity doped with a first metal film (not shown) are formed on an insulating substrate 200 such as glass. n + / p + a-Si) (not shown) are formed sequentially, and then the films are etched by a photolithography process so that the source / drain electrodes 204 and 202 and the source / drain electrodes 204 and 202 are topped. The ohmic contact layer 206 is formed in each.
이어, 도 2b에 도시된 바와 같이, 상기 결과의 기판 전면에 레진막(미도시)을 도포하고 나서, 상기 소오스/드레인 전극 사이의 공간을 잔류되도록 상기 레진막을 제거하여 레진막 패턴(210)을 형성한다.Subsequently, as shown in FIG. 2B, a resin film (not shown) is applied to the entire surface of the resultant substrate, and the resin film is removed by removing the resin film so that the space between the source / drain electrodes remains. Form.
그런 다음, 상기 레진막 패턴(210)에 어닐 공정을 실시하면, 레진막 패턴은 유동성을 가지고 퍼져 원만한 곡선형태를 가진다.(도면부호 211참조) 이때, 상기 어닐 공정은 적외선, 레이저 및 전자파 중 어느 하나를 이용한다.Then, when the annealing process is performed on the resin film pattern 210, the resin film pattern has fluidity and spreads to have a smooth curved shape (see reference numeral 211). In this case, the annealing process is performed by any one of infrared rays, lasers, and electromagnetic waves. Use one.
그런 다음, 도 2c에 도시된 바와 같이, 상기 곡선 형태의 레진막 패턴(211)을 포함한 기판 전면에 다결정 실리콘막(212)을 형성하고 나서, 상기 다결정 실리콘막(212)을 엑시머 레이저 어닐링(excimer laser annealing), SPC(Solid Phase Crystallization) 또는 MIC(Metal Induced Crystallization) 등에 의해 결정화시킨다.Then, as shown in FIG. 2C, after forming the polycrystalline silicon film 212 on the entire surface of the substrate including the curved resin film pattern 211, the polycrystalline silicon film 212 is excimer laser annealed (excimer). Crystallization is performed by laser annealing (SPC), solid phase crystallization (SPC) or metal induced crystallization (MIC).
이 후, 도 2d에 도시된 바와 같이, 상기 결정화된 실리콘막(212) 상에 게이트 절연막(214)을 형성한다.Thereafter, as shown in FIG. 2D, a gate insulating film 214 is formed on the crystallized silicon film 212.
그런 다음, 상기 게이트 절연막(214) 상에 제 2금속막(미도시)을 형성한 후, 포토리쏘그라피 공정에 의해 상기 제 2금속막을 식각하여 게이트 전극(216)을 형성한다. 도면에서, Dh는 수평옵셋영역을, Dv는 수직 옵셋영역을 도시한 것이다.Then, after forming a second metal film (not shown) on the gate insulating film 214, the second metal film is etched by a photolithography process to form a gate electrode 216. In the figure, Dh shows a horizontal offset area and Dv shows a vertical offset area.
본 발명은, 수직 옵셋영역(Dv) 및 수평 옵셋영역(Dh)을 조정함으로써, 오프상태의 누설 전류 및 이온 전류를 조절할 수 있고, 옵셋 영역을 통한 드레인 전계의 감소로부터 전계에 의한 전자-정공 주입 전류를 감소시킬 수 있다.In the present invention, by adjusting the vertical offset region (Dv) and the horizontal offset region (Dh), it is possible to adjust the leakage current and the ion current in the off state, and electron-hole injection by the electric field from the reduction of the drain electric field through the offset region Can reduce the current.
본 발명의 채널은 볼록한 곡선형태로서, 레이저, 열 또는 금속 유도 등의 결정화 공정에서 결정립 경계를 크게 할 수 있다.The channel of the present invention has a convex curved shape, which can increase grain boundaries in crystallization processes such as laser, heat, or metal induction.
본 발명에 따른 곡선형의 전도 채널을 가지는 스테거드형 박막 트랜지스터는 오프 시 곡선 및 자동 옵셋에 의해 드레인 전극의 전계를 낮출 수 있고 저누설 전류를 실현할 수 있다.The staggered thin film transistor having a curved conduction channel according to the present invention can lower the electric field of the drain electrode and realize a low leakage current by a curve and an automatic offset when off.
특히, 본 발명은 소오스/드레인 전극 사이의 채널이 볼록한 곡선형을 가짐으로써, 레이저 결정화 및 옵셋 형성에 유리하며, 곡선에 의한 옵셋 외에 불순물이 도핑되지 않은 실리콘층이 소오스/드레인 전극 상부 및 채널 사이에 존재하여 낮은 누설 전류를 실현할 수 있다.In particular, the present invention has a convex curved channel between the source and drain electrodes, which is advantageous for laser crystallization and offset formation, and the silicon layer which is not doped with impurities other than the offset by the curve is formed between the source and drain electrodes and the channel. It can exist in to realize low leakage current.
이상에서와 같이, 본 발명의 채널을 볼록한 곡선 형태로 형성함으로써, 레이저 결정화 및 옵셋 형성에 유리하며, 곡선에 의한 옵셋 외에 불순물이 도핑되지 않은 실리콘층이 소오스/드레인 전극 상부 및 채널 사이에 존재하여 낮은 누설 전류를 실현할 수 있다.As described above, by forming the channel of the present invention in the form of convex curve, it is advantageous for laser crystallization and offset formation, and the silicon layer which is not doped with impurities other than the offset by the curve exists between the source / drain electrode and the channel. Low leakage current can be realized.
본 발명에 따른 곡선형의 전도 채널을 가지는 스테거드형 박막 트랜지스터는 오프 시 곡선 및 자동 옵셋에 의해 드레인 전극의 전계를 낮출 수 있고 저누설 전류를 실현할 수 있다.The staggered thin film transistor having a curved conduction channel according to the present invention can lower the electric field of the drain electrode and realize a low leakage current by a curve and an automatic offset when off.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020045650A KR100867500B1 (en) | 2002-08-01 | 2002-08-01 | Method for fabricating thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020045650A KR100867500B1 (en) | 2002-08-01 | 2002-08-01 | Method for fabricating thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040012207A true KR20040012207A (en) | 2004-02-11 |
| KR100867500B1 KR100867500B1 (en) | 2008-11-06 |
Family
ID=37320214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020045650A KR100867500B1 (en) | 2002-08-01 | 2002-08-01 | Method for fabricating thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100867500B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8138503B2 (en) | 2008-10-08 | 2012-03-20 | Samsung Electronics Co., Ltd. | Display substrate having a protruding barrier pattern |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100425858B1 (en) * | 1998-07-30 | 2004-08-09 | 엘지.필립스 엘시디 주식회사 | Thin film transistor and its manufacturing method |
| KR100487256B1 (en) * | 2002-10-31 | 2005-05-03 | 엘지.필립스 엘시디 주식회사 | method for thin film transistor using poly silicon |
-
2002
- 2002-08-01 KR KR1020020045650A patent/KR100867500B1/en active IP Right Grant
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8138503B2 (en) | 2008-10-08 | 2012-03-20 | Samsung Electronics Co., Ltd. | Display substrate having a protruding barrier pattern |
| US8241934B2 (en) | 2008-10-08 | 2012-08-14 | Samsung Electronics Co., Ltd. | Display substrate and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100867500B1 (en) | 2008-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6001714A (en) | Method and apparatus for manufacturing polysilicon thin film transistor | |
| KR100280171B1 (en) | Non-single-crystal semiconductor device (thin film transistor), liquid crystal display device using the same and manufacturing method thereof | |
| CN106847703B (en) | Manufacturing method of low-temperature polycrystalline silicon thin film transistor and display device | |
| EP0702852A1 (en) | Manufacture of electronic devices comprising thin-film transistors | |
| US9627543B2 (en) | Thin film transistor and method for manufacturing the same, array substrate including the thin film transistor and display device including the array substrate | |
| KR100676330B1 (en) | Semiconductor device, method of manufacturing semiconductor device and method of manufacturing thin film transistor | |
| KR100282233B1 (en) | Thin film transistor and its manufacturing method | |
| KR20050081227A (en) | Thin film transistor having ldd structure | |
| JP2805590B2 (en) | Method for manufacturing semiconductor device | |
| US5923967A (en) | Method for producing a thin film semiconductor device | |
| JP2010098321A (en) | Semiconductor device | |
| US20020000614A1 (en) | Coplanar gate-source-drain Poly-TFT and method for fabricating the same | |
| KR100867500B1 (en) | Method for fabricating thin film transistor | |
| US7026201B2 (en) | Method for forming polycrystalline silicon thin film transistor | |
| KR100482462B1 (en) | Manufacturing method of polysilicon thin film transistor of liquid crystal display device | |
| US7141823B2 (en) | Thin film transistor semiconductor device | |
| JP3141979B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH11204800A (en) | Thin film transistor, its manufacture and impurity implanting equipment | |
| KR100274887B1 (en) | Thin film transistor and method for manufacturing the same | |
| KR100793278B1 (en) | Method for manufacturing polycrystalline silicon - thin film transistor | |
| JP4417327B2 (en) | Method for manufacturing semiconductor device | |
| JP3393834B2 (en) | Method for manufacturing semiconductor device | |
| JP3244387B2 (en) | Thin film semiconductor device | |
| JP3360057B2 (en) | Semiconductor device | |
| JP3293568B2 (en) | Thin film transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20120906 Year of fee payment: 5 |
|
| FPAY | Annual fee payment |
Payment date: 20130911 Year of fee payment: 6 |
|
| FPAY | Annual fee payment |
Payment date: 20140919 Year of fee payment: 7 |
|
| FPAY | Annual fee payment |
Payment date: 20150918 Year of fee payment: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20160920 Year of fee payment: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20170921 Year of fee payment: 10 |
|
| FPAY | Annual fee payment |
Payment date: 20181001 Year of fee payment: 11 |