KR20040011158A - A substrate for LCD and method for fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate of a liquid crystal display and a method of fabricating the same are provided to reduce an RC delay and produce a liquid crystal display with high picture quality. CONSTITUTION: An array substrate of a liquid crystal display includes a transparent insulating substrate(100), a gate line(104) and a gate electrode(102) formed on the substrate, and a gate insulating layer(106) that is formed on the gate line and gate electrode and has a plurality of pores. The array substrate further includes an active layer(108) and an ohmic contact layer(110) having an island shape, formed on the gate insulating layer, source and drain electrodes(112,114) coming into contact with the ohmic contact layer, and a data line(116) that is extended from the source electrode and intersects the gate line. The array substrate also has an organic passivation layer(118) that is formed on the overall surface of the substrate and exposes a portion of the drain electrode, and a transparent pixel electrode(124) formed on the organic passivation layer and connected with the exposed portion of the drain electrode.

Description

Array substrate for liquid crystal display device and manufacturing method thereof {A substrate for LCD and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device (LCD), and more particularly, to an array substrate for a liquid crystal display device and a method of manufacturing the same for improving operational characteristics of the liquid crystal display device by reducing RC delay.

1 is a view schematically showing a general liquid crystal display device.

As shown, a general color liquid crystal display device includes a color filter 34 including a sub-matrix filter 30 and a black matrix 31 formed between the color filters 30 and an upper portion of the color filter 34. The upper substrate 40 having the common electrode 36 deposited thereon, the pixel region P and the pixel electrode 32 formed on the pixel region, the gate electrode 12, the active layer 18, and the source electrode 22. ) And a lower substrate 10 having a switching element T including a drain electrode 24, a gate wiring 14, and a data wiring 26, and the upper substrate 40 and the lower substrate 10. The liquid crystal 50 is filled in between.

In this case, the pixel area P is an area defined by the gate wiring 12 and the data wiring 26 intersecting. A transparent pixel electrode 32 is formed on the pixel area P as described above. .

The pixel electrode 32 uses a transparent conductive metal having a relatively high light transmittance, such as indium-tin-oxide (ITO).

The driving of the liquid crystal panel having the configuration as described above is due to the electro-optical effect of the liquid crystal.

In detail, the liquid crystal layer 50 is a dielectric anisotropic material having spontaneous polarization characteristics, and when a voltage is applied, bipolar is formed by spontaneous polarization to arrange the molecules according to the direction of application of the electric field. This has changing characteristics.

Therefore, the optical characteristic is changed according to this arrangement state, thereby causing electrical light modulation.

By the light modulation phenomenon of the liquid crystal, an image is realized by a method of blocking or passing light.

Intensive research for large area and high image quality of the liquid crystal display device having the above-described configuration has been conducted. For this purpose, many studies have been conducted to solve the RC delay of the wiring.

The RC delay problem of the wiring is caused by a large resistance of the wiring itself or a parasitic capacitance generated in the structure where the wiring overlaps the wiring.

A description with reference to the cross-sectional view of FIG. 2 is as follows.

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1.

As shown in the drawing, in general, an array substrate for a liquid crystal display device, a gate electrode 12 and a gate wiring 14 are formed on a substrate 10.

The gate insulating layer 16 is formed on the gate electrode 12 and the gate wiring 14, and is formed of one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). .

The active layer 18 and the ohmic contact layer 20 are stacked on the gate insulating layer 16 on the gate electrode 12, and the source electrode 22 and the drain electrode 24 spaced apart from each other on the ohmic contact layer 20. ) And at the same time, a data line 26 connected to the source electrode 22 intersects with the gate line 14.

A silicon insulating layer 28 exposing a part of the drain electrode 24 is formed on the source and drain electrodes 22 and 24 and the data line 26.

The silicon insulating layer 30 is formed by depositing silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ) as described above, which is a protective film having an interfacial property between the active layer 18 and the silicon insulating layer 28. 30) because it is better than the configuration.

If the interface characteristics with the active layer 18 are not good, a trap level for trapping electrons is generated, which causes a decrease in the operating characteristics of the thin film transistor.

Therefore, in some cases, the silicon insulating film 28 is formed on the active layer 18.

A passivation layer 30 is formed on the silicon insulating layer 28, and a transparent pixel electrode 32 is formed on the passivation layer 30 to contact the exposed drain electrode 24.

In this case, the passivation layer 30 is formed of one selected from the group of organic insulating materials including benzocyclobutene (BCB) and acryl resin.

In the above-described configuration, the portion A where the gate line 14 and the data line 26 intersect, and the portion B where the gate electrode 12 overlaps the source and drain electrodes 22 and 24 are silicon. Each part is separated by the gate insulating film 28 which is an insulating film, and the portion C where the drain electrode 24 and the transparent pixel electrode 32 overlap is separated by the silicon etch film 28 and the protective film 30. do.

In such a configuration, the signal applied to the liquid crystal panel generates an RC delay due to the parasitic capacitance generated at the intersection between the sheet resistance of each wiring and each wiring or at the portion where each electrode overlaps.

RC can be expressed as

Where R _S is: sheet resistance of the wiring conductor

ε: dielectric constant of intermediate insulator between wirings

L ² : length of wiring conductor

d: thickness of intermediate insulator between wirings

In the above formula, when the same wiring conductor (that is, the sheet resistance is the same) and the thickness d of the insulator and the length L of the wiring are the same, RC depends on the dielectric constant value? Of the insulator.

At this time, if the silicon insulating film is used as the silicon oxide, the dielectric constant has a value of about 3.8 to 4.2.

This is a barrier to the realization of high image quality in flat panel display devices.

The present invention has been proposed for the purpose of solving the above-described problems, and in forming the inter-wire or inter-electrode insulating film, a silicon insulating film having fine pores is formed.

Such a structure can lower the dielectric constant of the insulating film, thereby reducing the RC delay, thereby making it possible to manufacture a large-area high-definition liquid crystal display device.

1 is a view schematically showing a general liquid crystal display device,

FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1;

3A to 3D are cross-sectional views illustrating a process sequence of the present invention cut along II-II ′ of FIG. 1.

<Brief description of the main parts of the drawing>

100 substrate 102 gate electrode

104: gate wiring 106: gate insulating film

108: active layer 110: ohmic contact layer

112 source electrode 114 drain electrode

116: data wiring 118: first protective film

120: second protective film 124: pixel electrode

An array substrate for a liquid crystal display device according to the present invention for achieving the above object is a transparent insulating substrate; A gate wiring formed on the substrate and a gate electrode extending therefrom; A gate insulating film formed over the gate wiring and the gate wiring, the gate insulating film being a silicon insulating film including a plurality of fine voids; An island-like active layer and an ohmic contact layer formed on the gate insulating film on the gate electrode; Source and drain electrodes in contact with the ohmic contact layer, and data lines extending from the source electrodes and crossing the gate lines; An organic passivation film formed on an entire surface of the substrate on which the source and drain electrodes and the data wiring are formed, and exposing a part of the drain electrode; And a transparent pixel electrode disposed on the organic passivation layer and in contact with the exposed drain electrode.

A silicon insulating film including a plurality of voids between the source and drain electrodes, the data line, and the passivation layer may be further configured.

The fine pores of the silicon insulating film is characterized in that the water or alcohol in the process of curing after coating a liquid reactant made by mixing a starting material containing silicon, a surfactant and a reactive catalyst on a substrate and characterized in that the flying.

The dielectric constant value of the silicon insulating layer including the micro voids may be 1.2 to 2.5.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: forming a gate wiring and a gate electrode extended thereto; Forming a gate insulating film which is a silicon insulating film including a plurality of fine pores on the gate wiring and the gate wiring; Forming an island-shaped active layer and an ohmic contact layer on the gate insulating layer on the gate electrode; Forming source and drain electrodes in contact with the ohmic contact layer and data lines extending from the source electrodes and intersecting the gate lines; Forming an organic passivation layer exposing a portion of the drain electrode on an entire surface of the substrate on which the source and drain electrodes and the data wiring are formed; Forming a transparent pixel electrode on the organic passivation layer and in contact with the exposed drain electrode.

The method may further include forming a silicon insulating layer including a plurality of voids between the source and drain electrodes, the data line, and the passivation layer.

The micro voids of the silicon insulating layer are made by blowing water or alcohol during the curing process after coating a liquid reactant made by mixing a metal alkoxide and other reactive catalyst on silicon on a substrate.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

The present invention is characterized by forming a silicon insulating film including a plurality of minute pores between wirings or between electrodes.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to an embodiment of the present invention will be described with reference to FIGS. 3A to 3D. .)

3A to 3D are cross sectional views taken along the line II-II ′ of FIG. 1 and shown in the process sequence of the present invention.

As shown in FIG. 3A, the substrate 100 includes aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), chromium (Cr), titanium (Ti), tantalum (Ta), and the like. A selected one of the conductive metal groups is deposited and patterned to form the gate electrode 102 and the gate wiring 104.

Next, a gate insulating layer 106 is formed on the entire surface of the substrate 100 on which the gate electrodes and the gate wirings 102 and 104 and the gate wiring 104 are formed, which is a silicon insulating film including a plurality of minute porous pores. do.

Various methods may be used to form the silicon insulating layer 106 including the micro voids, and among them, a sol-gel method may be mentioned.

The sol-gel method is one of the methods of forming a thin film. The starting material is formed in a colloidal suspended state, that is, a sol state, and is converted into a liquid network through the gelation process of the sol. Say the process of making.

That is, starting materials containing silica, for example, TEOS (Tetraethoxysilane: Si (OCH2CH3) 4) or TMOS (Tetramethoxysilane: Si (OCH3) 4 Tetramethoxysilane), a colloidal silica, and a surfactant and a solvent having both hydrophilic and hydrophobic groups (ethanol , Acetonitrile and the like) and a catalyst (hydrochloric acid (HCL)) are mixed and prepared in a solution state through a predetermined process.

In this case, briefly describing the reaction, the silicon is bonded to the hydrophilic group of the surfactant, and the hydrophobic group is arranged in the direction of lowering its energy to exist in the transparent liquid phase. After coating the solution in such a state on the substrate, the silicon insulating film 106 including a plurality of pores is formed while the hydrophobic groups and others of the surfactant are removed by pyrolysis during baking at about 200 ° C. or less. do.

The pore size is usually in nano units.

Of course, a method of forming a gap in the silicon insulating layer 106 may be variously experimented.

As described above, when a large number of voids are formed in the silicon insulating film, the dielectric constant value is remarkably decreased. That is, since the dielectric constant value of the air filling the voids is about 1, a low dielectric constant value of at least 1.1 to 2.5 can be obtained.

Next, as shown in FIG. 3B, pure amorphous silicon (a-Si: H) and impurity amorphous silicon are sequentially deposited and patterned on the gate insulating film 106 to form a gate insulating film on the gate electrode 102. The active layer 108 and the ohmic contact layer 110 are formed on the 106.

Next, the conductive metal as described above is deposited and patterned on the entire surface of the substrate 100 on which the ohmic contact layer 110 is formed, and the source and drain electrodes 112 and 114 contacting the ohmic contact layer 110, The data line 116 is formed to be connected to the source electrode 112 and cross the gate line 104.

As shown in FIG. 3C, the silicon insulating layer 118 including a plurality of voids using the sol-gel method described above on the entire surface of the substrate 100 on which the source and drain electrodes 112 and 114 and the data line 116 are formed. To form.

Next, the protective layer 120 is formed by depositing one selected from the group of organic insulating materials including benzocyclobutene (BCB) and acrylic resin (resin) on the silicon insulating layer 118.

Subsequently, the passivation layer 120 and the silicon insulating layer 118 under the pattern are patterned to form a drain contact hole 122 exposing a part of the drain electrode 114.

As shown in FIG. 3D, a transparent conductive metal including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited and patterned on the entire surface of the substrate 100 on which the passivation layer 120 is formed. The transparent pixel electrode 124 in contact with the exposed drain electrode is formed.

In the above-described configuration, the gate wiring and the data wiring, which are formed to cross each other, the gate electrode, the source and the drain electrode, and the drain electrode and the pixel electrode, which are partially overlapped in a planar manner, are insulated from each other through an insulating film.

As described above, since the insulating layer includes fine pores, the dielectric constant has a value of 1.1 to 2.5. Therefore, the RC delay phenomenon seen in the liquid crystal panel can be reduced by 30% to 60% than when using the conventional silicon insulating film.

Therefore, the present invention reduces the RC delay phenomenon to a considerable level or less by using an insulating film including a plurality of voids as a material for insulating the wiring and the electrode.

As a result, there is an effect that can produce a large-area liquid crystal panel to implement a high quality.

Claims (8)

A transparent insulating substrate; A gate wiring formed on the substrate and a gate electrode extending therefrom; A gate insulating film formed over the gate wiring and the gate wiring, the gate insulating film being a silicon insulating film including a plurality of fine voids; An island-like active layer and an ohmic contact layer formed on the gate insulating film on the gate electrode; Source and drain electrodes in contact with the ohmic contact layer, and data lines extending from the source electrodes and crossing the gate lines; An organic passivation film formed on an entire surface of the substrate on which the source and drain electrodes and the data wiring are formed, and exposing a part of the drain electrode; A transparent pixel electrode on the organic passivation layer and in contact with the exposed drain electrode Array substrate for a liquid crystal display device comprising a. The method of claim 1, And a silicon insulating film including a plurality of voids between the source and drain electrodes, the data line, and the passivation layer. The method of claim 1, The micro-pore of the silicon insulating layer is an array for a liquid crystal display device made by blowing water or alcohol during the curing process after coating a reactant in a liquid state made by mixing a starting material including silicon, a surfactant, and a reactive catalyst on a substrate. Board. The method of claim 1, And a dielectric constant value of the silicon insulating layer including the fine pores is 1.2 to 2.5. Forming a gate wiring and a gate electrode extending thereon on the substrate; Forming a gate insulating film which is a silicon insulating film including a plurality of fine pores on the gate wiring and the gate wiring; Forming an island-shaped active layer and an ohmic contact layer on the gate insulating layer on the gate electrode; Forming source and drain electrodes in contact with the ohmic contact layer and data lines extending from the source electrodes and intersecting the gate lines; Forming an organic passivation layer exposing a portion of the drain electrode on an entire surface of the substrate on which the source and drain electrodes and the data wiring are formed; Forming a transparent pixel electrode on the organic passivation layer and in contact with the exposed drain electrode; Array substrate manufacturing method for a liquid crystal display comprising a. The method of claim 5, wherein And forming a silicon insulating film comprising a plurality of voids between the source and drain electrodes, the data line, and the passivation layer. The method of claim 5, wherein The micro-pore of the silicon insulating film is produced by coating a liquid reactant made by mixing a metal alkoxide and other reactive catalyst on silicon on a substrate, and then making water or alcohol in the process of curing. Way. The method of claim 5, wherein The dielectric constant value of the silicon insulating film including the micro-pores is 1.1 to 2.5 array substrate manufacturing method for a liquid crystal display device.