KR20040008655A - Method of manufacturing capacitor for semiconductor device - Google Patents

Method of manufacturing capacitor for semiconductor device Download PDF

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Publication number
KR20040008655A
KR20040008655A KR1020020042324A KR20020042324A KR20040008655A KR 20040008655 A KR20040008655 A KR 20040008655A KR 1020020042324 A KR1020020042324 A KR 1020020042324A KR 20020042324 A KR20020042324 A KR 20020042324A KR 20040008655 A KR20040008655 A KR 20040008655A
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South Korea
Prior art keywords
lower electrode
film
capacitor
layer
hole
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KR1020020042324A
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Korean (ko)
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김준기
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주식회사 하이닉스반도체
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Priority to KR1020020042324A priority Critical patent/KR20040008655A/en
Publication of KR20040008655A publication Critical patent/KR20040008655A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to prevent focusing of electric field to a lower electrode and short between capacitors. CONSTITUTION: A capacitor oxide layer(21) is formed on a semiconductor substrate(20). A capacitor hole is formed by selectively etching the capacitor oxide layer. A lower electrode(22) is formed by depositing a polysilicon layer on the hole and the capacitor oxide layer. A gap-fill substance layer is filled in the capacitor hole. By blanket etching of the gap-fill substance layer and the lower electrode to expose the capacitor oxide layer, the lower electrode is isolated. A nitride layer(24) is formed at the top edges of the isolated lower electrode by nitridation processing. After removing the gap-fill substance layer, an HSG(Hemispherical Grain) layer(25) is then formed on the lower electrode.

Description

반도체 소자의 캐패시터 제조방법{METHOD OF MANUFACTURING CAPACITOR FOR SEMICONDUCTOR DEVICE}METHODS OF MANUFACTURING CAPACITOR FOR SEMICONDUCTOR DEVICE

본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 HSG막을 적용한 반도체 소자의 캐패시터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly to a method for manufacturing a capacitor of a semiconductor device to which an HSG film is applied.

반도체 소자의 고집적화에 따라 캐패시터의 하부전극인 스토리지 노드전극의형상을 대부분 실린더형으로 형성하고 있다. 또한, 좁은 셀면적 내에서 충분한 캐패시터 용량을 확보하기 위하여, 하부전극 표면에 HSG막을 성장시켜 표면적을 증가시키는 방법 등이 이루어지고 있다.As the semiconductor devices are highly integrated, most of the storage node electrodes, which are the lower electrodes of the capacitors, are formed in a cylindrical shape. In addition, in order to secure sufficient capacitor capacity within a narrow cell area, a method of increasing the surface area by growing an HSG film on the lower electrode surface has been made.

도 1은 HSG막을 적용한 종래의 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a method of manufacturing a capacitor of a conventional semiconductor device to which an HSG film is applied.

도 1을 참조하면, 도시되지는 않았지만, 트랜지스터, 플러그 및 층간절연막형성 등의 소정의 공정이 완료된 반도체 기판(10) 상에 캐패시터 산화막(11)을 형성하고, 기판(10)의 일부가 노출되도록 산화막(11)을 식각하여 실린더 형상의 캐패시터용 홀을 형성한다. 그 다음, 상기 홀 표면 및 산화막(11) 표면 상에 폴리실리콘막으로 하부전극(12)을 형성하고, 하부전극(12)이 형성된 홀에 매립되도록 기판 전면 상에 매립용 물질막(미도시)을 형성한다. 여기서, 매립용 물질막은 포토레지스트막이나 SOG막과 같은 플로우(flow) 특성을 갖는 막으로 형성한다.Referring to FIG. 1, although not shown, a capacitor oxide film 11 is formed on a semiconductor substrate 10 on which a predetermined process such as forming a transistor, a plug, and an interlayer insulating film is completed, and a portion of the substrate 10 is exposed. The oxide film 11 is etched to form a cylindrical capacitor hole. Subsequently, a lower electrode 12 is formed of a polysilicon film on the hole surface and the oxide film 11, and a buried material film (not shown) is formed on the entire surface of the substrate so as to be embedded in a hole in which the lower electrode 12 is formed. To form. Here, the embedding material film is formed of a film having flow characteristics such as a photoresist film or an SOG film.

그 후, 에치백 공정으로 매립용 물질막 및 하부전극(12)을 산화막(11)의 표면이 노출되도록 전면식각하여 하부전극(12)을 서로 분리시킨다. 그 다음, 공지된 방법으로 매립용 물질막을 제거하고, 하부전극(12)의 표면적 증대를 위하여 하부전극(12) 표면에 HSG막(13)을 형성한다.Subsequently, the buried material film and the lower electrode 12 are etched to the entire surface of the oxide film 11 by an etch back process to separate the lower electrodes 12 from each other. Then, the embedding material film is removed by a known method, and the HSG film 13 is formed on the surface of the lower electrode 12 to increase the surface area of the lower electrode 12.

그러나, 하부전극(12) 분리를 위한 에치백 공정에 의해 하부전극(12)의 최상부 형상이 뾰족하게 되고, 이러한 하부전극(12) 형상에 의해 디램(DRAM) 셀의 동작시 전계집중현상이 발생되어 심한 경우 캐패시터 유전막을 파괴하는 원인으로 작용하게 된다. 또한, 하부전극(12)의 표면적 증대를 위한 HSG막(13)의 형성시 하부전극(12) 상부의 첨점 부분에서 HSG막(13)이 인접 HSG막과 서로 접하게 되어 캐패시터 사이의 단락(short)을 유발함으로써 소자의 전기적 특성을 저하시킨다.However, an uppermost shape of the lower electrode 12 is sharpened by an etch back process for separating the lower electrode 12, and a field concentration phenomenon occurs when the DRAM cell is operated by the lower electrode 12 shape. In severe cases, it acts as a cause of destruction of the capacitor dielectric film. In addition, when the HSG film 13 is formed to increase the surface area of the lower electrode 12, the HSG film 13 is in contact with the adjacent HSG film at the peak portion of the lower electrode 12 so that a short circuit occurs between the capacitors. It causes the deterioration of the electrical characteristics of the device.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 하부전극 최상부의 전계집중 현상을 방지함과 동시에 HSG막 형성에 따른 캐패시터 사이의 단락을 방지할 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, a method of manufacturing a capacitor of a semiconductor device capable of preventing the field concentration phenomenon at the top of the lower electrode and at the same time can prevent a short circuit between the capacitor due to the formation of the HSG film. The purpose is to provide.

도 1은 종래의 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a capacitor manufacturing method of a conventional semiconductor device.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing

20 : 반도체 기판 21 : 캐패시터 산화막20 semiconductor substrate 21 capacitor oxide film

22 : 하부전극 23 : 매립용 물질막22: lower electrode 23: embedding material film

24 : 질화막 25 : HSG막24 nitride film 25 HSG film

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 소정의 공정이 완료된 반도체 기판 상에 캐패시터 산화막을 형성하는 단계; 산화막을 식각하여 캐패시터용 홀을 형성하는 단계; 홀 표면 및 산화막 표면 상에 폴리실리콘막으로 하부전극을 형성하는 단계; 하부전극이 형성된 홀에 매립되도록 기판 전면 상에 매립용 물질막을 형성하는 단계; 매립용 물질막 및 하부전극을 산화막의 표면이 노출되도록 전면식각하여 하부전극을 분리하는 단계; 기판을 질화처리하여 하부전극의 최상부에 질화막을 형성하는 단계; 매립용 물질막을 제거하는 단계; 및 하부전극 표면에 HSG막을 형성하는 단계를 포함하는 반도체 소자의 캐패시터 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, the above object of the present invention comprises the steps of forming a capacitor oxide film on a semiconductor substrate is completed a predetermined process; Etching the oxide film to form a hole for a capacitor; Forming a lower electrode on the hole surface and the oxide film surface with a polysilicon film; Forming a buried material film on the entire surface of the substrate to be buried in a hole in which the lower electrode is formed; Separating the lower electrode by etching the buried material layer and the lower electrode to expose the surface of the oxide layer; Nitriding the substrate to form a nitride film on top of the lower electrode; Removing the embedding material film; And forming a HSG film on the lower electrode surface.

바람직하게, 질화처리는 질소를 포함한 플라즈마 분위기에서 수행하거나,500 내지 800℃의 온도에서 N2, N2O 나 NH3와 같은 질소함유개스 분위기에서 수행한다.Preferably, the nitriding treatment is carried out in a plasma atmosphere containing nitrogen, or in a nitrogen-containing gas atmosphere such as N 2 , N 2 O or NH 3 at a temperature of 500 to 800 ° C.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도이다.2A through 2C are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

도 2a를 참조하면, 도시되지는 않았지만, 트랜지스터, 플러그 및 층간절연막형성 등의 소정의 공정이 완료된 반도체 기판(20) 상에 캐패시터 산화막(21)을 형성하고, 기판(20)의 일부가 노출되도록 산화막(21)을 식각하여 실린더 형상의 캐패시터용 홀을 형성한다. 그 다음, 상기 홀 표면 및 산화막(21) 표면 상에 폴리실리콘막으로 하부전극(22)을 형성하고, 하부전극(22)이 형성된 홀에 매립되도록 기판 전면 상에 매립용 물질막(23)을 형성한다. 여기서, 매립용 물질막은 포토레지스트막이나 SOG막과 같은 플로우 특성을 갖는 막으로 형성한다. 그 후, 에치백 공정으로 매립용 물질막(23) 및 하부전극(22)을 산화막(21)의 표면이 노출되도록 전면식각하여 하부전극(22)을 서로 분리시킨다. 이때, 종래와 마찬가지로, 에치백 공정에 의해 하부전극(22)의 최상부가 뾰족한 형상을 이루게 된다.Referring to FIG. 2A, a capacitor oxide film 21 is formed on a semiconductor substrate 20 on which a predetermined process such as transistor, plug, and interlayer insulating film formation is completed, so that a portion of the substrate 20 is exposed. The oxide film 21 is etched to form a cylindrical capacitor hole. Subsequently, a lower electrode 22 is formed of a polysilicon film on the hole surface and the oxide film 21, and a buried material film 23 is formed on the entire surface of the substrate so that the lower electrode 22 is embedded in the hole in which the lower electrode 22 is formed. Form. Here, the buried material film is formed of a film having flow characteristics such as a photoresist film or an SOG film. Subsequently, the buried material layer 23 and the lower electrode 22 are etched to expose the surface of the oxide layer 21 by an etch back process to separate the lower electrodes 22 from each other. At this time, as in the prior art, the uppermost portion of the lower electrode 22 has a sharp shape by an etch back process.

도 2b를 참조하면, 하부전극(22)이 분리된 상기 기판을 질화처리하여 하부전극(22)의 최상부에 질화막(24)을 형성한다. 여기서, 질화막(24)은 소자의 동작시하부전극 최상부의 전계집중을 방지할 뿐만 아니라 하부전극 최상부에서의 HSG막의 형성을 방지하여 캐패시터 사이의 단락을 방지한다. 바람직하게, 질화처리는 질소를 포함한 플라즈마 분위기에서 수행하거나, 500 내지 800℃의 온도에서 N2, N2O 나 NH3와 같은 질소함유개스 분위기에서 수행한다.Referring to FIG. 2B, the substrate on which the lower electrode 22 is separated is nitrided to form a nitride film 24 on the top of the lower electrode 22. Here, the nitride film 24 not only prevents electric field concentration at the top of the lower electrode during operation of the device, but also prevents formation of the HSG film at the top of the lower electrode, thereby preventing short circuits between capacitors. Preferably, the nitriding treatment is performed in a plasma atmosphere containing nitrogen, or in a nitrogen-containing gas atmosphere such as N 2 , N 2 O or NH 3 at a temperature of 500 to 800 ° C.

도 2c를 참조하면, 공지된 방법으로 매립용 물질막(23)을 제거하고, 하부전극(22)의 표면적 증대를 위하여 하부전극(22) 표면에 HSG막(25)을 형성한다. 이때, 질화막(24)에 의해 하부전극(22) 최상부에는 HSG막(25)이 형성되지 않는다.Referring to FIG. 2C, the buried material film 23 is removed by a known method, and the HSG film 25 is formed on the surface of the lower electrode 22 to increase the surface area of the lower electrode 22. At this time, the HSG film 25 is not formed on the top of the lower electrode 22 by the nitride film 24.

상기 실시예에 의하면, 질화처리를 통하여 하부전극 최상부에 질화막을 형성함으로써 소자의 동작시 전계집중 현상을 방지할 수 있을 뿐만 아니라, 질화막에 의해 하부전극 최상부에서는 HSG막이 형성되지 않게 되므로 HSG막 인접에 따른 캐패시터 사이의 단락 현상도 효과적으로 방지할 수 있게 된다.According to the above embodiment, the nitride film is formed on the top of the lower electrode through the nitriding process to prevent the field concentration phenomenon during the operation of the device, and the HSG film is not formed on the top of the lower electrode by the nitride film, so that the HSG film is adjacent to the HSG film. The short circuit phenomenon between the capacitors can be effectively prevented.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 하부전극 최상부의 질화처리를 통하여 소자의 동작시 전계집중 현상을 방지하여 누설전류 특성을 향상시킴과 동시에 캐패시터 유전막의 파괴를 방지할 수 있을 뿐만 아니라, HSG막 형성에 따른 캐패시터 사이의 단락도 효과적으로 방지할 수 있다.The present invention described above not only prevents electric field concentration during the operation of the device through nitriding on the lower electrode, thereby improving leakage current characteristics and at the same time preventing breakage of the capacitor dielectric layer, and also between capacitors according to HSG film formation. The short circuit can also be effectively prevented.

Claims (4)

소정의 공정이 완료된 반도체 기판 상에 캐패시터 산화막을 형성하는 단계;Forming a capacitor oxide film on the semiconductor substrate on which a predetermined process is completed; 상기 산화막을 식각하여 캐패시터용 홀을 형성하는 단계;Etching the oxide layer to form a hole for a capacitor; 상기 홀 표면 및 산화막 표면 상에 폴리실리콘막으로 하부전극을 형성하는 단계;Forming a lower electrode on the hole surface and the oxide film surface using a polysilicon film; 상기 하부전극이 형성된 홀에 매립되도록 기판 전면 상에 매립용 물질막을 형성하는 단계;Forming a buried material film on the entire surface of the substrate so as to fill in the hole in which the lower electrode is formed; 상기 매립용 물질막 및 하부전극을 상기 산화막의 표면이 노출되도록 전면식각하여 하부전극을 분리하는 단계;Separating the bottom electrode by etching the buried material layer and the lower electrode to expose the surface of the oxide layer; 상기 기판을 질화처리하여 상기 하부전극의 최상부에 질화막을 형성하는 단계;Nitriding the substrate to form a nitride film on top of the lower electrode; 상기 매립용 물질막을 제거하는 단계; 및Removing the embedding material film; And 상기 하부전극 표면에 HSG막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.And forming an HSG film on the lower electrode surface. 제 1 항에 있어서,The method of claim 1, 상기 질화처리는 질소를 포함한 플라즈마 분위기에서 수행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The nitriding treatment is a capacitor manufacturing method of a semiconductor device, characterized in that performed in a plasma atmosphere containing nitrogen. 제 1 항에 있어서,The method of claim 1, 상기 질화처리는 500 내지 800℃의 온도에서 N2, N2O 나 NH3와 같은 질소함유개스 분위기에서 수행하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The nitriding treatment is a capacitor manufacturing method of a semiconductor device, characterized in that carried out in a nitrogen-containing gas atmosphere such as N 2 , N 2 O or NH 3 at a temperature of 500 to 800 ℃. 제 1 항에 있어서,The method of claim 1, 상기 매립용 물질막은 포토레지스트막이나 SOG막과 같은 플로우 특성을 갖는 막으로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.And the buried material film is formed of a film having flow characteristics such as a photoresist film or an SOG film.
KR1020020042324A 2002-07-19 2002-07-19 Method of manufacturing capacitor for semiconductor device KR20040008655A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7642715B2 (en) 2005-01-17 2010-01-05 Seiko Epson Corporation Light-emitting device comprising an improved gas barrier layer, method for manufacturing light-emitting device, and electronic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7642715B2 (en) 2005-01-17 2010-01-05 Seiko Epson Corporation Light-emitting device comprising an improved gas barrier layer, method for manufacturing light-emitting device, and electronic apparatus

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