KR20040008647A - Method of decrease contact resistance in semiconductor device - Google Patents
Method of decrease contact resistance in semiconductor device Download PDFInfo
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- KR20040008647A KR20040008647A KR1020020042315A KR20020042315A KR20040008647A KR 20040008647 A KR20040008647 A KR 20040008647A KR 1020020042315 A KR1020020042315 A KR 1020020042315A KR 20020042315 A KR20020042315 A KR 20020042315A KR 20040008647 A KR20040008647 A KR 20040008647A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 배선저항이 낮은 반도체소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device with low wiring resistance.
일반적으로 MOS 구조의 트랜지스터의 온/오프(On/Off)를 위한 전원을 인가하는 게이트의 경우 게이트산화막상에 폴리실리콘을 전극으로 사용하나, 인가된 신호의 전달시 지연시간을 줄이기 위하여 전체 배선저항이 낮아야 하므로 폴리실리콘막에 비해 저항이 낮은 텅스텐실리사이드막(W-silicide)을 폴리실리콘막상에 형성하여 전체 배선저항을 감소시키고 있다.In general, in the case of a gate applying power for turning on / off a transistor of a MOS structure, polysilicon is used as an electrode on the gate oxide layer, but in order to reduce the delay time when the applied signal is transmitted, the total wiring resistance is reduced. Since the thickness must be low, a tungsten silicide film (W-silicide) having a lower resistance than that of the polysilicon film is formed on the polysilicon film to reduce the overall wiring resistance.
그리고, 텅스텐실리사이드막은 비저항이 30∼70Ω/sq.로서 예를 들면, SiH2Cl2/WF6/H2을 기체원으로 하는 화학기상증착법(CVD)에 의해 형성된다.The tungsten silicide film has a specific resistance of 30 to 70? / Sq., For example, formed by chemical vapor deposition (CVD) using SiH 2 Cl 2 / WF 6 / H 2 as a gas source.
한편, 외부의 전원을 게이트에 인가하기 위해서는 외부 금속선을 게이트간의 연결을 위한 콘택을 형성하여야 하며, 이때 게이트와 금속선간의 저항이 높을 경우 전체 신호 전달의 지연을 초래할 수 있다. 따라서 금속선과 게이트간의 접촉저항을 향상시키는 것이 전체 소자의 안정성을 위해 매우 중요하다.Meanwhile, in order to apply external power to the gate, a contact for connecting the external metal line to the gate should be formed. In this case, if the resistance between the gate and the metal line is high, it may cause a delay in the entire signal transmission. Therefore, improving the contact resistance between the metal wire and the gate is very important for the stability of the entire device.
도 1은 종래기술에 따른 반도체소자를 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor device according to the prior art.
도 1을 참조하면, 반도체기판(11)의 소정 영역에 필드산화막(12)이 형성되고, 반도체기판(11)의 선택된 영역상에 게이트산화막(13)이 형성되며, 게이트산화막(13)상에 폴리실리콘막(14), 텅스텐실리사이드막(15)이 순서적으로 적층된 게이트전극이 형성된다.Referring to FIG. 1, a field oxide film 12 is formed in a predetermined region of a semiconductor substrate 11, a gate oxide film 13 is formed in a selected region of the semiconductor substrate 11, and a gate oxide film 13 is formed on a gate oxide film 13. A gate electrode in which the polysilicon film 14 and the tungsten silicide film 15 are sequentially stacked is formed.
그리고, 텅스텐실리사이드막(15)상에 게이트보호막(16)이 형성되고, 게이트산화막(13), 폴리실리콘막(14), 텅스텐실리사이드막(15) 및 게이트보호막(16)의 순서로 적층된 게이트라인의 양측벽에 스페이서(17)가 형성된다. 그리고, 게이트구조물의 에지에 정렬되어 반도체기판(11)내에 LDD(Lightly Doped Drain) 구조의 소스/드레인영역(18)이 형성되며, 게이트구조물을 포함한 반도체기판(11)의 전면에 층간절연막(19)이 형성된다. 그리고, 층간절연막(19)과 게이트보호막(16)을 관통하여 텅스텐실리사이드막(15)을 노출시킨 콘택에 티타늄막(20)과 티타늄나이트라이드막(21)의 순서로 적층된 배리어금속막이 형성되고, 배리어금속막상에 금속선(22)이 형성된다. 여기서, 금속선(22)으로는 통상적으로 알루미늄막 또는 텅스텐막이 적용된다.A gate protective film 16 is formed on the tungsten silicide film 15, and the gate stacked in the order of the gate oxide film 13, the polysilicon film 14, the tungsten silicide film 15, and the gate protection film 16. Spacers 17 are formed on both side walls of the line. A source / drain region 18 of a lightly doped drain (LDD) structure is formed in the semiconductor substrate 11 in alignment with the edge of the gate structure, and the interlayer insulating film 19 is formed on the entire surface of the semiconductor substrate 11 including the gate structure. ) Is formed. Then, a barrier metal film laminated in the order of the titanium film 20 and the titanium nitride film 21 is formed in the contact exposed through the interlayer insulating film 19 and the gate protection film 16 to expose the tungsten silicide film 15. The metal wire 22 is formed on the barrier metal film. Here, as the metal wire 22, an aluminum film or a tungsten film is usually applied.
한편, 게이트전극과 금속선간 접촉저항을 감소시키기 위해 텅스텐실리사이드막(15)과 금속선(22) 사이에 티타늄실리사이드막(Ti-silicide)(23)이 형성된다.On the other hand, a titanium silicide film (Ti-silicide) 23 is formed between the tungsten silicide film 15 and the metal wire 22 to reduce the contact resistance between the gate electrode and the metal wire.
도 1에서, 티타늄실리사이드막(23)을 형성하기 위해 텅스텐실리사이드막(15)상에 캡핑 폴리실리콘막(24)을 증착한 후 콘택을 형성할 때 캡핑 폴리실리콘막(24)을 남겨두었다가 배리어금속막 공정에서 티타늄막(20)과 캡핑 폴리실리콘막(24)을 반응시킨다.In FIG. 1, after the capping polysilicon film 24 is deposited on the tungsten silicide film 15 to form the titanium silicide film 23, the capping polysilicon film 24 is left when the contact is formed. In the film process, the titanium film 20 and the capping polysilicon film 24 are reacted.
그러나, 상술한 종래기술은 캡핑 폴리실리콘막(24)을 형성한 후 게이트전극을 패터닝하기 위한 식각과정중에 단차, 예를 들어 DRAM 소자에서는 셀영역과 주변회로영역간에 단차가 존재하는 지역에서, 캡핑 폴리실리콘막(24)의 잔유물이 형성되어 오염원으로 작용할 수 있는 문제점이 있다. 또한, 캡핑 폴리실리콘막(24)을 식각해야하므로 식각과정의 난이도 측면에서 불리하다.However, the above-described conventional technique is a step during the etching process for patterning the gate electrode after the capping polysilicon film 24 is formed, for example, in an area in which there is a step between a cell region and a peripheral circuit region in a DRAM device. Residue of the polysilicon film 24 is formed there is a problem that can act as a pollution source. In addition, since the capping polysilicon layer 24 must be etched, it is disadvantageous in terms of difficulty of the etching process.
또한, 게이트외에도 폴리실리콘막과 실리사이드막으로 이루어진 폴리사이드 구조를 갖는 비트라인과 금속선간 연결, 폴리실리콘막과 실리사이드막으로 이루어진 폴리사이드 구조를 갖는 하부 금속배선과 금속막 구조를 갖는 상부 금속배선간의 연결에서도 동일한 문제점이 발생된다.In addition to the gate, a bit line having a polyside structure composed of a polysilicon film and a silicide film and a metal line connection, and a lower metal wiring having a polyside structure composed of a polysilicon film and a silicide film and an upper metal wiring having a metal film structure The same problem occurs with connections.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로, 캡핑 폴리실리콘막 적용시 하부 배선과 상부배선간 콘택저항 증가를 억제하면서 단차 지역에서 캡핑 폴리실리콘막의 잔유물에 의한 오염을 제거하는데 적합한 반도체소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and is suitable for removing contamination by the residue of the capping polysilicon film in the stepped area while suppressing an increase in contact resistance between the lower wiring and the upper wiring when the capping polysilicon film is applied. Its purpose is to provide a method for manufacturing a semiconductor device.
도 1은 종래기술에 따른 게이트라인과 금속선간 연결 관계를 도시한 도면,1 is a view showing a connection relationship between a gate line and a metal line according to the prior art,
도 2a 내지 도 2g는 본 발명의 제1 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도,2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention;
도 3a 내지 도 3c는 본 발명의 제2 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도.3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 필드산화막31 semiconductor substrate 32 field oxide film
33 : 게이트산화막 34 : 폴리실리콘막33: gate oxide film 34: polysilicon film
35 : 텅스텐실리사이드막 36a : 게이트보호막35 tungsten silicide film 36a gate protective film
38 : LDD 영역 39 : 스페이서38: LDD region 39: spacer
40 : 소스/드레인영역 41 : 층간절연막40: source / drain area 41: interlayer insulating film
44 : 실리콘막 45 : 티타늄막44 silicon film 45 titanium film
46 : 티타늄실리사이드막 47 : 티타늄나이트라이드막46: titanium silicide film 47: titanium nitride film
48 : 금속선48: metal wire
상기 목적을 달성하기 위한 본 발명의 반도체소자의 제조 방법은 반도체기판 상부에 제1 금속실리사이드막과 보호막의 순서로 적층된 하부 배선을 형성하는 단계, 상기 하부배선을 포함한 전면에 층간절연막을 형성하는 단계, 상기 층간절연막과 상기 보호막을 식각하여 상기 제1 금속실리사이드막의 소정표면을 노출시키는 콘택홀을 형성하는 단계, 상기 콘택홀내에 노출된 상기 제1 금속실리사이드막상에 선택적으로 실리콘막을 성장시키는 단계, 상기 실리콘막상에 배리어메탈을 형성하는 단계, 상기 실리콘막의 실리콘과 상기 배리어메탈의 금속막을 반응시켜 제2 금속실리사이드막을 형성하는 단계, 및 상기 배리어메탈상에 상부 배선을 형성하는 단계를 포함함을 특징으로 하고, 상기 선택적으로 실리콘막을 성장시키는 단계는 SiH4또는 SiH2Cl2를 소스가스로 하고, 수소(H2) 가스를 환원가스로 하여 800℃∼950℃의 온도에서 성장시키되 0.5torr∼1.5torr의 압력하에서 이루어지거나, 또는 SiH4또는 SiH2Cl2를 소스가스로 하고, 수소(H2) 가스와 HCl 가스를 동시에 도입하여 800℃∼950℃의 온도에서 성장시키되 30torr∼150torr의 압력하에서 이루어짐을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object is to form a lower wiring stacked in the order of the first metal silicide film and a protective film on the semiconductor substrate, forming an interlayer insulating film on the front surface including the lower wiring Forming a contact hole exposing a predetermined surface of the first metal silicide layer by etching the interlayer insulating layer and the passivation layer, and selectively growing a silicon film on the first metal silicide layer exposed in the contact hole; Forming a barrier metal on the silicon film, reacting silicon of the silicon film with a metal film of the barrier metal to form a second metal silicide film, and forming an upper wiring on the barrier metal. In the step of growing the silicon film selectively SiH 4 or SiH 2 Cl 2 Is grown as a source gas, and hydrogen (H 2 ) gas is reduced gas, and is grown at a temperature of 800 ° C. to 950 ° C., under a pressure of 0.5torr to 1.5torr, or SiH 4 or SiH 2 Cl 2 as a source gas. Hydrogen (H 2 ) gas and HCl gas are introduced at the same time to grow at a temperature of 800 ℃ to 950 ℃, characterized in that it is made under a pressure of 30torr to 150torr.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
이하 후술한 실시예에서는 폴리실리콘막과 금속실리사이드막으로 이루어진 폴리사이드 구조 또는 금속실리사이드막의 하부 배선과 배리어메탈을 사이에 두고 금속막 구조의 상부 배선을 연결하는 경우, 금속실리사이드막상에 선택적으로 실리콘막을 성장시킨 후 실리사이드막을 형성하므로써 하부 배선과 상부 배선의 콘택저항을 낮추는 방법을 제공한다.In the following embodiments, a silicon film is selectively formed on the metal silicide film when the upper wiring of the metal film structure is connected between the polysilicon structure consisting of the polysilicon film and the metal silicide film or the lower wiring of the metal silicide film and the barrier metal therebetween. After growing, a silicide film is formed, thereby providing a method of lowering contact resistance of the lower interconnection and the upper interconnection.
도 2a 내지 도 2g는 본 발명의 제1 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(31)의 소정 부분에 LOCOS(Local Oxidation of Silicon)법 또는 STI(Shallow Trench Isolation) 법중에서 선택하여 필드산화막(32)을 형성한 후, 반도체기판(31)상에 게이트산화막(33)을 형성한다.As shown in FIG. 2A, after forming the field oxide layer 32 by selecting from a local oxide of silicon (LOCOS) method or a shallow trench isolation (STI) method on a predetermined portion of the semiconductor substrate 31, the semiconductor substrate 31 is formed. Is formed on the gate oxide film 33.
다음으로, 게이트산화막(33)상에 폴리실리콘막(34), 텅스텐실리사이드막(35)을 차례로 증착한다. 이때, 텅스텐실리사이드막(35)은 예를 들면, SiH2Cl2/WF6/H2을 기체원으로 하는 화학기상증착법(CVD)에 의해 형성된다.Next, the polysilicon film 34 and the tungsten silicide film 35 are sequentially deposited on the gate oxide film 33. At this time, the tungsten silicide film 35 is formed by chemical vapor deposition (CVD) using, for example, SiH 2 Cl 2 / WF 6 / H 2 as a gas source.
다음으로, 텅스텐실리사이드막(35)상에 게이트보호막(36)으로서 산화막 또는 질화막을 형성한 후, 게이트보호막(36)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 게이트전극을 정의하는 마스크(37)를 형성한다.Next, after forming an oxide film or a nitride film as the gate protection film 36 on the tungsten silicide film 35, a photosensitive film is coated on the gate protection film 36, and patterned by exposure and development to define a gate electrode 37 ).
도 2b에 도시된 바와 같이, 마스크(37)를 식각마스크로 하여 게이트보호막(36), 텅스텐실리사이드막(35), 폴리실리콘막(34), 게이트산화막(33)을 순차적으로 패터닝하여 게이트산화막(33a), 폴리실리콘막(34a), 텅스텐실리사이드막(35a), 게이트보호막(36a)의 순서로 적층되는 게이트라인을 형성한다.As shown in FIG. 2B, the gate protection layer 36, the tungsten silicide layer 35, the polysilicon layer 34, and the gate oxide layer 33 are sequentially patterned using the mask 37 as an etch mask. 33a), a polysilicon film 34a, a tungsten silicide film 35a, and a gate protection film 36a are formed in this order.
다음으로, 마스크(37)를 제거한다.Next, the mask 37 is removed.
도 2c에 도시된 바와 같이, 게이트라인을 마스크로 이용한 불순물 이온주입으로 반도체기판(31)내에 LDD 영역(38)을 형성하고, 게이트라인의 양측벽에 접하는스페이서(39)를 형성한다. 여기서, 스페이서(39)는 게이트라인을 포함한 전면에 질화막 또는 산화막을 증착한 후 전면식각하여 형성한다.As shown in FIG. 2C, the LDD region 38 is formed in the semiconductor substrate 31 by impurity ion implantation using the gate line as a mask, and a spacer 39 is formed in contact with both side walls of the gate line. Here, the spacer 39 is formed by depositing a nitride film or an oxide film on the entire surface including the gate line and then etching the entire surface.
다음으로, 게이트라인 및 스페이서를 마스크로 하여 반도체기판에 불순물을 이온주입하여 LDD 영역(38)에 접하는 소스/드레인영역(40)을 형성한다.Next, impurities are implanted into the semiconductor substrate using the gate lines and the spacers as masks to form the source / drain regions 40 in contact with the LDD regions 38.
도 2d에 도시된 바와 같이, 반도체기판(31)의 전면에 층간절연막(41)을 형성한 후, 층간절연막(41)상에 콘택마스크(42)를 형성한 후, 콘택마스크(42)를 식각마스크로 하여 층간절연막(41)을 식각하고 연속해서 게이트보호막(36a)을 식각하여 텅스텐실리사이드막(35a)의 표면을 노출시키는 콘택홀(43)을 형성한다.As shown in FIG. 2D, after the interlayer insulating film 41 is formed on the entire surface of the semiconductor substrate 31, the contact mask 42 is formed on the interlayer insulating film 41, and then the contact mask 42 is etched. The interlayer insulating film 41 is etched using the mask, and the gate protection film 36a is subsequently etched to form the contact hole 43 exposing the surface of the tungsten silicide film 35a.
도 2e에 도시된 바와 같이, 콘택마스크(42)를 제거한 후, 콘택홀(43) 형성시 발생된 부산물을 제거하기 위한 세정과정을 수행하고, 선택적 실리콘 증착법을 이용하여 콘택홀(43)의 바닥에 노출된 텅스텐실리사이드막(35a)상에 실리콘막(44)을 선택적으로 성장시킨다.As shown in FIG. 2E, after the contact mask 42 is removed, a cleaning process is performed to remove the by-products generated when the contact hole 43 is formed, and the bottom of the contact hole 43 is subjected to selective silicon deposition. The silicon film 44 is selectively grown on the tungsten silicide film 35a exposed.
즉, 콘택홀(43) 형성시 노출된 텅스텐실리사이드막(35a)의 표면만이 실리콘막(44) 성장을 위한 핵생성 자리를 제공하므로 텅스텐실리사이드막(35a)상에서만 실리콘막(44)이 성장한다.That is, since only the surface of the tungsten silicide film 35a exposed when forming the contact hole 43 provides a nucleation site for the growth of the silicon film 44, the silicon film 44 grows only on the tungsten silicide film 35a. do.
실리콘막(44)을 선택적으로 성장시키기 위한 제1 방법으로는 SiH4또는 SiH2Cl2를 소스가스로 하고, 수소(H2) 가스를 환원가스로 하여 800℃∼950℃의 온도에서 성장시킨다. 이때, 수소 가스만을 환원가스로 사용하는 경우, 성장속도를 낮추기 위해 0.5torr∼1.5torr의 저압에서 이루어진다.As a first method for selectively growing the silicon film 44, SiH 4 or SiH 2 Cl 2 is used as a source gas, and hydrogen (H 2 ) gas is used as a reducing gas to grow at a temperature of 800 ° C to 950 ° C. . At this time, when only hydrogen gas is used as the reducing gas, it is made at a low pressure of 0.5torr to 1.5torr to lower the growth rate.
그리고, 제2 방법은 SiH4또는 SiH2Cl2를 소스가스로 하고, 수소(H2) 가스와 HCl 가스를 동시에 도입하여 800℃∼950℃의 온도에서 성장시킨다. 이때, HCl 가스를 도입하는 이유는 성장속도를 낮추기 위해 성장과 동시에 식각이 일어나도록 하기 위함이며, 제2 방법에 따른 실리콘막(44)의 성장은 30torr∼150torr의 압력에서 이루어진다.In the second method, SiH 4 or SiH 2 Cl 2 is used as a source gas, and hydrogen (H 2 ) gas and HCl gas are simultaneously introduced and grown at a temperature of 800 ° C. to 950 ° C. At this time, the reason for introducing the HCl gas is to cause the etching to occur at the same time as the growth in order to lower the growth rate, the growth of the silicon film 44 according to the second method is made at a pressure of 30torr ~ 150torr.
도 2f에 도시된 바와 같이, 전면에 티타늄막(45)을 증착한 후, 티타늄막(45)과 실리콘막(44)을 반응시켜 티타늄실리사이드막(46)을 형성한다.As shown in FIG. 2F, after the titanium film 45 is deposited on the entire surface, the titanium silicide film 46 is formed by reacting the titanium film 45 with the silicon film 44.
티타늄실리사이드막(46)을 형성하는 제1 방법은, 먼저 실리콘막(44)을 포함한 전면에 상온∼400℃의 온도에서 물리기상증착법(PVD)을 통해 60Å∼300Å의 두께로 티타늄막(45)을 증착한 후 600℃∼900℃의 온도에서 20초∼60초동안 급속열처리하여 티타늄실리사이드막(46)을 형성한다. 이때, 급속열처리시 분위기는 질소 분위기 또는 진공이다.In the first method of forming the titanium silicide film 46, the titanium film 45 has a thickness of 60 kPa to 300 kPa through physical vapor deposition (PVD) at a temperature of room temperature to 400 ° C. on the entire surface including the silicon film 44. After the deposition, the titanium silicide film 46 was formed by rapid heat treatment at a temperature of 600 ° C to 900 ° C for 20 seconds to 60 seconds. At this time, the atmosphere during rapid heat treatment is nitrogen atmosphere or vacuum.
그리고, 티타늄실리사이드막(46)을 형성하는 제2 방법은, 실리콘막(44)을 포함한 전면에 티타늄막(45)을 530℃∼700℃의 온도에서 화학기상증착법(CVD)을 통해 60Å∼100Å의 두께로 증착한다. 이때, 증착온도가 530℃∼700℃이므로 티타늄막(45) 증착과 동시에 인시튜(In-situ)로 티타늄막(45)이 실리콘막(44)과 반응하여 티타늄실리사이드막(46)을 형성시킨다.In the second method of forming the titanium silicide film 46, the titanium film 45 is formed on the entire surface including the silicon film 44 by chemical vapor deposition (CVD) at a temperature of 530 ° C to 700 ° C. To a thickness of. At this time, since the deposition temperature is 530 ° C to 700 ° C, the titanium film 45 reacts with the silicon film 44 in-situ at the same time as the titanium film 45 is deposited to form the titanium silicide film 46. .
도 2g에 도시된 바와 같이, 티타늄막(45)을 포함한 전면에 티타늄나이트라이드막(47)을 100Å∼300Å의 두께로 증착한 후, 티타늄나이트라이드막(47)상에 텅스텐막 또는 알루미늄막과 같은 금속막을 형성하고 식각 과정을 수행하여 게이트라인에 전기적인 신호를 인가하기 위한 금속선(48)을 형성한다.As shown in FIG. 2G, the titanium nitride film 47 is deposited on the entire surface including the titanium film 45 to a thickness of 100 kPa to 300 kPa, and then the tungsten film or aluminum film is deposited on the titanium nitride film 47. The same metal layer is formed and an etching process is performed to form a metal line 48 for applying an electrical signal to the gate line.
도 3a 내지 도 3c는 제2 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도이다.3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment.
도 3a에 도시된 바와 같이, 반도체기판(51)의 소정 부분에 LOCOS법 또는 STI 법중에서 선택하여 필드산화막(52)을 형성한 후, 반도체기판(51)상에 게이트산화막(53)을 형성한다.As shown in FIG. 3A, the field oxide film 52 is formed on a predetermined portion of the semiconductor substrate 51 by selecting from the LOCOS method or the STI method, and then the gate oxide film 53 is formed on the semiconductor substrate 51. .
다음에, 게이트산화막(53)상에 게이트전극(54)을 형성한 후, 게이트전극(54)을 마스크로 이용한 저농도 불순물의 이온주입을 통해 반도체기판(51)내에 LDD 영역(55)을 형성하고, 게이트전극(54)의 양측벽에 접하는 스페이서(56)를 형성한다.Next, after the gate electrode 54 is formed on the gate oxide film 53, the LDD region 55 is formed in the semiconductor substrate 51 through ion implantation of low concentration impurities using the gate electrode 54 as a mask. A spacer 56 is formed in contact with both side walls of the gate electrode 54.
다음으로, 게이트전극(54) 및 스페이서(56)를 마스크로 반도체기판(51)에 고농도의 불순물을 이온주입하여 LDD 영역(55)에 접하는 소스/드레인영역(57)을 형성한다.Next, a high concentration of impurities are implanted into the semiconductor substrate 51 using the gate electrode 54 and the spacer 56 as a mask to form a source / drain region 57 in contact with the LDD region 55.
다음에, 반도체기판(51)상에 제1 층간절연막(58)을 형성한 후, 제1 층간절연막(58)을 식각하여 반도체기판(51)의 소정 표면을 노출시키는 비트라인콘택홀을 형성한다. 이 비트라인콘택홀에 텅스텐막을 플러깅시켜 텅스텐플러그(59)를 형성한 후, 텅스텐플러그(59)에 연결되는 텅스텐실리사이드막(60)으로 된 비트라인을 형성한다. 여기서, 텅스텐실리사이드막(60)상에 비트라인을 보호하는 비트라인보호막(61)이 형성되어 있다.Next, after the first interlayer insulating film 58 is formed on the semiconductor substrate 51, the first interlayer insulating film 58 is etched to form bit line contact holes for exposing a predetermined surface of the semiconductor substrate 51. . The tungsten film is plugged into the bit line contact hole to form a tungsten plug 59, and then a bit line made of a tungsten silicide film 60 connected to the tungsten plug 59 is formed. Here, a bit line protective film 61 is formed on the tungsten silicide film 60 to protect the bit line.
다음으로, 비트라인을 포함한 제1 층간절연막(58)상에 제2 층간절연막(62)을형성한 후, 제2 층간절연막(62)을 식각하고 연속해서 비트라인보호막(61)을 식각하여 텅스텐실리사이드막(60)의 소정 표면을 노출시키는 금속선 콘택홀(63)을 형성한다.Next, after forming the second interlayer dielectric layer 62 on the first interlayer dielectric layer 58 including the bit line, the second interlayer dielectric layer 62 is etched and the bit line protective layer 61 is subsequently etched to form tungsten. A metal line contact hole 63 exposing a predetermined surface of the silicide film 60 is formed.
도 3b에 도시된 바와 같이, 금속선 콘택홀(63) 형성시 발생된 부산물을 제거하기 위한 세정과정을 수행하고, 선택적 실리콘 증착법을 이용하여 금속선 콘택홀(63)의 바닥에 노출된 텅스텐실리사이드막(60)상에 실리콘막(64)을 선택적으로 성장시킨다.As shown in FIG. 3B, a tungsten silicide layer exposed to the bottom of the metal line contact hole 63 may be cleaned by performing a cleaning process to remove by-products generated when the metal line contact hole 63 is formed. The silicon film 64 is selectively grown on 60.
즉, 금속선 콘택홀(63) 형성시 노출된 텅스텐실리사이드막(60)의 표면만이 실리콘막(64) 성장을 위한 핵생성 자리를 제공하므로 텅스텐실리사이드막(60)상에서만 실리콘막(64)이 성장한다.That is, since only the surface of the tungsten silicide film 60 exposed when the metal wire contact hole 63 is formed provides a nucleation site for the growth of the silicon film 64, the silicon film 64 is formed only on the tungsten silicide film 60. To grow.
실리콘막(64)을 선택적으로 성장시키기 위한 제1 방법으로는 SiH4또는 SiH2Cl2를 소스가스로 하고, 수소(H2) 가스를 환원가스로 하여 800℃∼950℃의 온도에서 성장시킨다. 이때, 수소 가스만을 환원가스로 사용하는 경우, 성장속도를 낮추기 위해 0.5torr∼1.5torr의 저압에서 이루어진다.As a first method for selectively growing the silicon film 64, SiH 4 or SiH 2 Cl 2 is used as a source gas, and hydrogen (H 2 ) gas is used as a reducing gas to grow at a temperature of 800 ° C to 950 ° C. . At this time, when only hydrogen gas is used as the reducing gas, it is made at a low pressure of 0.5torr to 1.5torr to lower the growth rate.
그리고, 제2 방법은 SiH4또는 SiH2Cl2를 소스가스로 하고, 수소(H2) 가스와 HCl 가스를 동시에 도입하여 800℃∼950℃의 온도에서 성장시킨다. 이때, HCl 가스를 도입하는 이유는 성장속도를 낮추기 위해 성장과 동시에 식각이 일어나도록 하기 위함이며, 제2 방법에 따른 실리콘막(44)의 성장은 30torr∼150torr의 압력에서 이루어진다.In the second method, SiH 4 or SiH 2 Cl 2 is used as a source gas, and hydrogen (H 2 ) gas and HCl gas are simultaneously introduced and grown at a temperature of 800 ° C. to 950 ° C. At this time, the reason for introducing the HCl gas is to cause the etching to occur at the same time as the growth in order to lower the growth rate, the growth of the silicon film 44 according to the second method is made at a pressure of 30torr ~ 150torr.
도 3c에 도시된 바와 같이, 전면에 전면에 티타늄막(65)을 증착한 후, 티타늄막(65)과 실리콘막(64)을 반응시켜 티타늄실리사이드막(66)을 형성한다.As shown in FIG. 3C, after the titanium film 65 is deposited on the entire surface, the titanium silicide film 66 is formed by reacting the titanium film 65 with the silicon film 64.
티타늄실리사이드막(66)을 형성하는 제1 방법은, 먼저 실리콘막(66)을 포함한 전면에 상온∼400℃의 온도에서 물리기상증착법(PVD)을 통해 60Å∼300Å의 두께로 티타늄막(65)을 증착한 후 600℃∼900℃의 온도에서 20초∼60초동안 급속열처리하여 티타늄실리사이드막(66)을 형성한다. 이때, 급속열처리시 분위기는 질소 분위기 또는 진공이다.In the first method of forming the titanium silicide film 66, the titanium film 65 has a thickness of 60 kPa to 300 kPa through physical vapor deposition (PVD) at a temperature of room temperature to 400 ° C. on the entire surface including the silicon film 66. After vapor deposition, the titanium silicide film 66 was formed by rapid heat treatment at a temperature of 600 ° C to 900 ° C for 20 seconds to 60 seconds. At this time, the atmosphere during rapid heat treatment is nitrogen atmosphere or vacuum.
그리고, 티타늄실리사이드막(66)을 형성하는 제2 방법은, 실리콘막(64)을 포함한 전면에 티타늄막(65)을 530℃∼700℃의 온도에서 화학기상증착법(CVD)을 통해 60Å∼100Å의 두께로 증착한다. 이때, 증착온도가 530℃∼700℃이므로 티타늄막(65) 증착과 동시에 인시튜로 티타늄막(65)이 실리콘막(64)과 반응하여 티타늄실리사이드막(66)을 형성시킨다.In the second method of forming the titanium silicide film 66, the titanium film 65 is formed on the entire surface including the silicon film 64 by chemical vapor deposition (CVD) at a temperature of 530 ° C to 700 ° C. To a thickness of. At this time, since the deposition temperature is 530 ° C to 700 ° C, the titanium film 65 reacts with the silicon film 64 in situ at the same time as the titanium film 65 is deposited to form the titanium silicide film 66.
다음으로, 티타늄막(65)을 포함한 전면에 티타늄나이트라이드막(67)을 100Å∼300Å의 두께로 증착한 후, 티타늄나이트라이드막(67)상에 텅스텐막 또는 알루미늄막과 같은 금속막을 형성하고 식각 과정을 수행하여 비트라인에 전기적인 신호를 인가하기 위한 금속선(68)을 형성한다.Next, a titanium nitride film 67 is deposited on the entire surface including the titanium film 65 to a thickness of 100 to 300 mm, and then a metal film such as a tungsten film or an aluminum film is formed on the titanium nitride film 67. An etching process is performed to form a metal line 68 for applying an electrical signal to the bit line.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 하부 배선과 상부 배선간의 콘택저항을 감소시켜 소자의 동작속도를 향상시킬 수 있는 효과가 있다.The present invention described above has the effect of improving the operation speed of the device by reducing the contact resistance between the lower wiring and the upper wiring.
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