KR20040007987A - Method of manufacture semiconductor device - Google Patents
Method of manufacture semiconductor device Download PDFInfo
- Publication number
- KR20040007987A KR20040007987A KR1020020041276A KR20020041276A KR20040007987A KR 20040007987 A KR20040007987 A KR 20040007987A KR 1020020041276 A KR1020020041276 A KR 1020020041276A KR 20020041276 A KR20020041276 A KR 20020041276A KR 20040007987 A KR20040007987 A KR 20040007987A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- film
- gate
- forming
- silicon
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 37
- 239000010703 silicon Substances 0.000 claims abstract description 37
- 238000005468 ion implantation Methods 0.000 claims abstract description 31
- 239000003990 capacitor Substances 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000000137 annealing Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 150000002431 hydrogen Chemical class 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- -1 LDD ions Chemical class 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract 1
- 229910017052 cobalt Inorganic materials 0.000 description 6
- 239000010941 cobalt Substances 0.000 description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 디램(DRAM)과 로직(Logic)을 하나의 칩(Chip)으로 구현하는 디바이스(device)를 제조하는 반도체공정 중 평면 MOS 캐패시터 형성 지역 및 이를 조절하는 소자구현지역에 선택적 성장법을 이용하여 실리콘을 성장시킨 후 웰(Well) 이온주입부터 살리사이드(Salicide) 공정을 진행하는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, to form and control a planar MOS capacitor forming region during a semiconductor process of manufacturing a device implementing DRAM and logic as one chip. The present invention relates to a method of fabricating a semiconductor device in which silicon is grown using a selective growth method in a device implementation region, and then a Salicide process is performed from a well ion implantation.
도 1a 내지 도 1g는 종래 기술에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정 단면도이다.1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
먼저, 도 1a와 같이, 실리콘(Si) 기판(1) 위에 소자분리를 위한 샬로우 트렌치 분리(Shallow Trench Isolation; STI)막(2)을 형성한다. 이 때, 상기 STI막(2)은 절연막(또는 산화막)으로 충진(fill) 및 화학적기계적연마(CMP) 공정으로 액티브 이외의 영역을 처리한다(평탄화).First, as shown in FIG. 1A, a shallow trench isolation (STI) film 2 for device isolation is formed on a silicon (Si) substrate 1. At this time, the STI film 2 is filled with an insulating film (or an oxide film) and processes a region other than active by a chemical mechanical polishing (CMP) process (planarization).
그 다음, 도 1b와 같이, 상기 구조물 위에 마스크 패턴(3)을 형성한 후 상기 실리콘 기판(1) 내에 웰(Well) 이온을 주입(4)하여 P웰 및 N웰을 형성한다.Next, as shown in FIG. 1B, after forming the mask pattern 3 on the structure, well ions are implanted into the silicon substrate 1 to form P wells and N wells.
그 다음, 도 1c와 같이, 상기 구조물 위에 게이트 산화막(5)과 폴리 실리콘막(6)을 증착한 후 패터닝 공정을 통해 게이트 전극을 형성한다. 이때, 폴리 실리콘막(6)은 등방성 식각된다.Next, as shown in FIG. 1C, a gate oxide layer 5 and a polysilicon layer 6 are deposited on the structure, and then a gate electrode is formed through a patterning process. At this time, the polysilicon film 6 is isotropically etched.
그 다음, 도 1d와 같이, 게이트 패턴을 형성한 후 LDD(Lightly Doped Drain) 이온주입층(7)에 LDD 이온주입을 수행함으로써 소스/드레인 접합층 간의 흐르는 캐리어들의 전기장을 조절하게 된다. 이는 소자의 크기가 감소하나 그에 따라 소자의 동작전압이 작아지지 못하여 채널 드레인 쪽 일부분에 매우 높은 전기장(Electric Field)이 집중되는 현상 때문에 원치 않는 캐리어의 흐름이 형성되어 소자의 작동에 어려움을 갖게되는 핫 캐리어 이펙트(HCE)를 최소화 할 수 있다.Next, as shown in FIG. 1D, after the gate pattern is formed, LDD ion implantation is performed on the lightly doped drain (LDD) ion implantation layer 7 to control electric fields of carriers flowing between the source / drain junction layers. This is because the size of the device is reduced, but the operating voltage of the device is not reduced, so that a very high electric field is concentrated in a portion of the channel drain side, and thus an unwanted carrier flow is formed, which makes it difficult to operate the device. Hot Carrier Effect (HCE) can be minimized.
이 후 LDD 이온주입층(7) 형성으로 인해 채널의 길이가 작아지게 되어 문턱전압이 낮아지는 SCE(Short Channel Effect) 특성을 개선시키고자 틸트(tilt)를 주어 이온주입을 실시하여 LDD 이온주입층(7) 주변에 틸트 이온주입층(8)을 형성시킴으로써 SCE 현상을 완화시키게 된다.After the LDD ion implantation layer 7, formation of the LDD ion implantation layer is performed by giving ion to give a tilt to improve the characteristics of the SCE (Short Channel Effect), in which the channel length is reduced and the threshold voltage is lowered. (7) By forming the tilt ion implantation layer 8 in the periphery, the SCE phenomenon is alleviated.
그 다음, 도 1e와 같이, 상기 게이트(6) 측벽에 버퍼 산화막(9)을 형성한다.Next, as shown in FIG. 1E, a buffer oxide film 9 is formed on the sidewall of the gate 6.
그 다음, 상기 구조물 위에 질화막을 증착한 후 식각하여 상기 게이트 측벽에 LDD 스페이서(10)를 형성한다.Next, a nitride film is deposited on the structure and then etched to form an LDD spacer 10 on the sidewall of the gate.
그 다음, 도 1f와 같이, 상기 구조물 위에 N+/P+ 이온주입(11) 공정을 진행하여 소스/드레인 영역(12)을 형성한다.Next, as shown in FIG. 1F, a process of N + / P + ion implantation 11 is performed on the structure to form a source / drain region 12.
그 다음, 도 1g와 같이, 상기 구조물 위에 실리사이드막을 형성하기 위한 코발트(Co) 및 캡핑(Capping) 물질인 TiN막(도시되지 않음)을 형성한 후 어닐 공정을 실시한다.Next, as shown in FIG. 1G, a cobalt (Co) and a TiN film (not shown), which is a capping material, are formed on the structure to perform an annealing process.
그 다음, 캡핑 물질 및 반응하지 않은 코발트(Co)막을 제거하고 나면 폴리실리콘이 드러나 있는 게이트(6) 및 소스/드레인 영역(12) 위에 코발트 실리사이드막(13)이 형성된다.Then, after removing the capping material and the unreacted cobalt (Co) film, a cobalt silicide film 13 is formed on the gate 6 and the source / drain region 12 where the polysilicon is exposed.
그러나, 종래의 반도체 소자의 제조 방법에 있어서는, 도 1c와 같이, 게이트 산화막을 절연체로 하는 캐패시터를 구현하는데 있어 캐패시터가 형성될 수 있는 영역이 한계를 가지게 된다. 이렇게 되면 캐패시터의 용량의 한계를 갖게되어 원하는 캐패시터 용량을 얻기 위해서는 평면 MOS 캐패시터 형성 면적을 늘여야 한다. 그러나, 이럴 경우 웨이퍼 내의 집적도가 떨어지며 하나의 제품의 칩 크기가 커지는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device, as shown in FIG. 1C, an area where a capacitor can be formed has a limit in implementing a capacitor having a gate oxide film as an insulator. This limits the capacitance of the capacitor, which requires increasing the planar MOS capacitor formation area to achieve the desired capacitor capacity. However, in this case, there is a problem in that the density in the wafer is reduced and the chip size of one product is increased.
즉, 시스템(System) 온(On) 칩(Chip) 사업의 일환으로 디램(DRAM)과 로직(Logic)을 하나의 칩(Chip)으로 구현하는 공정 중 평면 모스 캐패시터를 이용한 디램(DRAM)의 경우 로직 공정을 그대로 이용하여 구현하나 캐패시터 형성지역의 한계에 따라 캐패시터의 용량에 한계를 가지는 문제점이 있었다.That is, in the case of DRAM using a planar MOS capacitor during the process of implementing DRAM and logic as one chip as part of the system on chip business The logic process is used as it is, but there is a problem in that the capacity of the capacitor is limited according to the limitation of the capacitor formation region.
따라서, 본 발명은 상기 문제점을 해결하기 위하여 이루어진 것으로, 본 발명의 목적은 먼저 선택적 성장법을 이용하여 실리콘을 성장시킨 후 평면 모스 캐패시터 및 소자를 구현시키는 공정을 진행하므로써, 웨이퍼 내의 집적도의 저하 없이도 선택적으로 성장된 실리콘의 옆면까지 평면 모스 캐패시터 영역으로 활용할 수 있어 면적 증가를 통한 캐패시터 용량을 증가시킬 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to first grow a silicon by using a selective growth method, and then proceed with a process of implementing a planar MOS capacitor and a device, without deteriorating the density in the wafer. To provide a method for manufacturing a semiconductor device that can be used as a planar MOS capacitor region to the side surface of the selectively grown silicon can increase the capacitor capacity through the increase in area.
도 1a 내지 도 1g는 종래 기술에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정 단면도1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2h는 본 발명에 의한 반도체 소자의 제조 방법을 설명하기 위한 공정 단면도2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
21 : 실리콘 기판22 : 샬로우 트렌치 분리막21 silicon substrate 22 shallow trench isolation membrane
23 : 실리콘 성장막24 : 포토 레지스트막23 silicon growth film 24 photoresist film
26 : 게이트 산화막27 : 게이트 폴리 실리콘막26 gate oxide film 27 gate polysilicon film
28 : LDD 이온주입층29 : 틸트 이온주입층28: LDD ion implantation layer 29: tilt ion implantation layer
30 : 버퍼 산화막31 : 스페이서층30 buffer oxide film 31 spacer layer
33 : 소스/드레인 접합층34 : 실리사이드막33 source / drain bonding layer 34 silicide film
상기 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조 방법은,A semiconductor device manufacturing method according to the present invention for achieving the above object,
실리콘 기판 위에 샬로우 트렌치 분리(STI)막을 형성한 후 절연을 위해 산화막을 형성하는 단계;Forming a shallow trench isolation (STI) film on the silicon substrate and then forming an oxide film for insulation;
상기 산화막이 없는 실리콘 기판 위에 선택적 성장법을 이용하여 실리콘을 성장시켜 실리콘 성장막을 형성하는 단계;Forming a silicon growth film by growing silicon on the silicon substrate without the oxide film using a selective growth method;
상기 구조물 위에 이온을 주입하여 N 웰 및 P 웰을 형성하는 단계;Implanting ions onto the structure to form N wells and P wells;
상기 구조물 위에 게이트 산화막과 폴리 실리콘막을 형성하는 단계;Forming a gate oxide film and a polysilicon film on the structure;
상기 게이트 산화막과 폴리 실리콘막을 트랜지스터의 게이트로 사용할 제 1 지역과 평면 캐패시터로 사용할 제 2 지역으로 나누어 동시에 패터닝하되 상기 제 2 지역에서는 상기 실리콘 성장막의 윗쪽면만 아니라 측면까지 상기 게이트 산화막과 폴리 실리콘막이 형성되도록 패터닝하는 단계;The gate oxide layer and the polysilicon layer are divided into a first region to be used as a gate of a transistor and a second region to be used as a planar capacitor, and are simultaneously patterned. Patterning as possible;
상기 구조물 위에 LDD 이온 및 틸트 이온을 주입하여 LDD 이온주입층 및 틸트 이온주입층을 형성하는 단계;Implanting LDD ions and tilt ions onto the structure to form an LDD ion implantation layer and a tilt ion implantation layer;
상기 게이트의 측벽에 버퍼 산화막 및 LDD 스페이서를 형성하는 단계;Forming a buffer oxide layer and an LDD spacer on sidewalls of the gate;
상기 구조물 위에 N+/P+ 이온주입 공정을 진행하여 소스/드레인 접합층을 형성하는 단계; 및Performing a N + / P + ion implantation process on the structure to form a source / drain junction layer; And
상기 구조물 위에 실리사이드막을 형성하기 위한 금속물질막을 형성 한 후 어닐 공정을 실시하여 상기 게이트 및 상기 소스/드레인 접합층 위에 실리사이드막을 형성하는 단계를 구비한 것을 특징으로 한다.And forming a silicide layer on the gate and the source / drain junction layer by performing an annealing process after forming a metal material layer for forming the silicide layer on the structure.
상기 실리콘 성장막을 형성하기 전에 불화수소(HF) 계열의 화합물을 이용하여 자연산화막을 제거하는 것을 특징으로 한다.Before the silicon growth film is formed, a natural oxide film is removed using a hydrogen fluoride (HF) -based compound.
상기 실리콘 성장막을 형성하기 전에 수소 어닐링 공정을 통해 에피성장이 되어질 실리콘 기판을 수소로 보호하는 것을 특징으로 한다.Before forming the silicon growth layer, a hydrogen annealing process is used to protect the silicon substrate to be epi-growth with hydrogen.
상기 수소 어닐링 공정은 800-1000℃의 온도 범위에서 수소(H2)를 분당 1 내지 20 리터(liters)를 흘리며 약 10초 내지 5분 동안 진행하는 것을 특징으로 한다.The hydrogen annealing process is characterized in that for about 10 seconds to 5 minutes flowing hydrogen (H 2 ) 1 to 20 liters (liters) per minute in the temperature range of 800-1000 ℃.
상기 실리콘 성장막의 두께는 100 내지 2000Å의 두께로 진행하는 것을 특징으로 한다.The silicon growth film has a thickness of 100 to 2000 kPa.
상기 실리콘 성장막의 형성시 에피 성장의 조건은 650 내지 900℃, 10mtorr 내지 10torr 범위로 진행하는 것을 특징으로 한다.The epitaxial growth condition during the formation of the silicon growth layer is characterized in that the progress in the range of 650 to 900 ℃, 10mtorr to 10torr.
상기 실리콘 성장막의 형성시 사용되는 가스는 SiH2Cl2와 HCl을 각각 40 내지 800cc, 10 내지 200cc 범위내에서 진행하는 것을 특징으로 한다.Gas used in the formation of the silicon growth film is characterized in that the SiH 2 Cl 2 and HCl proceeds in the range of 40 to 800cc, 10 to 200cc, respectively.
상기 실리콘 성장막의 소스는 SiH2Cl2, SiH4, Si2H6중 어느 하나를 사용하는 것을 특징으로 한다.The source of the silicon growth film is characterized by using any one of SiH 2 Cl 2 , SiH 4 , Si 2 H 6 .
상기 선택적 성장을 위해 첨가되는 가스는 HCl 또는 Cl2가스를 사용하는 것을 특징으로 한다.The gas added for the selective growth is characterized by using HCl or Cl 2 gas.
상기 틸트 이온주입 공정 중 소스는 P웰의 경우에는 보론(Boron) 또는 BF2이온을 사용하고, N웰의 경우에는 인(P) 또는 비소를 이용하는 것을 특징으로 한다.The source of the tilt ion implantation process is characterized by using boron (Bron) or BF 2 ions in the case of P wells, phosphorus (P) or arsenic in the case of N wells.
상기 틸트 이온주입 공정 중 에너지는 2 내지 50KeV의 범위로 하는 것을 특징으로 한다.Energy during the tilt ion implantation process is characterized in that the range of 2 to 50 KeV.
상기 틸트 이온주입 공정 중 도우즈는 1.0E12 내지 5.0E13 atoms/cm2의 범위로 하는 것을 특징으로 한다.The dose in the tilt ion implantation step is characterized in that the range of 1.0E12 to 5.0E13 atoms / cm 2 .
상기 틸트 이온주입 공정 중 틸트는 7 내지 45°로 진행하는 것을 특징으로한다.The tilt during the tilt ion implantation process is characterized in that it proceeds to 7 to 45 °.
상기 틸트 이온주입 공정 중 트위스트는 0 내지 360°의 범위로 하는 것을 특징으로 한다.Twist during the tilt ion implantation process is characterized in that in the range of 0 to 360 °.
상기 틸트 이온주입 공정 진행시 순환 조건은 4회로 하는 것을 특징으로 한다.The circulation conditions during the tilt ion implantation process is characterized in that four times.
상기 게이트 산화막의 두께는 20 내지 70Å 정도로 형성하는 것을 특징으로 한다.The gate oxide film may have a thickness of about 20 to about 70 kPa.
상기 폴리 실리콘막의 두께는 1500 내지 2500Å 정도로 형성하는 것을 특징으로 한다.The thickness of the polysilicon film is formed to about 1500 to 2500Å.
상기 버퍼 산화막의 두께는 150 내지 300Å 정도로 형성하는 것을 특징으로 한다.The buffer oxide film may be formed to have a thickness of about 150 to 300 kPa.
상기 LDD 스페이서의 두께는 800 내지 1500Å 정도로 형성하는 것을 특징으로 한다.The LDD spacer may have a thickness of about 800 to 1500 mW.
(실시예)(Example)
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h는 본 발명에 의한 반도체 소자의 제조 방법을 설명하기 위한 공정 단면도이다.2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 도 2a는 소자를 형성하기 전 패턴(Pattern) 상태를 나타낸 것으로, 소자가 형성될 지역을 확보하고자 실리콘(Si) 기판(21) 위에 소자분리를 위한 샬로우트렌치 분리(Shallow Trench Isolation; STI)막(22)을 형성한다.First, FIG. 2A illustrates a pattern state before forming a device. In order to secure a region where a device is to be formed, a shallow trench isolation for device isolation on a silicon (Si) substrate 21 is provided. Film 22 is formed.
그 다음, 도 2b와 같이, 산화막이 없는 실리콘 지역에만 선택적으로 실리콘을 성장시켜 실리콘 성장막(23)을 형성시킨다. 이 때, 성장두께는 평면 MOS 캐패시터의 면적증가의 크기를 고려하여 결정하며, 또한 국소적인 STI 형성 넓이 미만으로 결정한다.Next, as shown in FIG. 2B, silicon growth film 23 is formed by selectively growing silicon only in a silicon region without an oxide film. At this time, the growth thickness is determined in consideration of the size of the area increase of the planar MOS capacitor, and is also determined to be less than the local STI formation area.
그 다음, 도 2c와 같이, 웰(Well) 형성 공정을 진행하기 위하여 먼저 형성되지 않아야할 지역을 포토 레지스트막(24)으로 덮은 후 이온 주입(25)을 수행한 후 상기 포토 레지스트막(24)을 제거함으로써 소자가 구현될 액티브 영역을 확보한다. 이 때, NMOS 트랜지스터의 경우는 보론(Boron)을 이용한 P 웰(Well)을, PMOS 트랜지스터의 경우는 인(Phosphorus) 및 비소(Arsenis)를 이용한 N 웰을 형성하게 된다.Next, as shown in FIG. 2C, in order to proceed with the well formation process, the photoresist layer 24 is covered with a photoresist layer 24, and then ion implantation 25 is performed, followed by the photoresist layer 24. By eliminating it, the active area in which the device is to be implemented is secured. At this time, in the case of an NMOS transistor, a P well using boron is formed, and in the case of a PMOS transistor, an N well using phosphorus and arsenic is formed.
그 다음, 도 2d와 같이, 상기 구조물 위에 게이트 산화막(26)과 폴리 실리콘막(27)을 성장 및 증착한 후 패턴을 형성한다. 이 때, 모스 트랜지스터의 게이트로서 이용할 부분과 평면 모스 캐패시터로 사용될 부분이 동시에 패터닝 될 수 있도록 한다.Next, as shown in FIG. 2D, the gate oxide layer 26 and the polysilicon layer 27 are grown and deposited on the structure, and then a pattern is formed. At this time, the portion to be used as the gate of the MOS transistor and the portion to be used as the planar MOS capacitor can be patterned at the same time.
이렇게 되면, 평면 MOS 캐패시터 부분의 경우 선택적 성장된 실리콘 표면의 구조적 모양에 의해서 선택적 성장된 실리콘 성장막(23)의 윗쪽면만 아니라 측면까지 상기 게이트 산화막(26)과 폴리 실리콘막(27)이 형성된다. 그러므로, 종래의 기술 방법으로 제조된 평면 모스 캐패시터 보다 높은 집적도를 가지며, 또한 넓은 캐패시터 면적을 가질 수 있어 캐패시터 용량이 늘어나게 된다.In this case, in the case of the planar MOS capacitor portion, the gate oxide layer 26 and the polysilicon layer 27 are formed not only on the upper side but also on the side surface of the selectively grown silicon growth layer 23 by the structural shape of the selectively grown silicon surface. . Therefore, it is possible to have a higher degree of integration than a planar MOS capacitor manufactured by the conventional method, and also to have a large capacitor area, thereby increasing the capacitor capacity.
게이트 도핑의 경우에는 후속 공정인 소스/드레인 접합층 형성 공정 진행시 동시에 도핑 되거나 추가적인 도핑 필요시 게이트 패터닝 전에 이온주입하는 경우도 있다.In the case of gate doping, doping may be performed simultaneously during the subsequent process of forming the source / drain junction layer, or ion implantation may be performed before gate patterning if additional doping is required.
그 다음, 도 2e와 같이, 게이트 패턴을 형성한 후 LDD(Lightly Doped Drain) 이온주입층(28)에 LDD 이온주입을 수행함으로써 소스/드레인 접합층 간의 흐르는 캐리어들의 전기장을 조절하게 된다. 이는 소자의 크기가 감소하나 그에 따라 소자의 동작전압이 작아지지 못하여 채널 드레인 쪽 일부분에 매우 높은 전기장(Electric Field)이 집중되는 현상 때문에 원치 않는 캐리어의 흐름이 형성되어 소자의 작동에 어려움을 갖게되는 현상(HCE)을 최소화 할 수 있다.Next, as shown in FIG. 2E, after the gate pattern is formed, LDD ion implantation is performed on the lightly doped drain (LDD) ion implantation layer 28 to control the electric field of carriers flowing between the source / drain junction layer. This is because the size of the device is reduced, but the operating voltage of the device is not reduced, so that a very high electric field is concentrated in a portion of the channel drain side, and thus an unwanted carrier flow is formed, which makes it difficult to operate the device. HCE can be minimized.
이 후 LDD 이온주입층(28) 형성으로 인해 채널의 길이가 작아지게 되어 문턱전압이 낮아지는 SCE(Short Channel Effect) 특성을 개선시키고자 틸트(tilt)를 주어 이온주입을 실시하여 LDD 이온주입층(28) 주변에 틸트 이온주입층(29)을 형성시킴으로써 SCE 현상을 완화시키게 된다.After the LDD ion implantation layer 28 is formed, the length of the channel is reduced and the LDD ion implantation layer is implanted by giving a tilt to improve the characteristics of the SCE (Short Channel Effect), which lowers the threshold voltage. (28) The SCE phenomenon is alleviated by forming the tilt ion implantation layer 29 around the periphery.
그 다음, 도 2f와 같이, 상기 게이트(27) 측벽에 버퍼 산화막(30)을 형성한다.Next, as shown in FIG. 2F, a buffer oxide layer 30 is formed on the sidewall of the gate 27.
그 다음, 상기 구조물 위에 질화막을 증착한 후 건식 식각하여 상기 버퍼 산화막(30) 위에 LDD 스페이서(31)를 형성한다.Next, a nitride film is deposited on the structure and then dry-etched to form the LDD spacers 31 on the buffer oxide film 30.
그 다음, 도 2g와 같이, 상기 구조물 위에 N+/P+ 이온주입(32) 공정을 진행하여 소스/드레인 접합층(33)을 형성한다.Next, as shown in FIG. 2G, a process of N + / P + ion implantation 32 is performed on the structure to form a source / drain junction layer 33.
그 다음, 어닐 공정을 실시하여 상기 게이트(27) 및 소스/드레인 접합층(33)에 고농도의 도펀트(dopant)가 존재할 수 있도록 한다.An annealing process is then performed to allow the presence of high concentrations of dopants in the gate 27 and the source / drain junction layer 33.
상기 게이트(27) 및 소스/드레인 접합층(33)은 이후 금속과 접촉함으로써 동작전압이 걸리며, 이로인해 캐리어들의 흐름을 선택적으로 조절하는 역할을 하게 된다. 그러나, 이 상태에서는 금속과의 접촉저항이 높기 때문에 이를 낮추기 위해 도 2h와 같이, 상기 게이트(27) 및 소스/드레인 접합층(33) 위에 실리사이드막(34)을 형성시키는 공정이 필요하다.The gate 27 and the source / drain junction layer 33 are then brought into contact with the metal to apply an operating voltage, thereby selectively controlling the flow of carriers. However, in this state, since the contact resistance with the metal is high, a process of forming the silicide layer 34 on the gate 27 and the source / drain junction layer 33 is needed to reduce the contact resistance with the metal.
이 공정은 도 2h와 같이, 상기 구조물 위에 실리사이드막을 형성하기 위한 코발트(Co) 및 캡핑(Capping) 물질인 TiN막(도시되지 않음)을 형성한 후 어닐 공정을 실시한다.As shown in FIG. 2H, a cobalt (Co) and a TiN film (not shown), which is a capping material, are formed on the structure to perform an annealing process.
그 다음, 캡핑 물질 및 반응하지 않은 코발트(Co)막을 제거하고 나면 폴리실리콘이 드러나 있는 게이트(27) 및 소스/드레인 접합층(33) 위에 코발트 실리사이드막(34)이 형성된다.Then, after removing the capping material and the unreacted cobalt (Co) film, a cobalt silicide film 34 is formed on the gate 27 and the source / drain junction layer 33 on which the polysilicon is exposed.
이상에서 설명한 바와 같이, 본 발명에 의한 반도체 소자의 제조 방법에 의하면, 먼저 선택적 성장법을 이용하여 실리콘을 성장시킨 후 평면 모스 캐패시터 및 소자를 구현시키는 공정을 진행하므로써, 웨이퍼 내의 집적도의 저하 없이도 선택적으로 성장된 실리콘의 옆면까지 평면 모스 캐패시터 영역으로 활용할 수 있어 면적 증가를 통한 캐패시터 용량을 증가시킬 수 있는 효과가 있다.As described above, according to the method of manufacturing a semiconductor device according to the present invention, by first growing the silicon using the selective growth method, and then proceeding to implement the planar MOS capacitor and the device, thereby selectively without deteriorating the density in the wafer As the planar MOS capacitor region can be used to the side of the grown silicon, the capacitor capacity can be increased by increasing the area.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020041276A KR100608324B1 (en) | 2002-07-15 | 2002-07-15 | Method of manufacture semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020041276A KR100608324B1 (en) | 2002-07-15 | 2002-07-15 | Method of manufacture semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040007987A true KR20040007987A (en) | 2004-01-28 |
| KR100608324B1 KR100608324B1 (en) | 2006-08-04 |
Family
ID=37317255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020041276A KR100608324B1 (en) | 2002-07-15 | 2002-07-15 | Method of manufacture semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100608324B1 (en) |
-
2002
- 2002-07-15 KR KR1020020041276A patent/KR100608324B1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| KR100608324B1 (en) | 2006-08-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100621546B1 (en) | Method and Apparatus For Making MOS Transistors With Elevated Source/Drain | |
| US6566734B2 (en) | Semiconductor device | |
| KR100791441B1 (en) | Structure and method of making strained semiconductor cmos transistors having lattice-mismatched source and drain regions | |
| US6121100A (en) | Method of fabricating a MOS transistor with a raised source/drain extension | |
| KR101124657B1 (en) | Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device | |
| US6812086B2 (en) | Method of making a semiconductor transistor | |
| KR101811796B1 (en) | Semiconductor devices including source/drain regions with abrupt junction profiles and methods of fabricating the same | |
| KR20020002093A (en) | Method for manufacturing semiconductor divice using damascene process | |
| KR20070052329A (en) | Metal gate transistors with epitaxial source and drain regions | |
| US20080194070A1 (en) | Metal-oxide-semiconductor transistor device, manufacturing method thereof, and method of improving drain current thereof | |
| JPS63141373A (en) | Mos field effect transistor structure, integrated circuit and manufacture of the same | |
| US6696729B2 (en) | Semiconductor device having diffusion regions with different junction depths | |
| US7091072B2 (en) | Semiconductor device and method for manufacturing the same | |
| KR100843879B1 (en) | Semiconductor device and method for fabricating the same | |
| US7118973B1 (en) | Method of forming a transistor with a channel region in a layer of composite material | |
| US20020090787A1 (en) | Self-aligned elevated transistor | |
| JP3524461B2 (en) | Process for fabricating a dual gate structure for a CMOS device | |
| KR100840684B1 (en) | method for manufacturing of semiconductor device | |
| CN113506747A (en) | Doping segregation Schottky manufacturing method for reducing FinFET contact resistance | |
| KR100200757B1 (en) | Semiconductor device and manufacturing method thereof | |
| KR100608324B1 (en) | Method of manufacture semiconductor device | |
| US7098095B1 (en) | Method of forming a MOS transistor with a layer of silicon germanium carbon | |
| KR100461156B1 (en) | Method of manufacturing SiGe BICMOS devices using selective epitaxial growth | |
| KR101068135B1 (en) | Method for fabricating semiconductor device | |
| KR100705233B1 (en) | Method of manufacturing a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| N231 | Notification of change of applicant | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20130620 Year of fee payment: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20140618 Year of fee payment: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20150617 Year of fee payment: 10 |
|
| FPAY | Annual fee payment |
Payment date: 20160620 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20170626 Year of fee payment: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20180618 Year of fee payment: 13 |
|
| FPAY | Annual fee payment |
Payment date: 20190619 Year of fee payment: 14 |