KR20040007801A - method for forming contact hole - Google Patents

method for forming contact hole Download PDF

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Publication number
KR20040007801A
KR20040007801A KR1020020040386A KR20020040386A KR20040007801A KR 20040007801 A KR20040007801 A KR 20040007801A KR 1020020040386 A KR1020020040386 A KR 1020020040386A KR 20020040386 A KR20020040386 A KR 20020040386A KR 20040007801 A KR20040007801 A KR 20040007801A
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South Korea
Prior art keywords
forming
line
contact
shaped contact
photoresist pattern
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KR1020020040386A
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Korean (ko)
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박성찬
이진욱
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주식회사 하이닉스반도체
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Priority to KR1020020040386A priority Critical patent/KR20040007801A/en
Publication of KR20040007801A publication Critical patent/KR20040007801A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a contact is provided to prevent the generation of bridges in a process for forming a conductive plug by using a line-shaped contact instead of a hole-shaped contact. CONSTITUTION: A bit line(205) is formed on a semiconductor substrate(200). An insulating spacer(206) is formed on a side of the bit line(205). A photoresist pattern is formed on the entire surface of the resultant structure. A line-shaped contact is formed by performing an etch process using the photoresist pattern. The photoresist pattern is removed. A conductive layer is formed on the entire surface of the semiconductor substrate(200). A conductive plug(220) is formed by performing a CMP process for the conductive layer.

Description

콘택 형성 방법{method for forming contact hole}Method for forming contact hole

본 발명은 반도체소자의 제조 방법에 관한 것으로, 보다 상세하게는 반도체 소자의 제조 공정 중 콘택 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a contact forming method during a manufacturing process of a semiconductor device.

반도체 소자의 콘택 형성 공정에 있어서, 홀 형상의 콘택은 콘택의 위치가 원하는 위치에서 벗어나게 되면 콘택의 면적이 작아지거나 콘택이 형성되지 않는 등의 문제가 있으며, 이러한 문제는 디바이스가 고집적화되면서 점점 더 심각해진다.In the process of forming a contact of a semiconductor device, a hole-shaped contact has a problem such that the contact area becomes smaller or the contact is not formed when the contact position is out of a desired position, and this problem becomes more serious as the device becomes highly integrated. Become.

도 1은 종래 기술에 따른 홀 형상의 콘택의 평면도이다. 또한, 도 2a 내지 도 2e는 종래 기술에 따른 콘택 형성 방법을 설명하기 위한 공정단면도이다.1 is a plan view of a hole-shaped contact according to the prior art. 2A to 2E are cross-sectional views illustrating a method for forming a contact according to the prior art.

종래 기술에 따른 콘택(20)은, 도 1에 도시된 바와 같이, 절연막(18)에 홀 형상을 가지도록 형성되며, 상기 홀형상의 콘택(20)은 도전플러그(23)에 의해 매립된다.The contact 20 according to the related art is formed to have a hole shape in the insulating film 18, as shown in FIG. 1, and the hole-shaped contact 20 is filled by the conductive plug 23.

종래 기술에 따른 콘택 형성 방법을 알아보면, 도 2a에 도시된 바와 같이, 먼저, 반도체기판(10) 상에 제 1도전막(12) 및 식각방지막(14)을 차례로 형성한 후, 식각방지막(14) 상에 감광막을 도포하고 노광 및 현상하여 비트라인영역(미도시)을 노출시키는 제 1 감광막 패턴(50)을 형성한다.Referring to the contact forming method according to the prior art, as shown in FIG. 2A, first, the first conductive film 12 and the etch stop layer 14 are sequentially formed on the semiconductor substrate 10, and then the etch stop layer ( The first photoresist layer pattern 50 may be formed by applying a photoresist layer on the substrate 14 and exposing and developing the photoresist layer to expose the bit line region (not shown).

이어, 도 2b에 도시된 바와 같이, 상기 제 1감광막 패턴을 마스크로 하고 식각방지막 및 제 1도전막을 식각하여 비트라인(15)을 형성한다. 그런 다음, 제 1감광막 패턴을 제거하고 나서, 비트라인(15)을 포함한 기판 전면에 실리콘 질화막을 증착및 에치백 공정을 진행하여 비트라인(15) 측면에 절연 스페이서(16)를 형성한다.Subsequently, as shown in FIG. 2B, the first photoresist pattern is used as a mask, and the etch stop layer and the first conductive layer are etched to form a bit line 15. Then, after removing the first photoresist pattern, the silicon nitride film is deposited and etched back on the entire surface of the substrate including the bit line 15 to form an insulating spacer 16 on the side of the bit line 15.

이 후, 도 2c에 도시된 바와 같이, 상기 결과물 전면에 절연막(18)을 형성하고 나서, 상기 절연막(18) 상에 홀형상의 콘택영역(미도시)을 노출시키는 제 2감광막 패턴(52)을 형성한다.Thereafter, as shown in FIG. 2C, after forming the insulating film 18 on the entire surface of the resultant, the second photoresist film pattern 52 exposing a hole-shaped contact region (not shown) on the insulating film 18. To form.

이어, 도 2d에 도시된 바와 같이, 제 2감광막 패턴을 마스크로 하고 절연막을 식각하여 콘택(20)을 형성한다. 그런 다음, 상기 콘택(20)을 포함한 절연막(18) 전면에 제 2도전막(22)을 형성한다. 상기 제 2도전막(22)으로는 금속막 및 다결정 실리콘막 중 어느 하나를 사용한다.Next, as shown in FIG. 2D, the contact 20 is formed by etching the insulating film using the second photoresist pattern as a mask. Then, the second conductive film 22 is formed on the entire surface of the insulating film 18 including the contact 20. As the second conductive film 22, any one of a metal film and a polycrystalline silicon film is used.

이 후, 도 2e에 도시된 바와 같이, 상기 제 2도전막을 씨엠피(CMP:Chemical Mechnical Polishing)하여 콘택(20)을 매립시키는 도전플러그(23)를 형성한다. 이때, 도전막 식각 공정에서 상기 씨엠피 공정은 고가의 씨엠피 장비가 소모되므로 씨엠피 공정보다 비용이 저렴한 에치백 공정으로 대체할 경우, 상기 에치백 공정으로는 콘택을 분리하기 위하여 절연막 및 제 2도전막을 동시에 원하는 위치까지 식각하는 것이 어렵기 때문에 불가능하다.Thereafter, as illustrated in FIG. 2E, the second conductive film is CMP (Chemical Mechnical Polishing) to form a conductive plug 23 for filling the contact 20. In this case, since the CMP process consumes expensive CMP equipment in the conductive film etching process, when the etchback process is cheaper than the CMP process, the insulating film and the second etch back process may be used to separate the contact. This is impossible because it is difficult to simultaneously etch the conductive film to a desired position.

도 3은 종래 기술에 따른 문제점을 보이기 위한 공정단면도이다.3 is a process cross-sectional view for showing a problem according to the prior art.

그러나, 종래 기술에 따른 홀 형상의 콘택 형성 공정은, 도 3에 도시된 바와 같이, 콘택 위치가 조금이라도 미스얼라인(misalign)된 경우 비트라인이 노출되어 이 후의 도전플러그 형성 시 브릿지(bridge)가 발생되었다.However, in the hole-shaped contact forming process according to the related art, as shown in FIG. 3, when the contact position is at least misaligned, the bit line is exposed so that a bridge is formed during the subsequent formation of the conductive plug. Was generated.

또한, 종래 기술에 따른 홀 형상의 콘택에 씨엠피 공정을 적용하여 도전플러그를 분리함으로써, 고가의 씨엠피 장비 및 그에 따른 소모품이 필요하게 되어 생산 비용이 증가된 문제점이 있었다.In addition, by separating the conductive plug by applying the CMP process to the hole-shaped contact according to the prior art, expensive CMP equipment and consumables are required, there is a problem that the production cost is increased.

이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 홀 형상의 콘택 대신 라인 형상의 콘택을 적용함으로서, 콘택 위치가 조금 미스얼라인된 경우라도 이 후의 도전플러그 형성 시 브릿지가 발생되는 것을 방지할 수 있는 콘택 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and by applying a line-shaped contact instead of a hole-shaped contact, even when the contact position is slightly misaligned, the bridge is generated when the conductive plug is formed later. It is an object of the present invention to provide a method for forming a contact that can be prevented.

본 발명의 다른 목적은 고가의 장비가 필요한 씨엠피 공정 대신 저렴한 에치백 공정을 적용하여 도전플러그를 분리할 수 있는 콘택 형성 방법을 제공하려는 것이다.Another object of the present invention is to provide a method for forming a contact that can separate a conductive plug by applying an inexpensive etchback process instead of a CMP process requiring expensive equipment.

도 1은 종래 기술에 따른 홀 형상의 콘택의 평면도.1 is a plan view of a hole-shaped contact according to the prior art.

도 2a 내지 도 2e는 종래 기술에 따른 콘택 형성 방법을 설명하기 위한 공정단면도.2A to 2E are cross-sectional views illustrating a method for forming a contact according to the prior art.

도 3은 종래 기술에 따른 문제점을 보이기 위한 공정단면도.Figure 3 is a process cross-sectional view for showing a problem according to the prior art.

도 4는 본 발명에 따른 콘택의 평면도.4 is a plan view of a contact according to the invention.

도 5a 내지 도 5e는 본 발명의 제 1실시예에 따른 콘택 형성 방법을 설명하기 위한 공정단면도.5A to 5E are cross-sectional views illustrating a method for forming a contact according to a first embodiment of the present invention.

도 6은 도 5c의 사시도.6 is a perspective view of FIG. 5C.

도 7은 도 5d의 사시도FIG. 7 is a perspective view of FIG. 5D

도 8은 도 5e의 사시도.8 is a perspective view of FIG. 5E.

도 9a 내지 도 9d는 본 발명의 제 2실시예에 따른 콘택 형성 방법을 설명하기 위한 공정단면도.9A to 9D are cross-sectional views illustrating a method for forming a contact according to a second embodiment of the present invention.

도 10은 도 9b의 사시도.10 is a perspective view of FIG. 9B.

도 11은 도 9d의 사시도.FIG. 11 is a perspective view of FIG. 9D; FIG.

상기 목적을 달성하기 위한 본 발명의 제 1실시예에 따른 콘택 형성 방법은, 반도체기판 상에 비트라인 및 비트라인 측면에 절연 스페이서를 각각 형성하는 단계와, 결과물 전면에 절연막 및 라인 형상의 콘택영역을 덮는 감광막 패턴을 차례로 형성하는 단계와, 감광막 패턴을 마스크로 하고 절연막을 식각하여 라인 형상의 콘택을 형성하는 단계와, 감광막 패턴을 제거하는 단계와, 라인 형상의 콘택을 포함한 기판 전면에 도전막을 형성하는 단계와, 도전막을 씨엠피하여 라인 형상의 콘택을 분리시키는 도전플러그를 형성하는 단계를 포함한 것을 특징으로 한다.According to a first aspect of the present invention, there is provided a contact forming method comprising: forming insulating spacers on a bit line and a side of a bit line on a semiconductor substrate; Forming a photoresist pattern covering the photoresist, forming a line contact by etching the insulating film using the photoresist pattern as a mask, removing the photoresist pattern, and forming a conductive film on the entire surface of the substrate including the line contact. And forming a conductive plug separating the line-shaped contact by CMP of the conductive film.

또한, 본 발명의 제 2실시예에 따른 콘택 형성 방법은, 반도체기판 상에 비트라인 및 비트라인 측면에 절연 스페이서를 각각 형성하는 단계와, 결과물 전면에 절연막을 형성하는 단계와, 절연막을 에치백하여 절연 스페이서를 포함한 비트라인상부를 노출시키는 단계와, 상기 구조의 절연막 상에 라인 형상의 콘택영역을 덮는 감광막 패턴을 형성하는 단계와, 감광막 패턴을 마스크로 하고 절연막을 식각하여 라인 형상의 콘택을 형성하는 단계와, 감광막 패턴을 제거하는 단계와, 라인 형상의 콘택을 포함한 기판 전면에 도전막을 형성하는 단계와, 도전막을 에치백하여 라인 형상의 콘택을 분리시키는 도전플러그를 형성하는 단계를 포함한 것을 특징으로 한다.In addition, the contact forming method according to the second embodiment of the present invention comprises the steps of forming an insulating spacer on the bit line and the side of the bit line on the semiconductor substrate, forming an insulating film on the entire surface of the resultant, and etching back the insulating film Exposing an upper portion of the bit line including the insulating spacers, forming a photoresist pattern covering the line-shaped contact region on the insulating film of the structure, and etching the insulating film using the photoresist pattern as a mask to form a line-shaped contact. Forming a film, removing the photoresist pattern, forming a conductive film on the entire surface of the substrate including the line-shaped contacts, and forming a conductive plug to etch back the conductive film to separate the line-shaped contacts. It features.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 4는 본 발명에 따른 라인 형상의 콘택의 평면도이다.4 is a plan view of a line-shaped contact according to the present invention.

본 발명에 따른 콘택(120)은, 도 4에 도시된 바와 같이, 라인 형상을 가지도록 형성되며, 상기 라인 형상의 콘택(120)은 도전플러그(123)에 의해 매립된다.As shown in FIG. 4, the contact 120 according to the present invention is formed to have a line shape, and the line shape contact 120 is filled by the conductive plug 123.

도 5a 내지 도 5e는 본 발명의 제 1실시예에 따른 콘택 형성 방법을 설명하기 위한 공정단면도이다. 또한, 도 6은 도 5c의 사시도이고, 도 7은 도 5d의 사시도이며, 도 8은 도 5e의 시도이다.5A to 5E are cross-sectional views illustrating a method for forming a contact according to a first embodiment of the present invention. 6 is a perspective view of FIG. 5C, FIG. 7 is a perspective view of FIG. 5D, and FIG. 8 is an attempt of FIG. 5E.

본 발명의 제 1실시예에 따른 콘택 형성 방법은, 도 5a에 도시된 바와 같이, 먼저, 반도체기판(100) 상에 제 1도전막(102) 및 식각방지막(104)을 차례로 형성한 다음, 상기 식각방지막(104) 상에 감광막을 도포하고 노광 및 현상하여 비트라인영역(미도시)을 노출시키는 제 1 감광막 패턴(150)을 형성한다.In the method for forming a contact according to the first embodiment of the present invention, as shown in FIG. 5A, first, a first conductive layer 102 and an etch stop layer 104 are sequentially formed on the semiconductor substrate 100. A first photoresist layer pattern 150 is formed on the etch stop layer 104 to expose a bit line region (not shown) by coating, exposing and developing the photoresist layer.

이어, 도 5b에 도시된 바와 같이, 상기 제 1감광막 패턴을 마스크로 하고 식각방지막 및 제 1도전막을 식각하여 비트라인(105)을 형성한다. 그런 다음, 제 1감광막 패턴을 제거하고 나서, 비트라인(105)을 포함한 기판 전면에 실리콘 질화막을 증착및 에치백 공정을 진행하여 비트라인(105) 측면에 절연 스페이서(106)를 형성한다.Subsequently, as illustrated in FIG. 5B, the bit line 105 is formed by etching the etch stop layer and the first conductive layer using the first photoresist pattern as a mask. Then, after removing the first photoresist pattern, the silicon nitride film is deposited and etched back on the entire surface of the substrate including the bit line 105 to form an insulating spacer 106 on the side of the bit line 105.

이 후, 도 5c 및 도 6에 도시된 바와 같이, 상기 결과물 전면에 절연막(108)을 형성하고 나서, 상기 절연막(108) 상에 라인 형상의 콘택영역(미도시)을 노출시키는 제 2감광막 패턴(152)을 형성한다.Thereafter, as shown in FIGS. 5C and 6, after forming the insulating film 108 on the entire surface of the resultant, the second photoresist film pattern exposing a line-shaped contact region (not shown) on the insulating film 108. 152 is formed.

이어, 도 5d 및 도 7에 도시된 바와 같이, 상기 제 2감광막 패턴을 마스크로 하고 상기 절연막(108)을 식각하여 라인 형상의 콘택(109)을 형성한다. 이때, 라인 형상의 콘택(109)에 의해, 도 7에 도시된 바와 같이, 절연 스페이서(106)을 포함한 비트라인(105) 사이의 기판이 노출된다.Subsequently, as illustrated in FIGS. 5D and 7, the second photoresist pattern is used as a mask, and the insulating layer 108 is etched to form a line contact 109. In this case, as shown in FIG. 7, the substrate between the bit lines 105 including the insulating spacer 106 is exposed by the line-shaped contact 109.

그런 다음, 도 5e 및 도 8에 도시된 바와 같이, 상기 라인 형상의 콘택(109)를 포함한 기판 전면에 금속막 또는 다결정 실리콘막 중 어느 하나를 이용하여 제 2도전막(미도시)을 형성한 후, 상기 제 2도전막을 씨엠피하여 각각의 라인 형상의 콘택(109)을 분리시키는 도전플러그(120)을 형성한다. 이때, 상기 각각의 라인 형상의 콘택(109)의 분리를 위해, 절연막과 제 2도전막을 원하는 두께까지 연마해야 한다.5E and 8, the second conductive film (not shown) is formed on the entire surface of the substrate including the line-shaped contact 109 using either a metal film or a polycrystalline silicon film. Thereafter, the second conductive film is CMP to form a conductive plug 120 that separates each of the line-shaped contacts 109. At this time, in order to separate the respective line-shaped contacts 109, the insulating film and the second conductive film must be polished to a desired thickness.

본 발명의 제 1실시에서는 홀 형상의 콘택 대신 라인 형상의 콘택을 적용함으로서, 콘택 식각 공정에서 약간의 미스얼라인이 발생될 경우라도 이 후의 도전플러그 형성 시 브릿지가 발생되는 것이 방지된다.In the first embodiment of the present invention, by applying a line-shaped contact instead of a hole-shaped contact, even when a slight misalignment occurs in the contact etching process, the bridge is prevented from being generated during the subsequent formation of the conductive plug.

도 9a 내지 도 9d는 본 발명의 제 2실시예에 따른 콘택 형성 방법을 설명하기 위한 공정단면도이다. 또한, 도 10은 도 9b의 사시도이고, 도 11은 도 9d의 사시도이다.9A to 9D are cross-sectional views illustrating a method for forming a contact according to a second embodiment of the present invention. 10 is a perspective view of FIG. 9B, and FIG. 11 is a perspective view of FIG. 9D.

본 발명의 제 2실시예에 따른 콘택 형성 방법은, 도 9a에 도시된 바와 같이, 반도체기판(200) 상에 비트라인(205) 및 그 측면에 절연 스페이서(206)를 형성한다. 이어, 상기 절연 스페이서(206), 비트라인(205)을 포함한 기판 전면에 절연막(208)을 형성하고 나서, 상기 절연막(208)을 에치백(etch back)하여 상기 절연 스페이서(206)를 포함한 비트라인(205) 상부를 노출시킨다.In the contact forming method according to the second embodiment of the present invention, as shown in FIG. 9A, the bit line 205 and the insulating spacer 206 are formed on the side surface of the semiconductor substrate 200. Subsequently, after the insulating film 208 is formed on the entire surface of the substrate including the insulating spacer 206 and the bit line 205, the insulating film 208 is etched back to form a bit including the insulating spacer 206. Expose the top of line 205.

그런 다음, 도 9b 및 도 10에 도시된 바와 같이, 상기 결과물 상에 라인 형상의 콘택영역(미도시)을 노출시키는 감광막 패턴(252)을 형성한다.9B and 10, a photoresist pattern 252 is formed on the resultant to expose a line-shaped contact region (not shown).

이후, 도 9c에 도시된 바와 같이, 상기 제 2감광막 패턴을 마스크로 하고 상기 절연막(208)을 식각하여 라인 형상의 콘택(209)을 형성한다. 이때, 라인 형상의 콘택(209)에 의해 절연 스페이서(206)을 포함한 비트라인(205) 사이의 기판이 노출된다.Thereafter, as shown in FIG. 9C, the second photoresist pattern is used as a mask, and the insulating layer 208 is etched to form a line contact 209. At this time, the substrate between the bit lines 205 including the insulating spacer 206 is exposed by the line-shaped contact 209.

이어, 도 9d에 도시된 바와 같이, 상기 라인 형상의 콘택(209)를 포함한 기판 전면에 금속막 또는 다결정 실리콘막 중 어느 하나를 이용하여 도전막(미도시)을 형성한 후, 상기 도전막을 에치백하여 각각의 라인 형상의 콘택(209)을 분리시키는 도전플러그(220)을 형성한다.Subsequently, as shown in FIG. 9D, a conductive film (not shown) is formed on the entire surface of the substrate including the line-shaped contact 209 using either a metal film or a polycrystalline silicon film. The conductive plug 220 is formed to separate the respective line-shaped contacts 209.

본 발명의 제 2실시에서는 홀 형상의 콘택 대신 라인 형상의 콘택을 적용함으로서, 콘택 식각 공정에서 약간의 미스얼라인이 발생될 경우라도 이 후의 도전플러그 형성 시 브릿지가 발생되는 것이 방지되며, 또한, 고가의 씨엠피 공정 대신저가의 에치백 공정을 적용함으로서, 공정 원가를 낮출 수 있다.In the second embodiment of the present invention, by applying a line-shaped contact instead of a hole-shaped contact, even if a slight misalignment occurs in the contact etching process, the bridge is prevented from being generated during the subsequent formation of the conductive plug. By applying a low-cost etch back process instead of an expensive CMP process, process costs can be lowered.

이상에서와 같이, 본 발명은 홀 형상의 콘택 대신 라인 형상의 콘택을 적용함으로서, 콘택 식각 공정에서 약간의 미스얼라인이 발생될 경우라도 이 후의 도전플러그 형성 시 브릿지가 발생되는 것이 방지된다.As described above, the present invention applies a line-shaped contact instead of a hole-shaped contact, so that even if a slight misalignment occurs in the contact etching process, the bridge is prevented from being generated during the subsequent formation of the conductive plug.

또한, 본 발명은 고가의 씨엠피 공정 대신 저가의 에치백 공정을 적용함으로서, 공정 원가를 낮출 수 있다.In addition, the present invention can reduce the process cost by applying a low-cost etch back process instead of the expensive CMP process.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (2)

반도체기판 상에 비트라인 및 상기 비트라인 측면에 절연 스페이서를 각각 형성하는 단계와,Forming an insulating spacer on each side of the bit line and the bit line on the semiconductor substrate; 상기 결과물 전면에 절연막 및 라인 형상의 콘택영역을 덮는 감광막 패턴을 차례로 형성하는 단계와,Sequentially forming a photoresist pattern covering the insulating layer and the line-shaped contact region on the entire surface of the resultant; 상기 감광막 패턴을 마스크로 하고 상기 절연막을 식각하여 라인 형상의 콘택을 형성하는 단계와,Forming a line-shaped contact by etching the insulating layer using the photoresist pattern as a mask; 상기 감광막 패턴을 제거하는 단계와,Removing the photoresist pattern; 상기 라인 형상의 콘택을 포함한 기판 전면에 도전막을 형성하는 단계와,Forming a conductive film on the entire surface of the substrate including the line-shaped contact; 상기 도전막을 씨엠피하여 상기 라인 형상의 콘택을 분리시키는 도전플러그를 형성하는 단계를 포함한 것을 특징으로 하는 콘택 형성 방법.And forming a conductive plug separating the line-shaped contact by CMP of the conductive film. 반도체기판 상에 비트라인 및 상기 비트라인 측면에 절연 스페이서를 각각 형성하는 단계와,Forming an insulating spacer on each side of the bit line and the bit line on the semiconductor substrate; 상기 결과물 전면에 절연막을 형성하는 단계와,Forming an insulating film on the entire surface of the resultant, 상기 절연막을 에치백하여 상기 절연 스페이서를 포함한 비트라인 상부를 노출시키는 단계와,Etching back the insulating film to expose an upper portion of the bit line including the insulating spacer; 상기 구조의 절연막 상에 라인 형상의 콘택영역을 덮는 감광막 패턴을 형성하는 단계와,Forming a photoresist film pattern covering a line-shaped contact region on the insulating film of the structure; 상기 감광막 패턴을 마스크로 하고 상기 절연막을 식각하여 라인 형상의 콘택을 형성하는 단계와,Forming a line-shaped contact by etching the insulating layer using the photoresist pattern as a mask; 상기 감광막 패턴을 제거하는 단계와,Removing the photoresist pattern; 상기 라인 형상의 콘택을 포함한 기판 전면에 도전막을 형성하는 단계와,Forming a conductive film on the entire surface of the substrate including the line-shaped contact; 상기 도전막을 에치백하여 상기 라인 형상의 콘택을 분리시키는 도전플러그를 형성하는 단계를 포함한 것을 특징으로 하는 콘택 형성 방법.And forming a conductive plug to etch back the conductive film to separate the line-shaped contact.
KR1020020040386A 2002-07-11 2002-07-11 method for forming contact hole KR20040007801A (en)

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