KR20040006767A - Semiconductor memory device for performing partial array self refresh - Google Patents

Abstract

PURPOSE: A semiconductor memory device performing a partial array self refresh is provided to reduce a refresh current. CONSTITUTION: A plurality of latch units(LAT0-LAT15) divide a memory area into a plurality of parts using one or more than one upper address bit of a memory address, and determine whether to refresh each part by being matched to each part. A decoder(11) outputs a latch selection signal selecting a corresponding latch unit by decoding the upper address bit. An initialization unit(12) outputs an initialization signal resetting the above latch unit using one or more than one lower address bit of the memory address. A command analyser(13) generates a corresponding operation signal by analyzing an external command inputted from an external command pin. And a command pass unit(14) determines a refresh operation of a corresponding area according to a state of the latch unit corresponding to the upper address bit.

Description

Semiconductor memory device for performing partial array self refresh}

The present invention relates to a semiconductor memory device that performs a self refresh function, and more particularly, to perform a partial array self refresh operation without an instruction from an external CPU or chipset, so that the semiconductor memory device can operate at low power. A semiconductor memory device that performs a function.

In general, as the use of mobile applications increases, the need to use low power memory devices increases.

1 is a conceptual diagram illustrating a specification of an extended mode register set (EMRS) of a low power 128M DRAM according to the prior art.

To use the Partial Array Self Refresh (PASR) feature, you must select the memory area that you want to be refreshed with at least one EMRS instruction before starting the self refresh. That is, the memory area should be selected by the combination of A <0: 2> among the EMRS commands.

In addition, since the selection of the partial array area is classified on the assumption that valid data is always stored sequentially from the lower address to the upper address, the lower address area is always included in the self refresh area.

2 is a block diagram showing a case in which valid data exists only in the upper address area 1.

Therefore, there is a problem that the entire memory should be selected as the self refresh area even when there is valid data only in the highest address (1).

In other words, in the case of the PASR function of EMRS, the refresh areas that can be selected are determined as 1/16, 1/8, 1/4, 1/2, or 1 part of the entire memory based on the lowest address. If valid data exists only in the corresponding memory cell array, the entire address must be selected as the refresh area.

An object of the present invention for solving the above problems is to reduce the refresh current by dividing the memory into several parts by using an upper address, and then performing only refreshing of each used part.

1 is a conceptual diagram showing specifications of an extended mode register set (EMRS) of a low power 128M DRAM according to the prior art;

Fig. 2 is a block diagram showing a case in which valid data exists only in an upper address area.

3 is a block diagram illustrating a DRAM performing a partial array self refresh function in accordance with the present invention.

4 is an operation timing diagram illustrating an operation of initializing the latch unit illustrated in FIG. 3.

FIG. 5 is a timing diagram illustrating an operation when an active command is input to the DRAM shown in FIG. 3. FIG.

6A and 6B are operation timing diagrams when a refresh operation is performed on the DRAM shown in FIG.

A semiconductor memory device performing the partial array self refresh function of the present invention for achieving the above object,

A plurality of latch means for dividing the memory area into a plurality of parts by using one or more upper address bits of the memory address and matching each part to determine whether to refresh each part;

Decoding means for decoding the upper address bits and outputting a latch selection signal for selecting the corresponding latch means;

Initialization means for outputting an initialization signal for resetting the latch means by using one or more lower address bits of the memory address;

Command interpreting means for interpreting an external command input from an external command pin and generating a corresponding operation signal; And

And command passing means for determining a refresh operation of the corresponding area according to the state of the latch means corresponding to the upper address bit.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a DRAM performing a partial array self refresh function according to the present invention. Here, 128M DRAM will be described as an example.

The DRAM includes a decoder section 11, an initialization section 12, an instruction decoding section 13, a latch section LAT0 to LAT15, and an instruction passing section 14.

The decoder section 11 decodes the upper address bits BA <0: 1>, A <10:11> and outputs a latch select signal ASEL <0:15> for selecting the corresponding latch section.

The initialization unit 12 outputs an initialization signal INIT <0:15> for resetting the latch units LAT0 to LAT15 when the power-up signal PWRUP is input to initialize the power supply and when an external EMRS command is input.

The command decoding unit 13 analyzes the external control signals RASB, CASB, and WEB input from the external command pin to generate the active signal ACT or the refresh signal REF.

The latch sections LAT0 to LAT15 divide the memory area into 16 parts using four high order bits BA <0: 1> and A <10:11> of the memory address, and match each part.

The command passing section 14 enables the final refresh signal REFD of the corresponding area by using the signals LO <0:15> and upper addresses BA <0: 1>, A <10:11> stored in the latch sections LAT0 to LAT15. Or disable the last refresh signal REFD in the region.

4 is an operation timing diagram illustrating an operation of initializing the latch unit illustrated in FIG. 3.

First, when the power supply voltage VDD is input and reaches a predetermined level, the power-up signal PWRUP generates a high pulse.

The high pulse of the power-up signal PWRUP causes all of the initialization addresses INIT <0:15> to generate a high pulse to initialize all the latch sections LAT0 to LAT15.

On the other hand, if the EMRS command is input externally to change the self refresh area while the semiconductor memory device is operating, the latch unit corresponding to the PASR area is decoded to decode the lower address A <0: 2> to initialize the signal INIT <0:15>. Initialize using. Here, when the lower address A <0: 2> is (101) ₂ , INIT <2: among the initialization signals INIT <0:15> according to the EMRS instruction that only the 1/2 bank performs self refresh in the initialization unit 12. 15> becomes the high level, and the latch parts LAT2 to LAT15 to which the high level initialization signals INIT <2:15> have been applied among the latch parts LAT0 to LAT15 are initialized, and self-refresh is not performed in the banks that do not correspond to the PASR area. Do not.

Further, among the initialization signals INIT <0:15>, the initialization signal INIT <0: 1> is at a low level, and the latch parts LAT0 to LAT1 to which the low level initialization signals INIT <0: 1> are applied among the latch parts LAT0 to LAT15. Since does not perform a reset, it performs a self refresh for the bank corresponding to the PASR area.

FIG. 5 is a timing diagram illustrating an operation when an active command is input to the DRAM illustrated in FIG. 3.

When an active command is input from the outside, the command decoding unit 13 generates an active signal ACT having a high pulse.

At this time, the decoder unit 11 decodes the upper addresses BA <0: 1> and A <10:11> to generate the latch select signals ASEL <0:15>.

Therefore, the latch portion selected by the active signal ACT and the latch select signals ASEL <0:15> is set.

For example, if the upper addresses BA <0: 1> and A <10:11> are both low level, that is, BA <0: 1> is (00) ₂ and A <10:11> is (00). ₂ ), the decoder 11 enables only ASEL <0> to a high level so that the corresponding latch portion LAT <0> is selected and set by the active signal ACT.

FIG. 6A is an operation timing diagram when a refresh operation is performed in the DRAM shown in FIG. 3. Here, when the upper addresses BA <0: 1> and A <10:11> are both low level, that is, BA <0: 1> is (00) ₂ and A <10:11> is (00) ₂ Is an operation timing diagram when.

First, when an auto refresh command AREF (or a self refresh command) is input from the outside, the instruction decoding unit 13 generates a refresh signal REF having a high pulse.

The level of the final refresh signal REFD is determined according to the set or reset state of the latch portion selected by the upper addresses BA <0: 1> and A <10:11> which select the address area to be refreshed.

In this case, since the upper addresses BA <0: 1> and A <10:11> are both at the low level, the latch part LAT <0> is selected, where the latch part LAT <0> is previously set by the active signal ACT. Since the command passage section 14 passes the high pulse of the refresh signal REF, the final refresh signal REFD is output as a signal having a high pulse.

FIG. 6B is an operation timing diagram when a refresh operation is performed in the DRAM shown in FIG. 3. Here, when the upper addresses BA <0: 1> and A <10:11> are both at a high level, that is, BA <0: 1> is (11) ₂ and A <10:11> is (11) ₂ Is an operation timing diagram when.

First, when an auto refresh command AREF (or a self refresh command) is input from the outside, the instruction decoding unit 13 generates a refresh signal REF having a high pulse.

The level of the final refresh signal REFD is determined according to the set or reset state of the latch portion selected by the upper addresses BA <0: 1> and A <10:11> which select the address area to be refreshed.

In this case, since the upper addresses BA <0: 1> and A <10:11> are both at a high level, the latch part LAT <15> is selected, and the latch part LAT <15> has been previously reset by the active signal ACT. Therefore, the command passing section 13 blocks the high pulse of the refresh signal REF so that the final refresh signal REFD maintains a low level.

Therefore, since the address area corresponding to the reset latch portion 15 is not refreshed, the auto refresh current (or self refresh current) is reduced.

As described above, since the semiconductor memory device according to the present invention is to use a PASR function applicable to a low power DRAM to be used in a low power device such as a PDA and a mobile phone without an external EMRS command, the operation system of the low power device is low power. Even if the DRAM does not recognize the PASR function, the DRAM itself implements the PASR, which reduces the refresh current to reduce the current consumption. That is, the DRAM of the present invention can reduce the refresh current because the memory can be divided into several parts and only the parts used in each can be refreshed.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (4)

A plurality of latch means for dividing the memory area into a plurality of parts by using one or more upper address bits of the memory address and matching each part to determine whether to refresh each part; Decoding means for decoding the upper address bits and outputting a latch selection signal for selecting the corresponding latch means; Initialization means for outputting an initialization signal for resetting the latch means by using one or more lower address bits of the memory address; Command interpreting means for interpreting an external command input from an external command pin and generating a corresponding operation signal; And And a command passing means for determining a refresh operation of a corresponding area according to a state of the latch means corresponding to the upper address bit. The method of claim 1, The initialization means, When the power supply voltage is applied, a power-up signal for generating a high pulse is inputted, and all the latch means are reset when the power is initialized. And resetting only the latch means corresponding to the upper address bits when an external extended mode register set (EMRS) command is input. The method of claim 1, The command interpreting means, When an active command is input from the external command pin, an active signal is generated to set the latch means selected by the latch select signal, When the refresh command is input from the external command pin, a semiconductor memory device for performing a partial array self refresh, characterized in that for generating a refresh signal. The method of claim 1, The command passing means, If the state of the latch means corresponding to the upper address bit is set to pass through the refresh signal, And performing a partial array self refresh when the state of the latch means corresponding to the upper address bit is reset.