KR20040005357A - A Structure For Treating The Cell Defects Of Semiconductor Device Of Method Thereof - Google Patents

A Structure For Treating The Cell Defects Of Semiconductor Device Of Method Thereof Download PDF

Info

Publication number
KR20040005357A
KR20040005357A KR1020020039876A KR20020039876A KR20040005357A KR 20040005357 A KR20040005357 A KR 20040005357A KR 1020020039876 A KR1020020039876 A KR 1020020039876A KR 20020039876 A KR20020039876 A KR 20020039876A KR 20040005357 A KR20040005357 A KR 20040005357A
Authority
KR
South Korea
Prior art keywords
cell
upper electrode
electrode
semiconductor device
central
Prior art date
Application number
KR1020020039876A
Other languages
Korean (ko)
Inventor
박효식
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020020039876A priority Critical patent/KR20040005357A/en
Publication of KR20040005357A publication Critical patent/KR20040005357A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A structure of a semiconductor device for processing a defect of a cell and a processing methods thereof are provided to cure the defect of the cell by implanting the hydrogen-nitrogen gas into a center etch portion of a top electrode laminated on a bottom electrode. CONSTITUTION: A charge storage apparatus for semiconductor device includes a bottom electrode(10) for storing charges and a top electrode(20) stacked on an upper surface of the bottom electrode(10). A structure of a semiconductor device for processing a defect of a cell includes a center etch portion(22) and a dummy cell(12). The center etch portion(22) is formed on a center of the top electrode(20). The center etch portion(22) has an exposed bottom portion. The hydrogen-nitrogen gas is implanted into the exposed bottom portion of the center etch portion(22) in an annealing process. The bottom electrode(10) exposed by the center etch portion(22) is formed with the dummy cell(12).

Description

반도체소자의 셀 결함처리구조 및 그 방법 { A Structure For Treating The Cell Defects Of Semiconductor Device Of Method Thereof }A structure for treating the cell defects of semiconductor device of method thereof}

본 발명은 반도체소자의 전하저장전극 셀(Cell)에 관한 것으로서, 특히, 전하저장장치인 하부전극을 형성하고 그 상부면에 상부전극인 플레이트를 적층한 후,상부전극의 플레이트 중앙부위에 식각으로 하부전극을 노출하고, 그 노출된 하부전극을 어드레스가 부여되지 않는 더미셀(Dummy Cell)로 이용하여 어닐링시 수소-질소가스가 중앙식각부위로 침투하여 중심부분의 셀의 결함을 치유하도록 하는 반도체소자의 셀 결함처리구조 및 그 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge storage electrode cell of a semiconductor device. In particular, a lower electrode, which is a charge storage device, is formed, and a plate, which is an upper electrode, is stacked on an upper surface thereof, and then etched on the plate center of the upper electrode. A semiconductor that exposes a lower electrode and uses the exposed lower electrode as an unaddressed dummy cell so that hydrogen-nitrogen gas penetrates into the central etching portion during annealing to heal defects in the cells in the center portion. A cell defect treatment structure of a device and a method thereof are provided.

일반적으로, 반도체소자의 공정시 손상된 셀(Damaged)이나 트랩(Trap)된 셀을 치유하기 위하여 전하저장전극의 상부전극인 플레이트 공정 이후에 수소-질소 어닐링 열처리를 해준다.In general, a hydrogen-nitrogen annealing heat treatment is performed after a plate process, which is an upper electrode of the charge storage electrode, to heal damaged or trapped cells during processing of a semiconductor device.

상기 수소-질소 어닐링을 850℃ 정도로 30분정도 처리해주면 수소-질소가 상부전극 밑으로 침투하여 공정 진행중에 발생하였거나 원래부터 지니고 있던 결함셀들을 치유해준다. 특히, 상부전극플레이트의 측면부분으로 침투하여 결함을 치유하여준다. 상기 어닐링공정은 메탈공정이 완료된 후에는 450°에서 30분 정도처리하여도 충분하다.When the hydrogen-nitrogen annealing is performed at about 850 ° C. for about 30 minutes, hydrogen-nitrogen penetrates under the upper electrode to heal the defective cells generated or originally in progress. In particular, it penetrates into the side portion of the upper electrode plate to heal the defect. After the annealing process is completed, the metal processing may be performed at 450 ° for about 30 minutes.

도 1은 종래의 256 ×512셀 전하보존장치의 상부전극과 하부전극 배열도이다.1 is a top and bottom electrode arrangement diagram of a conventional 256 x 512 cell charge storage device.

종래의 전하를 보존하는 전하보존장치의 구성은, 여러 공정을 거쳐 전하를 저장하는 하부전극(2)을 형성하도록 한다. 도면에서 도시된 바와 같이, 사각형상으로 가로, 세로로 일정한 간격으로 배열하여 다수 형성하도록 한다.The conventional structure of the charge storage device for storing charges makes it possible to form the lower electrode 2 for storing charges through various processes. As shown in the figure, to form a plurality by arranging at regular intervals horizontally and vertically in a rectangular shape.

그리고, 그 위에 플레이트 형상인 다결정 실리콘을 적층하여 상부전극(4)을 형성하게 된다.Then, the upper electrode 4 is formed by stacking plate-shaped polycrystalline silicon thereon.

그런데, 상기한 바와 같이, 하부전극에 넓은 면적을 갖는 상부전극인 플레이트가 덮고 있으므로 어닐링공정시에 수소-질소가 플레이트의 측면부분을 통하여 하부전극인 셀로 침투하여 결함을 치유하게 되지만, 중앙부분에 위치한 셀에는 수소-질소가 도달하지 못하므로 치유하기 어려운 문제점을 지닌다.However, as described above, since the upper electrode plate having a large area is covered on the lower electrode, hydrogen-nitrogen penetrates into the lower electrode cell through the side portion of the plate during the annealing process, and the defect is healed. Hydrogen-nitrogen does not reach the cells in which it is located, which makes it difficult to cure.

실제로 패시베이션(Passivation) 하지 않은 웨이퍼에서 리프레쉬 테스트(Refresh Test)를 하면, 256 ×512셀을 덮고 있는 단위플레이트에서 플레이트의 외각부분은 수소-질소가 잘 침투하여 결함이 잘 치유 되지만 플레이트 내측에 있는 결함셀은 치유되기 어려워서 반도체소자의 페일(Fail)을 유발하는 단점을 지닌다.In the case of a refresh test on a non-passivated wafer, in the unit plate covering 256 x 512 cells, the outer part of the plate penetrates the hydrogen-nitrogen well so that the defect is well healed, but the defect inside the plate The cell is difficult to heal and has a disadvantage of causing a fail of the semiconductor device.

본 발명은 이러한 점을 감안하여 안출한 것으로서, 전하저장장치인 하부전극을 형성하고 그 상부면에 상부전극인 플레이트를 적층한 후, 상부전극의 플레이트 중앙부위에 식각으로 하부전극을 노출하고, 그 노출된 하부전극을 어드레스가 부여되지 않는 더미셀로 이용하여 어닐링시 수소-질소 분자가 중앙식각부위로 침투하여 중심부분의 셀의 결함을 치유하도록 하는 것이 목적이다.The present invention has been made in view of this point, and after forming a lower electrode as a charge storage device and stacking the upper electrode plate on the upper surface, the lower electrode is exposed by etching to the center portion of the plate of the upper electrode, It is an object to use the exposed lower electrode as an unaddressed dummy cell so that hydrogen-nitrogen molecules penetrate into the central etching portion during annealing to heal defects of cells in the central portion.

도 1은 종래의 256 ×512셀 전하보존장치의 상부전극과 하부전극 배열도이고,1 is a top and bottom electrode arrangement of the conventional 256 x 512 cell charge storage device,

도 2는 본 발명에 따른 256 ×512셀 전하보존장치의 상부전극과 하부전극 배열도이다.2 is an arrangement diagram of an upper electrode and a lower electrode of a 256 × 512 cell charge storage device according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10 : 하부전극 12 : 더미셀10: lower electrode 12: dummy cell

20 : 상부전극 22 : 중앙식각부위20: upper electrode 22: central etching portion

본 발명의 목적은, 전하를 저장하는 하부전극과; 상기 하부전극 상부면에 플레이트 형상으로 적층되는 상부전극으로 이루어진 반도체소자의 전하보존장치에 있어서, 상기 상부전극의 중앙부위에 하부가 노출되고, 어닐링시 수소-질소가 침투하도록 하는 중앙식각부위를 형성하고, 상기 중앙식각부위를 통하여 노출된 하부전극을 여분의 더미셀로 형성하는 반도체소자의 셀결함처리구조를 제공함으로써 달성된다.An object of the present invention, the lower electrode for storing the charge; In the charge storage device of a semiconductor device consisting of an upper electrode stacked on the upper surface of the lower electrode in a plate shape, the lower portion is exposed to the central portion of the upper electrode, and forms a central etching portion to allow hydrogen-nitrogen to penetrate during annealing In addition, the present invention provides a cell defect treatment structure of a semiconductor device in which the lower electrode exposed through the central etching portion is formed as an extra dummy cell.

그리고, 하부전극의 중앙부위에서 다수개의 하부전극을 더미셀로 형성하는 단계; 상기 결과물 상에 상부전극인 플레이트를 적층하는 단계와; 상기 상부전극의 중앙식각부위를 식각하여 더미셀을 노출하는 단게와; 상기 결과물에 어닐링공정으로 수소-질소를 공급하여 상부전극의 중앙식각부위로 침투하여 셀의 결함을 치유하도록 하는 단계를 포함하여 이루어진 반도체소자의 셀 결함처리방법을 제공함으로써 달성된다.And forming a plurality of lower electrodes as dummy cells at the center of the lower electrode; Stacking a plate as an upper electrode on the resultant; Exposing a dummy cell by etching a central etching portion of the upper electrode; It is achieved by providing a cell defect treatment method of a semiconductor device comprising the step of supplying hydrogen-nitrogen in the annealing process to the resultant to penetrate the central etching portion of the upper electrode to heal the defect of the cell.

그리고, 상기 어닐링공정은, 800 ∼ 900℃의 온도범위에서 20분 ∼ 40분 간 처리하도록 한다.And, the annealing step is to be treated for 20 to 40 minutes in the temperature range of 800 ~ 900 ℃.

특히, 상기 어닐링공정은, 850℃의 온도에서 30분간 처리하는 것이 바람직 하다.In particular, the annealing step is preferably treated for 30 minutes at a temperature of 850 ℃.

만약, 어닐링공정은 메탈공정이 완료된 후 진행하는 경우에는 450°에서 30분 정도처리 하여도 충분하다.If the annealing process is performed after the metal process is completed, the annealing process may be performed at 450 ° for about 30 minutes.

또한, 상기 상부전극의 중앙식각부위는, 단축방향으로 형성하는 것이 바람직 하다.In addition, the central etching portion of the upper electrode is preferably formed in the short axis direction.

이하, 첨부도면에 의거하여 본 발명의 일 실시예를 살펴 보도록 한다.Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

도 2는 본 발명에 따른 256 ×512셀 전하보존장치의 상부전극과 하부전극 배열도이다.2 is an arrangement diagram of an upper electrode and a lower electrode of a 256 × 512 cell charge storage device according to the present invention.

본 발명의 구성은, 전하를 저장하는 하부전극(10)과; 상기 하부전극(10) 상부면에 플레이트 형상으로 적층되는 상부전극(20)으로 이루어진 반도체소자의 전하보존장치에 있어서, 상기 상부전극(20)의 중앙부위에 하부가 노출되고, 어닐링시 수소-질소가 침투하도록 하는 중앙식각부위(22)를 형성하고, 상기 중앙식각부위(22)를 통하여 노출된 하부전극(11)을 여분의 더미셀(12)로 형성하도록 한다.The configuration of the present invention, the lower electrode 10 for storing the charge; In the charge preservation apparatus of the semiconductor device including the upper electrode 20 stacked on the upper surface of the lower electrode 10, the lower part is exposed to the central portion of the upper electrode 20, and hydrogen-nitrogen is annealed. To form a central etching portion 22 to penetrate, and the lower electrode 11 exposed through the central etching portion 22 to form an extra dummy cell 12.

이하, 본 발명의 반도체소자의 셀 결함처리방법을 살펴 보도록 한다.Hereinafter, a cell defect processing method of the semiconductor device of the present invention will be described.

먼저, 하부전극(10)의 중앙부위에서 다수개를 하부전극(10)을 더미셀(12)로 형성하도록 한다.First, a plurality of lower electrodes 10 are formed as dummy cells 12 at a central portion of the lower electrode 10.

그리고, 상기 결과물 상에 상부전극(20)인 플레이트를 적층하도록 한다.Then, to stack the plate which is the upper electrode 20 on the resultant.

그리고, 도 2에서와 같이, 상기 상부전극(20)의 중앙식각부위(22)를 식각하여 더미셀(12)을 노출하도록 한다.As shown in FIG. 2, the central etching portion 22 of the upper electrode 20 is etched to expose the dummy cell 12.

상기 더미셀(12)은 어드레스를 부여하지 않도록 한다.The dummy cell 12 is not given an address.

그리고, 상기 결과물에 어닐링공정으로 수소-질소를 공급하여 상부전극(20)의 중앙식각부위(22)로 침투하여 셀의 결함을 치유하도록 하도록 한다.Then, hydrogen-nitrogen is supplied to the resultant by an annealing process to penetrate into the central etching portion 22 of the upper electrode 20 to heal the defect of the cell.

즉, 어닐링공정에서 수소-질소가스는 상부전극인 플레이트의 측면부분을 통하거나 중앙식각부위(22)를 통하여 공급되어지면서 셀의 결함을 치유하게 된다.That is, in the annealing process, hydrogen-nitrogen gas is supplied through the side portion of the plate as the upper electrode or through the central etching portion 22 to heal the defect of the cell.

상기 어닐링공정은, 800 ∼ 900℃의 온도범위에서 20분 ∼ 40분 간 처리하는 것이 바람직하고, 특히, 어닐링공정은, 850℃의 온도에서 30분간 처리하는 것이 가장 바람직 하다.It is preferable to process the said annealing process for 20 minutes-40 minutes in the temperature range of 800-900 degreeC, and especially, it is most preferable to process annealing process at the temperature of 850 degreeC for 30 minutes.

그리고, 상기 상부전극(20)의 중앙식각부위(22)는, 단축방향으로 형성하도록 한다.In addition, the central etching portion 22 of the upper electrode 20 may be formed in a short axis direction.

따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 셀 결함처리구조 및 그 방법에 의하면, 전하저장장치인 하부전극을 형성하고 그 상부면에 상부전극인 플레이트를 적층한 후, 상부전극의 플레이트 중앙부위에 식각으로 하부전극을 노출하고, 그 노출된 하부전극을 어드레스가 부여되지 않는 더미셀(Dummy Cell)로 이용하여 어닐링시 수소-질소 가스가 중앙식각부위로 침투하여 중심부분의 셀의 결함을 치유하므로 반도체소자의 수율을 증대하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, according to the cell defect treatment structure and method of the semiconductor device according to the present invention, after forming a lower electrode as a charge storage device and stacking the upper electrode plate on the upper surface, the plate of the upper electrode The lower electrode is exposed by etching to the center part, and the exposed lower electrode is used as a dummy cell which is not given an address, and when annealing, hydrogen-nitrogen gas penetrates into the center etching part so that the cell of the center part is defective. Therefore, it is a very useful and effective invention for increasing the yield of semiconductor devices.

Claims (5)

전하를 저장하는 하부전극과; 상기 하부전극 상부면에 플레이트 형상으로 적층되는 상부전극으로 이루어진 반도체소자의 전하보존장치에 있어서,A lower electrode for storing charge; In the charge storage device of the semiconductor device consisting of an upper electrode stacked on the upper surface of the lower electrode, 상기 상부전극의 중앙부위에 하부가 노출되고, 어닐링시 수소-질소가 침투하도록 하는 중앙식각부위를 형성하고, 상기 중앙식각부위를 통하여 노출된 하부전극을 여분의 더미셀로 형성하는 것을 특징으로 하는 반도체소자의 셀 결함처리구조.A lower portion is exposed to a central portion of the upper electrode, and a central etching portion is formed to allow hydrogen-nitrogen to penetrate during annealing, and the lower electrode exposed through the central etching portion is formed as an extra dummy cell. Cell Defect Handling Structure of Semiconductor Device. 하부전극의 중앙부위에서 다수개를 하부전극을 더미셀로 형성하는 단계;Forming a plurality of lower electrodes as dummy cells at a central portion of the lower electrode; 상기 결과물 상에 상부전극인 플레이트를 적층하는 단계와;Stacking a plate as an upper electrode on the resultant; 상기 상부전극의 중앙식각부위를 식각하여 더미셀을 노출하는 단계와;Etching a central etching portion of the upper electrode to expose a dummy cell; 상기 결과물에 어닐링공정으로 수소-질소를 공급하여 상부전극의 중앙식각부위로 침투하여 셀의 결함을 치유하도록 하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 셀 결함처리방법.And a step of supplying hydrogen-nitrogen to the resultant to penetrate into the central etching portion of the upper electrode to heal the defect of the cell. 제 2 항에 있어서, 상기 어닐링공정은, 800 ∼ 900℃의 온도범위에서 20분 ∼ 40분 간 처리하는 것을 특징으로 하는 반도체소자의 셀 결함처리방법.The method of claim 2, wherein the annealing step is performed for 20 to 40 minutes at a temperature in the range of 800 to 900 占 폚. 제 3 항에 있어서, 상기 어닐링공정은, 메탈공정이 완료된 경우에는 450℃의 온도에서 30분간 처리하는 것을 특징으로 하는 반도체소자의 셀 결함처리방법.The method of claim 3, wherein the annealing process is performed for 30 minutes at a temperature of 450 ° C. when the metal process is completed. 제 2 항에 있어서, 상기 상부전극의 중앙식각부위는, 단축방향으로 형성하는 것을 특징으로 하는 반도체소자의 셀 결함처리방법.The method of claim 2, wherein the central etching portion of the upper electrode is formed in a short axis direction.
KR1020020039876A 2002-07-10 2002-07-10 A Structure For Treating The Cell Defects Of Semiconductor Device Of Method Thereof KR20040005357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020020039876A KR20040005357A (en) 2002-07-10 2002-07-10 A Structure For Treating The Cell Defects Of Semiconductor Device Of Method Thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020020039876A KR20040005357A (en) 2002-07-10 2002-07-10 A Structure For Treating The Cell Defects Of Semiconductor Device Of Method Thereof

Publications (1)

Publication Number Publication Date
KR20040005357A true KR20040005357A (en) 2004-01-16

Family

ID=37315684

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020039876A KR20040005357A (en) 2002-07-10 2002-07-10 A Structure For Treating The Cell Defects Of Semiconductor Device Of Method Thereof

Country Status (1)

Country Link
KR (1) KR20040005357A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009070874A1 (en) 2007-12-05 2009-06-11 Institut National De La Recherche Scientifique Gecl4 and/or sicl4 recovery process from optical fibers or glassy residues and process for producing sicl4 from sio2 rich materials
US9520401B2 (en) 2013-05-23 2016-12-13 Samsung Electronics Co., Ltd. Semiconductor devices capable of self-curing

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009070874A1 (en) 2007-12-05 2009-06-11 Institut National De La Recherche Scientifique Gecl4 and/or sicl4 recovery process from optical fibers or glassy residues and process for producing sicl4 from sio2 rich materials
US9520401B2 (en) 2013-05-23 2016-12-13 Samsung Electronics Co., Ltd. Semiconductor devices capable of self-curing

Similar Documents

Publication Publication Date Title
CN109887936A (en) Array substrate and preparation method thereof
JP2005528797A5 (en)
CN105990123A (en) Wafer thinning method
KR20040005357A (en) A Structure For Treating The Cell Defects Of Semiconductor Device Of Method Thereof
KR20070101978A (en) Glass treatment apparatus
US6417064B1 (en) Method for treating the surface of a deep trench
KR100622806B1 (en) Method for manufacturing the semiconductor device
KR100275959B1 (en) Heavy metal impurity gettering method
JPH06168956A (en) Manufacture of thin-film transistor
CN113178385A (en) Chip manufacturing method and device and chip
KR100320677B1 (en) method for manufacturing thyristor devices
JPS6092611A (en) Diffusing method of impurity of semiconductor element
JPH1167684A (en) Semiconductor device and its manufacture
KR100588217B1 (en) Method for forming gate oxide in semiconductor device
US7314803B2 (en) Method for producing a semiconductor structure
KR20100123112A (en) Method for fabricating of wafer
JPH0493079A (en) Manufacture of semiconductor device
KR930005230B1 (en) Manufacturing method of metal-oxide-silicon field effect transistor (mosfet)
JPS6151843A (en) Formation of oxide film for isolating element of semiconductor device
JPH04306841A (en) Manufacture of semiconductor device
JPS63196064A (en) Production of semiconductor device
JPH10321603A (en) Peeling method of resist and its device
KR980005371A (en) Method for forming polysilicon film of semiconductor device
JPS603126A (en) Formation of insulating layer
KR20010109791A (en) Metal impurity gettering method in silicon wafer

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid