KR20040002762A - Modulating apparatus for using fast fourier transform of mixed-radix scheme - Google Patents

Abstract

PURPOSE: A mixed-radix type modulation apparatus using FFT(Fast Fourier Transform) is provided to improve calculation performance as well as reduce device size. CONSTITUTION: A mixed-radix type modulation apparatus using FFT, is provided with an input/output interface(101) for carrying out an input and output process, a pair of N word memories(102,103) having four banks, and the first data switching part(104) for connecting the banks assigned to the input/output of each butterfly(105) with four inputs of a butterfly operational circuit to select a memory and perform in-place calculation for a FFT process . At this time, the butterfly is capable of carrying out the Radix-4 and Radix-2 supplied from the first data switching part by using one circuit. The mixed-radix type modulation apparatus using FFT further includes the second data switching part(106) and an address generating part.

Description

Mixed-odd modulator using fast Fourier transform {MODULATING APPARATUS FOR USING FAST FOURIER TRANSFORM OF MIXED-RADIX SCHEME}

The present invention relates to a data modulation device, and more particularly, to an orthogonal frequency division multiplexing (OFDM) system or a discrete multi-tone (DMT) modulation device.

In general, in a digital data communication system, data is transmitted through modulation and demodulation at the time of data transmission and reception. This modulation and demodulation is performed in a device called a modem. The device of the modem for modulation and demodulation has a different configuration and structure according to each modulation scheme. Common modulation schemes used in data communications include code multiplexing (CDM), frequency modulation (FDM), orthogonal frequency modulation (hereinafter referred to as "OFDM"), and discrete multiple tones (hereinafter referred to as "DMT"). Modulation schemes and the like.

Hereinafter, the OFDM scheme and the DMT modulation scheme will be described.

The OFDM scheme is proposed for high speed data transmission through a multipath channel in a wireless communication system. Prior to the OFDM scheme, data was transmitted in a single carrier transmission scheme. That is, in a wireless communication system prior to the OFDM scheme, serial data to be transmitted is modulated, and each symbol modulated at the time of transmission is transmitted using the frequency band of all channels. However, the OFDM method or the DMT method converts the modulated data as many as the number of subcarriers (subcarriers) in parallel and modulates them into corresponding subcarriers. Modulation using such subcarriers is implemented using Discrete Fourier Transform (DFT). However, real hardware designs do not use DFTs or Inverse Discrete Fourier Transforms (IDFTs) and use Fast Fourier Transforms (FFTs) algorithms to reduce computation. Implement using The processor for processing such an FFT algorithm has the largest complexity in an OFDM system and requires high speed computation. Therefore, the processor for processing the FFT algorithm is a difficult part to implement.

As the FFT processor used in the field requiring such high performance, an FFT processor having a pipeline line structure is mainly used. However, this structure requires as many computation units as the number of stages, and consumes a large area when implemented in real hardware when the number of points increases. Therefore, processors are proposed that use a memory structure and a single butterfly operation unit to overcome the above problems and maintain a small hardware size.

One example is a memory structure FFT processor using Radix-2 (hereinafter referred to as "Radix-2") FFT algorithm. The memory structure FFT processor can use the Radix-2 algorithm in the memory structure, thereby minimizing the number of multipliers. Therefore, the memory structure FFT processor can implement an FFT processor that consumes a small area.

However, the memory structure FFT processor using the Radix-2 algorithm requires a lot of computational cycles. Therefore, the computation time becomes very long. Therefore, it is not suitable for an OFDM system or a DMT system requiring high speed operation, and a very high operating frequency is required to satisfy this. Therefore, in general, an OFDM system or a DMT system mainly uses a Radix-4 (Radix-4: hereinafter referred to as "Radix-4") algorithm rather than a Radix-2 scheme. The following describes the Radix-4 algorithmic FFT processors that have been published and used.

Figure 1 shows an FFT processor based on the Radix-4 algorithm published by AMPHION. In the case of the Radix-4 algorithm, the number of stages is reduced to 1/2 compared to the Radix-2 algorithm. The number of butterfly operations per stage is also half that of Radix-2. Therefore, the Radix-4 algorithm has much fewer butterfly operations than the Radix-2 algorithm. Table 1 shows the number of operations according to the FFT length of the Radix-4 algorithm, the Radix-2 algorithm, and the horn-odd algorithm described below.

FFT length Radix-2 Radix-4 Mixed-base 256 1,024 256 - 512 2,304 - 640 1,024 5,120 1,280 - 2,048 11,264 - 3,072 4,096 24,576 6,144 - 8,192 53,248 - 14,336

As shown in Table 1, the Radix-4 algorithm is only capable of FFT operations having a length of 4 ⁿ (n is an integer below), and the Radix-2 algorithm has a length of 2 ⁿ . The length of the FFT can be calculated. This will be described below using the FFT length shown in Table 1. Since the FFT length 256 is 2 ^8, it can be used in both the Radix-2 and Radix-4 algorithms. However, because the FFT length 512 is 2 ⁹ , the Radix-4 algorithm cannot perform the operation when the FFT length is 512. Therefore, a mixed-radix algorithm is required that uses the Radix-4 algorithm with other Radix to enable all FFT operations with a length of 2 ⁿ . The last column of Table 1 shows the number of butterfly operations when the mixed-radix algorithm using the Radix-4 and Radix-2 algorithms is used. The number of operations on the mixed-base of <Table 1> is the number of operations performed by the apparatus provided by Ampion Co., Ltd. of FIG. Then, with reference to Figure 1 looks at the device provided by Ampion.

The FFT processor of FIG. 1 using the mixed-odd algorithm selectively combines Radix-4 butterfly and Radix-4 / Radix-2 buffer fly to mix Radix-4, Radix-8 and Radix-16. Perform a radix operation.

The input / output interface and the controller 11 control to FFT the data X input from the outside, and output the result data Y from which the FFT operation is performed to the outside of the processor. Herein, the data X input to the input / output interface and the controller 11 and the output data Y may be OFDM symbols or DMT symbols. The memory controller 12 controls address generation of the memory 13 to read and write data input for FFT operation from the input / output interface and the controller 11 and data in operation. The memory 13 is configured as a 1024-word dual port memory, and stores or reads data input from the outside, data in the middle of the FFT operation, and result data at an address indicated by the memory controller 12.

In addition, the butterfly calculating unit 10 includes a Radix-4 butterfly 14, a rotation factor lookup table (LUT) 16, and a decoding multiplier 15. The Radix-4 butterfly 14 performs addition and subtraction operations among Radix-4 butterfly operations. The rotation factor LUT 16 is a memory table that stores rotation factors of data on which calculation is performed and outputs rotation factor values. The complex multiplier 15 performs a multiplication on the complex number during the Radix-4 butterfly operation and outputs the result. In addition, the Radix-4 / Radix-2 selective butterfly 17 is a device for selectively performing the required final operation according to the FFT length. In other words, if the final operation requires Radix-2 operation according to the FFT length, select Radix-2 butterfly to perform Radix-2 operation. If the final operation requires Radix-4 operation, Radix- 4 Select Butterfly to perform Radix-4 operations. Therefore, the overall FFT operation is performed in conjunction with the Radix-4 butterfly operation of the operation unit 10 to perform Radix-8 or Radix-16 operation. Therefore, in the last stage, the Radix-4 / Radix-2 selective butterfly 17 is used, and in the remaining stages, the MUX 18 is used to use only the Radix-4 butterfly calculation unit 10. The Radix-4 algorithm is implemented as a butterfly with four inputs and outputs. Therefore, four inputs and outputs must be performed in one cycle to minimize the operation cycle. In order to achieve four inputs and outputs in one cycle, the memory must be divided into multiple banks. However, the FFT processor of FIG. 1 has a structure that does not use a multi-bank structure. Therefore, when the operation is performed in the structure as shown in FIG. 1, many operation cycles are required and thus the advantage of the Radix-4 operation is not utilized.

FIG. 2 is a block diagram of an FFT processor having a mixed-odd algorithm and a multi-bank structure published by Drey Enterprise. As shown in FIG. 2, the FFT processor released by Dray Enterprise also has a memory structure. In the FFT processor of FIG. 2, one of two memories (RAM) 21 and 22 stores the external input data while the other RAM is used for the FFT operation. The MUX 23 then determines whether to receive a butterfly input from one of the input RAMs or a butterfly input from one of the output RAMs 28, 29. The Radix-2 calculators 26 and 27 perform a Radix-2 operation at the stage performing the Radix-2 operation and output the result. The MUX 24 also receives the Radix-2 butterfly output from the Radix-2 calculators 26 and 27 and stores it in one of the input RAMs 21 and 22 or in one of the output RAMs 28 and 29. Output multiplexed result values for storage. The Radix-2 / Radix-4 shared operation unit 25 performs Radix-4 operation at the stage performing Radix-4 operation, and performs Radix-2 operation at the stage performing Radix-2 operation to obtain the result value. Output While one of the two output RAMs 28 and 29 is used for the FFT operation, the other one outputs the result data of the FFT operation to the outside. The structure shown in FIG. 2 uses a mixed-base algorithm of Radix-4 and Radix-2, and a memory also uses a multi-bank structure. Therefore, the operation clock cycle is minimized by using the multi-bank structure of the memory.

However, the structure of FIG. 2 does not apply an in-plase algorithm that stores the butterfly output in a memory location where the butterfly input is accessed. Therefore, the structure uses two memories having N words for FFT operation. That is, only two memories among four banks of memory may be used for the FFT operation alone, but two memories for input and output must be used to perform continuous processing. Therefore, a total of four memories are used in FIG. 2. Memory is one of the blocks that occupies most of the area in an FFT processor. Therefore, when the number of memories increases as described above, the complexity of the memory increases, the volume of the hardware increases, and the price increases.

In order to minimize the memory complexity of the memory structures. An example of the 16-point FFT of the in-place algorithm published by L. G. Johnson is shown in FIG. 3. The in-place algorithm is an algorithm for the case where the memory is divided into multiple banks. Four data must be accessed simultaneously for the Radix-4 butterfly operation, and four results of the butterfly operation must be stored simultaneously in the accessed location. To do this, the main memory is divided into four banks (bank 0, bank 1, bank 2, and bank 3), and appropriate addressing must be performed to avoid accessing multiple data in one bank at the same time. 3 is an example of in-place memory addressing for a 16-point FFT. Referring to FIG. 3, a configuration is performed from the first butterfly operation to the eighth butterfly operation. Also, look at each butterfly operation, taking four inputs at a time. Four inputs are then read from different banks. Let's take a look at the first and second butterfly operations. ① In case of butterfly, read 4 inputs from address 0 of bank, address 1 of bank 1, address 2 of bank 2, address 3 of bank 3, and store the result of butterfly operation in the same banks and addresses. . In the case of No. 2 butterfly, four inputs are read from address 0 of bank 1, address 1 of bank 2, address 2 of bank 3, and address 3 of bank 0, and the result of the butterfly operation is stored in the same position. The bank index (bank i) indicating which bank to use in FIG. 3 can be easily obtained by dividing the data input count bits into 2-bit digits and taking modulo-4 addition. Since FIG. 3 is a 16-point FFT, a 4-bit counter is used to count 16 data. The bank index is obtained by dividing the four bits into the digits of the upper two bits and the lower two bits, and performing modulo-4 addition on the upper two bits and the lower two bits.

However, the in-place algorithm described above has been proposed for use only in fixed radix, not mixed-base. Therefore, there is a problem that the in-place algorithm described above cannot be applied to the mixed-base system as it is.

The following describes a conventional structure having a continuous processing structure. R. Radhouane has proposed a FFT processor with a memory structure capable of performing continuous processing using only two memories having an N word size by simultaneously performing input and output in the memory structure. In the above structure, the DIF operation is performed once in the Radix-2 algorithm and the DIT operation is performed. Implemented Table 2 below shows a calculation method of a continuous processing structure using two memories.

Memory 1 Memory 2 OFDM symbol Memory status FFT-I / 0 mode Memory status FFT-I / 0 mode 0 C DIF I / O NAT One I / O BR C DIF 2 C DIT I / O BR 3 I / O NAT C DIT

In Table 2, the OFDM symbol means data corresponding to the length of the FFT operation. For example, in the case of a 256-point FFT operation, one OFDM symbol means 256 data. In Table 2, C means FFT operation and I / O means I / O. NAT is the original 0, 1, 2, 3,…. In other words, the memory addressing is performed in the correct order of the address N-1, and the BR means the memory I / O is performed by bit reverse addressing. In addition, while memory 1 performs DIF operation in OFDM symbol 0 of Table 2, memory 2 performs input / output by addressing NAT in the correct order. In the next OFDM symbol, memory 1 performs input / output by BR, that is, bit reverse addressing, and memory 2 performs operation by DIF. In symbol 2, memory 1 performs operations with DIT, and memory 2 performs input and output with BR, that is, bit reverse addressing. In symbol 3, memory 1 performs I / O in the correct order, and memory 2 operates with DIT. From the next 4 symbols, the operation flow of 0, 1, 2, 3 symbols is repeated. To enable continuous processing with two memories, the other memory must be able to execute input and output in sequential order while one memory performs the operation. As described above, in the above structure, two memories can be successively processed with only two memories in a manner in which I / O and FFT operations are alternately performed.

While the conventional structure disclosed by Alcatel Inc. implements continuous processing using three memories, the conventional continuous processing structure can minimize memory complexity using only two memories.

However, the continuous processing structure is configured only for the case of using the Radix-2 algorithm. Therefore, since only Radix-2 operations are performed, there are problems that require many operation cycles and high operating frequencies.

In order to solve the above problems, an object of the present invention is to provide a processor capable of satisfying high performance and minimizing an area by providing a circuit having a minimum complexity and a high speed operation in an FFT processor.

Another object of the present invention is to provide a processor device capable of reducing a small area and complexity while providing a mixed-base of Radix-2 / Radix-4 when performing an FFT operation.

It is still another object of the present invention to provide a processor device capable of processing at high speed while providing a mixed-base of Radix-2 / Radix-4 in a processor performing an FFT operation.

It is another object of the present invention to provide a processor device capable of continuous processing while providing a mixed-base of Radix-2 / Radix-4 in a processor performing an FFT operation.

In order to achieve the above objects, the present invention provides a FFT processor having a mixed-radix algorithm and a continuous processing structure, comprising: an input / output interface for performing input and output from a selected memory and an arbitrary bank of the selected memory; Two N word memories consisting of four banks used for input and output to the interface and FFT operations; A data exchanger for supplying four buckle inputs from the selected memory and bank; A Radix-4 / 2 butterfly operation circuit configured to perform two types of butterflies supplied from the data exchanger as a single circuit and configure a symmetrical reverse output; A data exchanger for supplying four butterfly outputs to said selected memory and bank; An FFT processor includes an address generator for generating an address for performing an in-place operation in a multi-bank memory structure.

The present invention for achieving the above object is a mixed-odd modulation device using a fast Fourier transform, comprising: two memories consisting of four banks for storing input symbols or symbols for which fast Fourier operations have been completed; A butterfly that performs a butterfly operation in radix-4 or radix-2 according to the number of symbols output from the memory, and outputs the calculated values symmetrically in reverse, and each bank of one of the memories A first data exchanger reading one symbol from each of the symbols and outputting the symbols to the butterfly, and storing the symbols calculated and outputted from the butterfly at the same address as the address read from the first data exchanger. A second data exchanger matching the data sets and a symbol read from the first data exchanger after the operation is performed. And an address generator for controlling the output of the second data exchange unit such that the bank and address read from the first data exchange unit and the output bank and address of the second data exchange unit are the same when outputted through the data exchange unit. It is done.

1 is a block diagram illustrating the structure of a mixed-radix algorithm FFT processor that does not use a conventional multi-bank structure.

2 is a block diagram illustrating the structure of a hop-odd algorithm FFT processor that does not use a conventional in-place algorithm.

FIG. 3 illustrates a Radix-4 in-place algorithm for a conventional multi-bank memory. FIG.

4 is a block diagram illustrating the structure of an In-place algorithm mixer-based FFT processor with a continuous processing structure in accordance with the present invention.

5 is a computational flow diagram of a 32-point mixed-odd FFT processor in accordance with the present invention.

6A is a block diagram of a Radix-4 / Radix-2 butterfly circuit used in the FFT processor of FIG.

FIG. 6B shows an equivalent butterfly pair during the Radix-2 butterfly operation of FIG. 6A. FIG.

7 is a flow chart of an FFT operation for implementing continuous processing when using only the Radix-4 algorithm of FIG.

8A illustrates the digit reverse order of output when using only the Radix-4 algorithm for 4 ⁿ -point FFT operations.

FIG. 8B shows the asymmetric reverse order of the outputs when using a Mixed-radix algorithm using Radix-2 together for a 2 ⁿ (n = 3, 5, 7, 9,…) -point FFT operation.

9 illustrates an asymmetric reverse output order corresponding to column 4 of FIG. 5, which is a 32-point Mixed-radix FFT operation.

FIG. 10 shows a symmetrical reverse output sequence corresponding to column 3 of FIG. 5, which is a 32-point Mixed-radix FFT operation.

FIG. 11 shows the symmetric reverse output order of mixed-base for 2 ⁿ (n = 3, 5, 7, 9, ...)-point FFT operations.

12 is a flow diagram illustrating data exchange for generating a symmetric reverse output order corresponding to column 3 of FIG.

Figure 13 illustrates the bank index generation method of Figure 5 which is a 32-point mixed-odd FFT operation.

14 illustrates a method for generating a mixed-base bank index for a 2 ⁿ (n = 3, 5, 7, 9, ...)-point FFT operation.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a block diagram of an FFT processor applying a in-place algorithm according to the present invention and simultaneously performing a mixed-radix structure and an input / output in a 2N word memory.

The input / output interface 101 selects one of the memories 102 and 103 for the FFT operation on the input data, and selects one of the four banks of the memory to record the data. When the operation of the input data is completed, the input / output interface 101 selects a memory in which the data on which the FFT operation is completed is stored, selects one bank among four banks of the selected memory, and reads out the data. Two N word memories 102 and 103 having four banks store data input from the interface 101 and output the data to the first data exchanger 104 for FFT operation of the stored data. The data received from the data exchange unit 106 is stored again. In addition, the data in which the FFT operation is completed in each of the memories 102 and 103 is output to the input / output interface 101. The first data exchanger 104 selects a memory in which data to perform an FFT operation and a bank of the memory, and reads four data from a bank of the memory selected for in-place operation according to the present invention. The first data exchanger 104 exchanges the read data according to the address generation value output from the address generator 107 and outputs the read data to the Radix-4 / 2 butterfly 105. In addition, the Radix-4 / 2 butterfly 105 according to the present invention operates in the Radix-4 method or the Radix-2 method according to the data input from the first data exchanger 104. To perform. The Radix-4 / 2 butterfly 105 consists of one circuit and has a symmetrical reverse output. The data calculated by the Radix-4 / 2 butterfly 105 is output to the second data exchange unit 106. The second data exchanger 106 selects and stores a memory to store a value output from the Radix-4 / 2 butterfly 105 and a bank in the memory according to an address received from the address generator 107. do. The address generator 107 generates and outputs a bank index and an address for performing an in-place operation according to the present invention in the multi-bank memory structure.

The FFT processor having the structure of FIG. 4 has a flowchart as shown in FIG. 5. 5 shows an example of a 32-point mixed-radix FFT operation, in which stage 1 and stage 2 are Radix-4, and stage 3 is Radix-2. As shown in FIG. 4, in the structure of the present invention, two data are divided into four banks and four data can be accessed simultaneously. Thus, for a Raidx-2 butterfly using two data, two butterfly operations can be performed simultaneously. In addition, two Radix-2 butterflies in the thin solid line of Stage 3 represent butterfly pairs that can be executed simultaneously. Thus, by running two Radix-2 butterflies in one cycle at the same time, the benefit of computational cycle reduction can be seen.

In the FFT processor, the Radix-2 butterfly structure is implemented by adding a data switching circuit to the Radix-4 butterfly rather than a separate butterfly. This is shown in Figure 6a. In FIG. 6A, a Radix-4 butterfly and two Radix-2 butterflies are implemented through a multiplexer selection signal called 'Radix-2'. The drawings illustrated in FIG. 6A will be described below. The two symbols of data x (0) and the symbols of x (2) are input to the adders constituting each Radix-2 butterfly, and the symbols of x (1) and the symbols of x (3) are different. Inputs are made to the adders that make up the Radix-2 butterfly. In this way, the adders that make up each Radix-2 butterfly split the output into two, and each output is input to one input of the multiplexer. The other branched output is input to the other input terminal of each of the multiplexers by performing addition, subtraction, and subtraction of the outputs from different adders constituting the Radix-2 butterfly. Thereafter, the outputs of the multiplexers are branched again as shown in the drawing to be selected through the other multiplexers or output as is. The values thus output are mapped to addresses for in-place in accordance with the present invention. This will be described in more detail with reference to the accompanying drawings below. The equivalent circuit of FIG. 6A is configured as shown in FIG. 6B. 6B shows an equivalent Radix-2 butterfly pair when implementing a Radix-2 butterfly circuit with a Radix-4 butterfly circuit.

Next, a structure for performing continuous processing in the memory structure of the present invention will be described. As described in the prior art, the continuous processing structure proposed by R. Radhuan is the structure for the Radix-2 algorithm. However, the structure of the present invention is a structure for Radix-4 and mixed-base. In addition, the conventional structure is a method of alternately performing the FFT and DIT operations. However, the structure of the present invention performs only DIF operations and performs continuous processing only under the control of memory addressing.

In order to perform continuous processing as in the present invention, a symbol to be newly decoded must be stored at a position of a symbol to be decoded. In this way, the operation of reading a symbol to be decoded and storing a symbol to be decoded are simultaneously read and written by one clock. In addition, to satisfy the Radix-4 butterfly, only one symbol from each bank must be output from a memory with four banks. And, when the operation is completed through each stage, the symbols must be written to the read position. Therefore, creating an address in this way is the biggest challenge. The method described above can be easily implemented when using only the Radix-4 algorithm. Thus, FIG. 7 shows an example of a 16-point FFT using only the Radix-4 algorithm.

In FIG. 7, columns 1 and 2 represent memory banks and addresses where data are stored, and column 3 represents a digit reverse output order. In FIG. 7, externally input data are stored in the bank and the address of the column 2. The input data is performed four butterfly operations in the first stage and four butterfly operations in the second stage. That is, in FIG. 7, ① to ④ represent four butterfly operations performed in the first stage, and ⑤ to ⑧ represent four butterfly operations performed in the second stage. In the butterfly operation of each stage, it can be seen that one data is read from each of four banks provided in one memory. In the first butterfly operation, address 0 data of bank 0, address 1 data of bank 1, address 2 data of bank 2, and address 3 data of bank 3 are read. Therefore, data is read and processed one by one for each bank. In this way, when four butterfly operations are completed, four butterfly operations are performed again in the second stage.

The outputs computed in the above manner have the output order as shown in column 3 of FIG.

As described above, when the FFT operation is performed, the output is configured in the digit reverse order of column 3, and the memory storage location performs the in-place operation, so the bank and address of column 2 are maintained as they are. If the results of the operation are output in sequential order through digit reverse addressing and the next data is input in sequential order at the same time, new input data is stored in the bank and address of column 1. Output '0' of column 3 is stored in address 0 of bank 0 of column 2, and outputs it. Then, '0' of new data for the next FFT operation is stored in the bank and address where the output is made. Next, output '1' of column 3 is located at address 1 of bank 1 of column 2, and the output is stored in the position where the output is made. The output of '2' is stored in address 2 of bank 2 of column 2, and the output thereof is stored in the position where the output is made. Storing a new input in this way creates a bank and address for column 1. After the FFT operation is performed, the output is performed in sequential order and the inputs are stored in sequential order. Then, the FFT operation is restored to the bank and address assignment of column 2. Thus, the bank and address assignments in columns 1 and 2 are alternately performed.

In this way, if I / O can be performed simultaneously in a sequential order, the remaining memory can be processed continuously with only two memories while one memory performs an operation. In this case, the FFT operation should be performed at an operating frequency twice that of the input / output operating frequency. This is because, as shown in Table 1, the FFT computation clock cycle is longer than the number of FFT points. That is, the computational clock cycle is longer from 1024-point FFT for Radix-4 and 512-point FFT for Radix-4 / Radix-2 mixed-base.

In the case of mixed-odds, a separate operation is required for sequential input and output for continuous processing. In the case of a 32-point mixed-base the output is shown in column 4 of FIG. This has an asymmetric reverse form, unlike the reverse order of the Radix-4 algorithm in FIG. First, the digit reverse order when only the Radix-4 algorithm is used will be described. FIG. 8A shows the digit reverse order for the 2 ⁿ -point FFT of the Radix-4. An n bit counter is used because n bits are needed to count 2 ⁿ data. In FIG. 8A, the (n-1, n-2) th bit, the (n-3, n-4) th bit,... Reverse is performed by using a pair of the (3, 2) th bit and the (1, 0) th bit as one digit. In the present invention, it should be noted that such a reverse is called "digit reverse". As can be seen in Figure 8a it can be seen that the symmetrical reverse around the center of the digits.

8B shows the reverse order of mixed-base for a 2 ⁿ -point FFT. For mixed-odds, only two-bit digits, such as Radix-4, because the number of output power bits is odd, such as 23, 25, 27, 29, etc. It cannot be reversed. The least significant bit must be reversed separately, resulting in an asymmetrical reverse shape. Column 4 of FIG. 5 corresponding to 32 (2 ⁵ ) -points in FIG. 8B has an asymmetrical reverse form as shown in FIG. 9. In the case of having an asymmetric reverse output, the bank and address of the columns 1 and 2 are not repeated as shown in FIG. 7 configured with the Radix-4 algorithm. To have a structure in which columns 1 and 2 are repeated for continuous processing as shown in FIG. 7 using only Radix-4 in mixed-base, the output must have a symmetrical reverse form. For this purpose, a data exchange is performed in the mixed-base algorithm that converts an asymmetrical output order, such as column 4 of FIG. 5, to have a symmetrical output order, such as column 3, resulting in 32 (2 ⁵ ) -point symmetrical reverse output The order is as shown in column 3 of FIG. 5 and can be generated as shown in FIG. 10. Generalizing this, the case of 2 ⁿ -point mixed-odd FFT shows that the symmetrical reverse order of the output is shown in Fig. 11, and the upper two bits (n-1, n-2) and the lower two bits (1, 0) are digits. Reverse is performed, and bits (n-3, n-4, ..., 3, 2) are reversed in the middle. In conclusion, the asymmetric reverse form of FIG. 8B is originally converted into the symmetric reverse form of FIG. 11 through a data exchange process.

A data exchange procedure for implementing the 32-point symmetric reverse order shown in column 3 of FIG. 5 and FIG. 10 is shown in FIG. FIG. 12 corresponds to an 8-point DFT portion boxed by a thick solid line at the upper right of FIG. 5. As shown in Fig. 12, simply in stage 2, the storage positions of the outputs g'2 (n) and g'3 (n) which exist for each of the second and third of the Radix-4 butterfly are exchanged, and stage 3 Also exchanges the storage locations of the outputs X'2 (n) and X'3 (n) of the Radix-2 butterfly pair. This configuration converts the symmetrical reverse order as shown in column 1 of FIG. In FIG. 12, column 2 is shown in contrast to the asymmetric reverse order when the storage location is not exchanged as in the present invention. Such data exchange may be performed through control of the 'Exchange' signal in the butterfly circuit of FIG. 6A. Second and third outputs of the Radix-4 butterfly at all stages except the first stage in all 2 ⁿ (n = 1, 3, 5, 7, 9,…) -point FFTs as well as the example 32-point FFT It is possible to configure a symmetrical reverse output order by swapping storage locations and swapping the second and third output storage locations of the two Radix-2 butterflies in the last stage.

Finally, bank index generation in the Mixed-radix algorithm is described. The bank index generation method according to the present invention is to generate the bank index shown in the column 1 and column 2 of FIG. The bank index and address generation of each bank are generated by using an n bit counter when the FFT length is 2 ⁿ . The Radix-4 algorithm described in the prior art has a number of points such as 2 ² , 2 ⁴ , 2 ⁶ and 2 ⁸ . Therefore, bank index (bank i) generation can be obtained by modulo-4 addition for 2-bit digits. However, in the case of mixed-radix, the number of input count bits is 2 ³ , 2 ⁵ , 2 ⁷ , 2 ⁹ , etc., so that an odd number exists such as 3 bits, 5 bits, 7 bits, 9 bits, and the like. Thus, a modulo-4 addition of two bit digits alone cannot produce a bank index. In the case of mixed-radix according to the present invention, a method of generating a bank index when the number of digits of an input count bit is odd is performed through the following two processes. First, swap the positions of the most significant two bits. Secondly, the count value of the position exchange is divided into two bit digits from the lower bit, and modular-4 addition is performed on the divided two bits. The most significant 1 bit is left, and the value computed by the remainder of the most significant 1 bit and modular-4 addition is recalculated to modular-4.

A method of configuring two bits and one bit of a 32 (2 ⁵ ) -point FFT is shown in FIG. 13. When the positions of the input count bits are exchanged and the operation is performed according to the above-described method, when the operation of the modular-4 is performed, the last bit remaining in one bit corresponds to the third bit of the input data count bits. In addition, matching of bits for performing the modular-4 addition operation by 2 bits from the lower bits corresponds to (4, 2) and (1, 0). Creating a bank in this way can not only import data from other banks during the FFT operation, but also maintain the bank index order when changing from column 2 to column 1 of FIG. 5.

FIG. 14 illustrates a bank index generation method in a 2n-point mixed-radix FFT by generalizing a bank index generation method in 32-point. In FIG. 14, the separate 1-bit position of the input data count bits is the n-2 th bit, and this extra bit is included in the modulo-4 addition of 2-bit digits.

As described above, the present invention enables a high-speed operation by using a mixed-radix algorithm based on the Radix-4 algorithm. In addition, by applying an in-place operation to the mixed-radix algorithm and simultaneously performing input / output operations, two N word memories composed of four banks can be used to minimize the area used for the memory.

The calculation cycle of the FFT processor according to the present invention and the calculation cycle of the FFT processor described in the prior art are shown in comparison with Table 3 below. It can be seen from Table 3 that the computational cycle is reduced to about 1/4 compared to the conventional memory structure using the Radix-2 algorithm.

rescue Algorithm Clock Cycle N = 2,048 N = 4,096 Conventional Memory Structure Radix-2 log2N + 2 11,266 24,578 Structure of the Invention Radix-4 log4N + 6 - 6,150 Mixed-radix (Radix-4, Radix-2) log42N + 6 3,078 -

In addition, when comparing the present invention with a conventional mixed-radix FFT processor based on the Radix-4 algorithm without using a multi-bank structure, the FFT processor according to the prior art consumes about four times as many computation cycles as the present invention. .

In addition, the mixed-radix FFT processor described in the prior art, which does not adopt a structure for inputting / outputting at the same time as an in-place algorithm, requires four N word memories composed of four banks, thereby requiring two N word memories. It has twice as much memory area as the structure.

Therefore, the present invention is easy to apply to OFDM and DMT systems by satisfying not only high speed operation but also small hardware size.

As described above, using the present invention, it is easy to perform a high-speed operation in the FFT operation, there is an advantage that can be implemented through a small size of hardware.

Claims (11)

An input / output interface for performing input and output by selecting a memory for input / output among memory for input / output and FFT operation, and selecting one bank among four banks of the memory; Two N word memories consisting of four banks for input and output to the interface and FFT operations; First data for selecting a memory for FFT operation among the input / output to the interface and the memory for FFT operation and connecting the banks allocated to each butterfly input / output for in-place operation with the four inputs of the butterfly operation circuit. With exchange, A butterfly configured to perform two types of butterfly supplied from the first data exchanger in one circuit and to form a symmetrical reverse output; Second data for selecting a memory for FFT operation among the input / output to the interface unit and the memory for FFT operation and connecting the banks allocated to each butterfly input / output for in-place operation with the four outputs of the butterfly operation circuit. With exchange, And an address generator for generating a bank index and an address for performing an in-place operation in the multi-bank memory structure. The method of claim 1, The butterfly consists of four banks of N word memory configured by symmetrical reverse output order by exchanging the outputs of the Radix-4 butterfly and the two Radix-2 butterflies to perform sequential input and output simultaneously. A mixed-base modulator using a fast Fourier transform, characterized in that it is a Radix-4 / 2 butterfly arithmetic circuit capable of performing continuous processing only. The method of claim 1, The in-place algorithm is an in-place algorithm for the mixed-odd algorithm by modifying the in-place algorithm of the multi-bank memory structure of the Radix-4 algorithm. . The method of claim 1, The in-place algorithm is a modulated apparatus of the mixed-base system using fast Fourier transform, characterized in that the n-2th bit is included in modulo-4 addition separately when the 2 ⁿ -point operation in the bank index generation. In a mixed-base modulator using a fast Fourier transform, Two memories consisting of four banks for storing input symbols or for storing fast Fourier-completed symbols, A butterfly for performing a butterfly operation in radix-4 or radix-2 according to the number of symbols output from the memory, and outputting the calculated values symmetrically with reverse; A first data exchanger which reads one symbol from each bank of one of the memories and outputs the symbols to the butterfly; A second data exchanger for matching each symbol to store the symbols calculated and outputted from the butterfly at the same address as the address read from the first data exchanger; When a symbol read from the first data exchanger is output through the second data exchanger after the operation, the bank and address read from the first data exchanger and the output bank and address of the second data exchanger are the same. And an address generator for controlling the output of the second data exchanger. The method of claim 5, And an input / output interface for interfacing the two memories with the input / output data. The method of claim 5, wherein the butterfly, Mixture using a fast Fourier transform having a structure of radix-4 butterfly and configured to perform two radix-2 operations through a multiplexer provided inside the butterfly when the operation of radix-2 is required. Radix modulator. The method of claim 5, wherein the symmetrical reverse of the butterfly, Mixed-base using Fast Fourier Transform, characterized in that the binary output counter value determined by the total number of symbols for which the butterfly operation is performed is symmetrically converted into one bit unit and determined as an address. Modulator. The method of claim 8, When the number of digits of the binary output counter is an odd number, the mixed-odd modulator using a fast Fourier transform, characterized in that the symmetric conversion on the basis of the center bit of the digits to determine the address. The method of claim 5, wherein the address generator, And a modulus-based modulator using fast Fourier transform, wherein the bank is determined based on a modular-4 operation based on a binary input count bit value corresponding to the symbol to be calculated. The method of claim 10, wherein the address generator, If the number of digits of the binary input count bit is odd, the position of the most significant two bits is exchanged, the lower two bits are modulated, the modular-4 operation is performed, and the bank is determined through the replaced most significant bit and the modular-4 operation. A mixed-base modulator using a fast Fourier transform.