CN116805027A

CN116805027A - DFT multiplexing method and device, communication equipment and storage medium

Info

Publication number: CN116805027A
Application number: CN202310779863.2A
Authority: CN
Inventors: 张�杰; 吴明
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2023-06-28
Filing date: 2023-06-28
Publication date: 2023-09-26

Abstract

The invention discloses a DFT multiplexing method and device, communication equipment and storage medium, wherein the method comprises the following steps: inputting N point data, splitting the N point data according to the number of stages, and writing the split data into a memory so that a data processing module reads the N point data to perform DFT operation to obtain frequency domain data; and writing the frequency domain data back into the memory. By using the scheme of the invention, DFT with high speed and low time delay can be realized, and the resource consumption is reduced.

Description

DFT multiplexing method and device, communication equipment and storage medium

Technical Field

The present invention relates to the field of digital signal processing technologies, and in particular, to a DFT multiplexing method and apparatus, a communication device, and a storage medium.

Background

The discrete Fourier transform (Discrete Fourier Transform, DFT) is an important mathematical transform commonly used in the field of digital signal processing, and is essentially a finite discrete sampling point for Fourier transform of finite length sequences, so that the digital signal processing can use simple mathematical operation in the frequency domain, a path for frequency domain discretization is opened up, and the flexibility of digital signal processing is greatly improved. However, since the DFT is too large in calculation amount, it is difficult to process the problem in real time even with a computer for a long time, and thus it has not been widely used.

Assuming that the sequence x [ N ] has N points, the definition of N-point DFT (i.e., a signal with N Discrete points obtained at a sampling interval of 2×pi/N for Discrete Time Fourier Transform (DTFT)) is as follows:

where k=0, 1.

As can be seen from the above equation, the numbers in the DFT are complex, so that every calculation of an x (N) value requires N complex multiplications and N-1 complex additions. One complex multiplication directly spreads out and requires 4 real multiplications and 2 real additions, and one complex addition requires 2 real additions. Thus, the DFT is directly calculated, and the number of multiplications and the number of additions are both equal to N ² In proportion, when N is large, the computation amount is quite large, for example, 1024-point DFT conversion needs to multiply more than one million times, and for signal processing with strong real-time performance, the requirement on the computation speed is extremely high, so that the data computation method needs to be improved to reduce the computation times.

DFT (67 points, not the power of 2) transformation needs to be completed in a 5G system, the time delay requirement is extremely high, the resource consumption is relatively severe, and the existing DFT method cannot meet the requirement.

Disclosure of Invention

The embodiment of the invention provides a DFT multiplexing method and device, communication equipment and a storage medium, which can realize high-speed and low-delay DFT and reduce resource consumption.

In one aspect, an embodiment of the present invention provides a DFT multiplexing method, where the method includes:

inputting N point data, splitting the N point data according to the number of stages, and writing the split data into a memory so that a data processing module reads the N point data to perform DFT operation to obtain frequency domain data;

and writing the frequency domain data back into the memory.

Optionally, the data processing module includes a DFT module, where the DFT module includes an M-path DFT sub-module;

the writing of the split data into the memory includes:

writing the split data into a memory in a format of M rows and L columns according to the sequence from left to right and from top to bottom, wherein N=M×L;

the data processing module reads the N point data to perform DFT operation, and the obtaining of the frequency domain data includes:

and the M-path DFT sub-module performs M-point DFT operation on the N-point data in the memory in parallel to finally obtain the N-point frequency domain data.

Optionally, the method further comprises: and controlling the read-write operation of the memory in a ping-pong mode.

Optionally, the memory is a dual-port RAM or a ping-pong RAM.

Optionally, the M-path DFT sub-module performs M-point DFT operation on the N-point data in the memory in parallel, and finally obtaining N-point frequency domain data includes:

the M paths of DFT sub-modules simultaneously read L point data of corresponding lines from the memory to perform M point DFT operation, and each DFT sub-module sequentially performs DFT operation on the cached L point data;

and multiplying M vectorization decomposition results obtained by each round of DFT operation by a rotation factor respectively, and finally obtaining N-point frequency domain data through multiple rounds of calculation.

Optionally, the method further comprises:

setting a twiddle factor list, and storing the twiddle factor list into a ROM in advance;

and obtaining the twiddle factors of the points in a table look-up mode.

Optionally, the storing the twiddle factor list in ROM includes:

setting M paths of ROM corresponding to the M paths of DFT sub-modules;

and respectively placing the twiddle factor lists into M paths of ROM.

Optionally, the storing the twiddle factor list in ROM includes:

setting ROM corresponding to the first path DFT sub-module;

and placing the twiddle factor list in the ROM.

Optionally, the method further comprises:

reading the N-point frequency domain data from the memory;

carrying out subcarrier mapping on the N-point frequency domain data;

and performing IFFT conversion on the mapped N-point frequency domain data by using an IFFT module to obtain transmission data.

Optionally, the IFFT module and the DFT module are multiplexing structure modes.

On the other hand, the embodiment of the invention also provides a DFT multiplexing device, which comprises: the device comprises an input module, a memory and a data processing module;

the input module is used for inputting N-point data, splitting the N-point data according to the number of stages and writing the split data into the memory;

the data processing module is used for reading the N point data to perform DFT operation to obtain frequency domain data, and writing the frequency domain data back into the memory.

the input module is specifically configured to write the split data into the memory in a format of M rows and L columns according to a sequence from left to right and from top to bottom, where n=m×l;

and the M-path DFT sub-module is used for performing M-point DFT operation on the N-point data in the memory in parallel to finally obtain the N-point frequency domain data.

Optionally, the apparatus further comprises: and the memory control module is used for controlling the read-write operation of the memory in a ping-pong mode.

Optionally, the data processing module further comprises: a computing module;

the calculation module is used for multiplying the M vectorization decomposition results obtained by each round of DFT operation by a rotation factor respectively, and finally obtaining N-point frequency domain data through multiple rounds of calculation.

Optionally, the apparatus further comprises: m paths of storage units corresponding to the M paths of DFT sub-modules or storage units corresponding to the first paths of DFT sub-modules, wherein a twiddle factor list is stored in the storage units;

the calculation module is further configured to search the twiddle factor list to obtain twiddle factors of corresponding points.

On the other hand, the embodiment of the invention also provides a communication device, which comprises the DFT multiplexing device.

In another aspect, an embodiment of the present invention further provides a computer readable storage medium having a computer program stored thereon, where the computer program when executed by a processor performs the steps of the DFT multiplexing method described above.

In another aspect, an embodiment of the present invention further provides a communication device, including a memory and a processor, where the memory stores a computer program that can be run on the processor, and the processor executes the steps of the DFT multiplexing method described above when running the computer program.

According to the DFT multiplexing method and device, the communication equipment and the storage medium, the input N-point data are split according to the number of stages, the split data are written into the memory, the data processing module reads the N-point data to perform DFT operation, frequency domain data are obtained, the obtained frequency domain data are written back into the same memory, multiplexing of the input data and the write-back data to the same memory is achieved, storage resources are effectively saved, and resource consumption is reduced.

Furthermore, a read-write operation is needed in the DFT operation process, so that the read-write operation of the memory is controlled by adopting a ping-pong mode, and the memory chip is divided into two blocks to realize the ping-pong operation under the condition of not increasing the size of the memory, thereby conveniently realizing the read-write control of the multiplexing memory.

Further, by setting the M paths of parallel DFT sub-modules, the input N-point data is stored in the memory according to the corresponding format, and correspondingly, the corresponding L-point data is read from the memory and cached in the corresponding M paths of DFT sub-modules, so that the M paths of DFT sub-modules can perform corresponding operation in parallel, and simultaneously, each path of DFT sub-modules performs serial operation on the L-point data, and the DFT sub-modules have the same data flow form, thereby realizing multiplexing of resources to the greatest extent, improving the DFT operation speed, further reducing the processing time of a communication link and reducing the resource consumption.

Further, twiddle factors corresponding to the points are written into a twiddle factor list, and the twiddle factor list is preset in a storage unit such as a ROM, so that twiddle factors corresponding to the points can be conveniently acquired in a searching mode.

Further, considering that a certain common multiple relation exists between twiddle factors corresponding to different points, only twiddle factors of partial points are written in a twiddle factor list, twiddle factors of other points are obtained through table lookup and calculation, and therefore ROM resource consumption can be reduced.

Further, since the IFFT operation after the DFT operation may have the same structure as that of the plurality of parallel DFT sub-modules, the DFT module and the IFFT module may be integrated together to realize multiplexing of logic resources.

Drawings

FIG. 1 is a schematic diagram showing a comparison of a conventional OFDM waveform and a DFT-S-OFDM waveform generation process;

FIG. 2 is a schematic diagram of a data processing procedure for adding DFT-S-OFDM in the uplink;

FIG. 3 is a flowchart of a DFT multiplexing method according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a storage structure of 540 points in a memory according to an embodiment of the present invention;

FIG. 5 is a diagram of extracted data when 6-point DFT is performed on the 540-point data in FIG. 4;

FIG. 6 is a diagram of extracted data when 10-point DFT is performed on the 540-point data in FIG. 4;

FIG. 7 is a diagram of extracted data when 9-point DFT is performed on the 540-point data in FIG. 4;

FIG. 8 is a schematic diagram of phase timing relationships of different points;

fig. 9 is a schematic structural diagram of a DFT multiplexing device according to an embodiment of the present invention;

fig. 10 is a schematic hardware structure of a communication device according to an embodiment of the present invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

The Prime-factor FFT algorithm algorithm (PFA) is a fast fourier transform (Fast Fourier Transform, FFT) that takes n=n ₁ N ₂ The discrete fourier transform of size is re-denoted as N ₁ ×N ₂ Two-dimensional discrete fourier transform of size, where N ₁ And N ₂ Mutual quality is required. Becomes N ₁ And N ₂ After the fourier transform of size, the PFA may continue to be used recursively, or calculated using other fast fourier transform algorithms. At present, PFA is the most effective non-2 power FFT algorithm, and adopts a nested multidimensional structure, so that the computational complexity can be effectively reduced.

The conventional orthogonal frequency division multiplexing (Orthogonal Frequency Division Multiplexing, OFDM) waveform maps the frequency domain data directly onto the subcarriers at the transmitting end, and transforms to the time domain through an inverse fast fourier transform (Inverse Fast Fourier Transform, IFFT) of N points. Because the user side has higher requirements on the Peak-to-AverageRatio, PAR (Peak-to-average) ratio of the transmitted signal, compared with the traditional OFDM waveform, the uplink DFT Spread OFDM waveform (DFT-Spread OFDM, DFT-S-OFDM) has an additional DFT operation at the transmitting end, as shown in fig. 1, when the user side transmits the time domain data, the user side firstly transforms the time domain data to the frequency domain through the DFT of M points, and then through the IFFT of N points after subcarrier mapping, so that the uplink transmitted signal has single carrier characteristics and the Peak-to-average ratio of the signal can be reduced.

DFT conversion needs to be done in 5G systems and FFT/IFFT processors need to be employed to implement OFDM conversion and inverse conversion of the signal. For the transmitting device and the receiving device, the ultra-low latency characteristics need to be satisfied and the resource consumption is as small as possible.

The DFT-S-OFDM technology is added to the uplink of the New Radio (NR)/long term evolution (Long Term Evolution, LTE) system, which can be equivalently that the input data is subjected to IFFT processing after DFT, and the obtained result is subjected to decision feedback equalizer (Decision Feedback Equalizer, DFE) and finally output to the next module, where the data processing process is shown in fig. 2. The number of DFT points in FIG. 2 is smaller than the number of IFFT points, and the shortage is complemented by 0. And where DFT is not arbitrarily counted, but is regularly 2 in the communication protocol ^α ，2 ^β ，2 ^γ The products are combined, wherein alpha, beta and gamma are non-negative integers. This provides for implementing the DFT using a fast algorithm.

Therefore, the DFT multiplexing method, the device, the communication equipment and the storage medium adopt a plurality of parallel DFT sub-modules to decompose and process data in parallel, namely, original DFT data is divided into a plurality of DFT sub-data with the same length, the DFT operation is simultaneously carried out by the corresponding plurality of parallel DFT sub-modules, the parallel DFT sub-modules have the same data flow form, and small-point DFT is carried out at the last stage or the first stage, so that the calculation method is simplified, the calculation speed is improved, and the DFT with high speed and low time delay is realized.

Similarly, the IFFT after DFT is processed by adopting a plurality of parallel IFFT sub-modules with the same structure, so that the DFT module and the IFFT module can be integrated into one module, or one DFT sub-module and one corresponding IFFT sub-module are integrated into one sub-module, thereby realizing multiplexing of logic resources and reducing resource consumption.

The number of DFT in NR amounts to 67, specifically 6, 12, 18, 24, 30, 36, 48, 54, 60, 72, 90, 96, 108, 120, 144, 150, 162, 180, 192, 216, 240, 270, 288, 300, 324, 360, 384, 432, 450, 480, 486, 540, 576, 600, 648, 720, 750, 768, 864, 810, 900, 960, 972, 1080, 1152,1200,1296,1350, 1440,1458, 1500, 1536,1620, 1728, 1800, 1920, 1944, 2160, 2304, 2400, 2592, 2700, 2880, 2916, 3000, 3072, 3240.

The small-point DFT (i.e. the point processed by each DFT submodule) should be kept as small as possible when splitting the points, otherwise the consumed resources become large.

Taking 90 points as an example, serial operations are assumed.

If the normal decomposition is performed on four stages of 2×3×3×5, the operation time is 2×3×3×5 beats for base 2, 2×3×3×5 beats for base 3, 2×3×3×5 beats for base 5, and 90×4 (stages) =360 beats in total.

The number of points calculated at each stage is large and is decomposed into 9×10 two stages, and the calculation time is 9×10 beats for the base 9, 9×10 beats for the base 10, and 90×2 (stages) =180 beats in total.

Therefore, the larger the base number is, the fewer the number of stages is, so that the operation speed of the DFT sub-module can be improved, and the read-write times of the memory can be reduced.

The combination of dividing N points into small points is substituted into a formula, and the principle of reducing the operand by grouping division is combined with an FFT (fast Fourier transform) algorithm

Wherein n is input ₁ ＝0,1,...,N ₁ -1，n ₂ ＝0,1,...,N ₂ -1..output k ₁ ＝0,1,...,K ₁ -1，k ₂ ＝0,1,...,K ₂ -1，...。

The upstream communication protocol explicitly states that the number of DFT points N is 2 ^α ，2 ^β ，2 ^γ The combination is combined, and the combined resource allocation is performed by taking a resource block or a half resource block as a unit, and the DFT to be performed can be seen to contain a factor of 6. To increase the speed of the upstream DFT, it is considered to divide the original DFT into 6 DFT sub-modules of the same length.

Based on the above formula, the following formula can be obtained:

firstly, 6-point DFT is made, and the formula is as follows:

TABLE 1

n ₂

0

1

2

3

...

M-1

Data0

0

1

2

3

...

M-1

Data1

M

M+1

M+2

M+3

...

2M-1

Data2

2M

2M+1

2M+2

2M+3

...

3M-1

Data3

3M

3M+1

3M+2

3M+3

...

4M-1

Data4

4M

4M+1

4M+2

4M+3

...

5M-1

Data5

5M

5M+1

5M+2

5M+3

...

6M-1

6 points multiplied by different twiddle factorsThe twiddle factor for each pass is then shown in table 2 below:

TABLE 2

Then, the operation becomes a 6-way DFT sub-module as follows:

it will be seen that these 6 DFT sub-modules will have the same data stream form, except that a 6-point DFT is required to be performed once in the last stage or first stage to ensure compliance with the split-into-6-way formula.

Based on the above principle, a flowchart of the DFT multiplexing method provided by the embodiment of the present invention is shown in fig. 3, and includes the following steps:

step 301, inputting N-point data, splitting the N-point data according to a series, and writing the split data into a memory, so that a data processing module reads the N-point data to perform DFT operation to obtain frequency domain data;

step 302, writing the frequency domain data back into the memory.

The memory may be RAM (Random Access Memory ) or other module or unit with similar memory functions.

The memory may be a dual port RAM or a ping-pong RAM.

In one non-limiting embodiment, the data processing module may include a DFT module including an M-way DFT sub-module.

Accordingly, in step 301, the split data may be written into the memory according to a certain format. For example, the split data is written into the memory in a format of M rows and L columns in the order from left to right and from top to bottom, where n=m×l. In this way, the subsequent processing of the DFT sub-module is facilitated.

For example, for 48-point data, the data can be broken down into 6×8, so that the 6-way DFT submodules can simultaneously read the 8-point data cache of the corresponding row from the memory and perform 6-point DFT operation, and then each DFT submodule sequentially performs DFT operation on the cached 8-point data to obtain 6 vectorization decomposition results.

For another example, for 90-point data, the data can be split into 6×15, so that the 6-way DFT submodules can simultaneously read 15-point data caches of corresponding lines from the memory and perform 6-point DFT operation, and then each DFT submodule sequentially performs DFT operation on the cached 15-point data to obtain 6 vectorization decomposition results.

In the embodiment of the invention, the M-path DFT sub-module performs M-point DFT operation on the N-point data in the memory in parallel to finally obtain the N-point frequency domain data. Specifically, the M-path DFT sub-modules simultaneously and respectively read L-point data of corresponding lines from the memory to perform M-point DFT operation, and each DFT sub-module sequentially performs DFT operation on the cached L-point data to obtain M vectorization decomposition results. The M-path DFT sub-modules of each round of DFT operation are performed synchronously.

Taking 540-point data as an example, it can be decomposed into: 6×90, 90 can also be decomposed into 10×9 in order to minimize the number of points processed by each DFT sub-module.

Therefore, 6-path DFT sub-modules can be used for simultaneously and parallelly making 6-point DFT, then each DFT sub-module is used for serially making 90-point DFT, and 6 vectorization decomposition results are obtained after the round of polling is completed. Because the positions of the data read each time between the DFT sub-modules are the same (i.e. the same columns are read according to the clock beats between the DFT sub-modules), the data storage positions corresponding to each DFT sub-module can be combined into a large storage unit in bit width.

Taking 540 point data as an example, the bit width of the memory cell corresponding to each DFT sub-module may be set to 90 (the unit is the bit occupied by each data), that is, the memory is set to a 6×90 memory structure, and 540 point data is written into the memory in the 6×90 structure, as shown in fig. 4. Of course, 6 small memories may be used, i.e. one memory is written to each row in fig. 4, which is not limited to the embodiment of the present invention.

In order to reduce the consumption of resources, the number of points should be split to keep the small number of points DFT as much as possible, so that the L-point data buffered in each DFT submodule may be split into l=l1×l2, and accordingly, when the serial DFT operation is performed, the L1-point DTF operation is performed first, then the L2-point DFT operation is performed, and after the L-point DFT operation is completed, M first operation results are obtained.

Taking 540-point data as shown in fig. 4 as an example, splitting the 540-point data into 6×10×9, firstly reading the data corresponding to each path by 6 DFT sub-modules to make 6-point DFT, then making 10-point DFT for each path of data in series, and then making 9-point DFT for each DFT sub-module.

Fig. 5 shows a schematic diagram of taking a 6-point DFT, fig. 6 shows a schematic diagram of taking a 10-point DFT, and fig. 7 shows a schematic diagram of taking a 9-point DFT.

Referring to fig. 5, the 6-way DFT sub-module firstly takes out the first point data from the corresponding storage units of each way and simultaneously makes a 6-point DFT;

after 6-point DFT, referring to FIG. 6, each path DFT sub-module takes one point data from 90 point data corresponding to the path cache every 9 points, and makes 10-point DFT;

and then, fetching continuous 9 point data from 90 point data in each path of cache, and performing 9 point DFT.

Through the three steps, 540-point DFT can be finished.

In some cases, M vectorization decomposition results obtained by each round of DFT operation are multiplied by a twiddle factor, and N-point frequency domain data are finally obtained through multiple rounds of computation.

In a specific application, a twiddle factor list can be set, and the twiddle factor list is stored in ROM in advance, and twiddle factors of points are obtained in a table look-up mode.

In one non-limiting embodiment, ROM (Read-Only Memory) may be separately provided in the M-way DFT sub-module, and the twiddle factor list may be placed in the ROM in the M-way DFT sub-module.

Consider the feature that there is a common multiple of twiddle factors for some points, such as for the points shown in Table 3 below.

TABLE 3 Table 3

1620	1728	1800	1920	1944
					2160	2304	2400	2592	2700
2880	2916	3000	3072	3240

Wherein 1620 and 3240 may share a twiddle factor list, 1620 and the number of points below is a subset of table 3 above. These numbers are all divisible by powers of 2 or more and thus, only a twiddle factor of 1/2 or 1/4 of the number of points may be stored for each path of ROM.

For example, the power of 2, where 2700 and 2916 can be divided by integer at most, is 4, so the number of points corresponding to the twiddle factor list stored in the ROM of 2700 and 2916 can only be reduced to at most 1/4, and the other points can be divided by 8. The amount of data stored with a reduction to 1/4 is equivalent to 1/8 of 5400/5832, at which time 1800 and 1944 can be covered, so the total storage amount can become:

(1728+1800+1920+1944+2160+2304+2400+2592+5400+2880+5832+3000+3072+3240)/8=4566.

Accordingly, the phases of the last stage twiddle factors corresponding to the 6-way DFT submodule are shown in the following table 4:

TABLE 4 Table 4

As can be seen from Table 4, the twiddle factor is different for each point.

Accordingly, in one non-limiting embodiment, a ROM may be provided for each path DFT sub-module, and the twiddle factor list for the path may be pre-written to the path ROM.

In another non-limiting embodiment, only the ROM corresponding to the first path DFT sub-module may be set, and the twiddle factor list corresponding to the path may be written in the path ROM in advance. Accordingly, the phase value of each point of the next path is determined according to the phase values of the corresponding points of the previous path and the first path, namely, the two paths are added (phase addition is equal to complex multiplication), that is, the twiddle factor of each point is determined in a searching and calculating mode.

The phase timing relationship of the different points is shown in fig. 8.

According to the DFT multiplexing method provided by the embodiment of the invention, the input N-point data is split according to the number of stages, the split data is written into the memory, the data processing module reads the N-point data to perform DFT operation, frequency domain data is obtained, the obtained frequency domain data is written back into the same memory, multiplexing of the input data and the write-back data to the same memory is realized, storage resources are effectively saved, and resource consumption is reduced.

In addition, the twiddle factors corresponding to the points are obtained in a table look-up mode, so that DFT processing is facilitated, and the processing speed is increased. In addition, only partial twiddle factors of points are written in the twiddle factor list, twiddle factors of other points are obtained through table lookup and calculation, and therefore resource consumption can be further reduced.

Correspondingly, the embodiment of the invention also provides a DFT multiplexing device, as shown in FIG. 9, which is a schematic structural diagram of the device.

The device comprises: an input module 901, a memory 902, and a data processing module 903. Wherein:

the input module 901 is configured to input N-point data, split the N-point data according to a number of stages, and write the split data into the memory 902;

the data processing module 903 is configured to read the N-point data from the memory 902 to perform DFT operation, obtain frequency domain data, and write the frequency domain data back to the memory 902.

In a specific application, the memory 902 may be implemented by using a RAM or a memory module with a similar function, which is not limited to the embodiment of the present invention.

With continued reference to FIG. 9, one non-limiting structure of the data processing module 903 may include a DFT module 931, the DFT module 931 including an M-way DFT sub-module.

Accordingly, in order to facilitate the reading of the data by the M-way DFT submodule, the input module 901 may write the split data into the memory 902 in a format of M rows and L columns in order from left to right and from top to bottom, where n=m×l.

Accordingly, the M-path DFT sub-module may perform M-point DFT operation on the N-point data in the memory 902 in parallel, so as to obtain N-point frequency domain data, and the specific process of DFT operation on the data may refer to the description in the foregoing method embodiment of the present invention, which is not described herein again.

Further, to implement the read/write operation on the memory 902, the DFT multiplexing device may further include: and the memory control module (not shown) is used for controlling the read-write operation of the memory in a ping-pong manner.

With continued reference to fig. 9, the data processing module 903 may further include: a calculation module 932.

And the M paths of DFT sub-modules simultaneously read L point data of corresponding lines from the memory to perform M point DFT operation, and each DFT sub-module sequentially performs DFT operation on the cached L point data. Correspondingly, the calculation module 932 is configured to multiply the M vectorized decomposition results obtained by each round of DFT operation with a twiddle factor, and obtain N-point frequency domain data after multiple rounds of calculation.

Further, in one non-limiting embodiment, the DFT multiplexing device may further comprise: m paths of storage units corresponding to the M paths of DFT sub-modules or storage units corresponding to the first paths of DFT sub-modules, wherein a twiddle factor list is stored in the storage units.

Accordingly, the calculation module 932 may obtain the twiddle factor for the corresponding point number by looking up the twiddle factor list.

The specific implementation manner of each module and sub-module may refer to the description in the foregoing method embodiment of the present invention, and will not be repeated herein.

In one non-limiting embodiment, the apparatus further comprises: m paths of ROM corresponding to the M paths of DFT sub-modules.

In another non-limiting embodiment, the apparatus further comprises: ROM corresponding to the first path DFT sub-module.

Accordingly, a twiddle factor list is stored in the ROM, and of course, the contents of twiddle factor lists stored in the ROM set in two different ways are different, and specific reference is made to the foregoing description of the method embodiment of the present invention.

Accordingly, the data processing module 904 may obtain the twiddle factor of the corresponding point number by looking up the twiddle factor list, or obtain the twiddle factor of the corresponding point number by looking up the table and adding calculation.

In practical applications, the memory may be a dual port RAM or a ping-pong RAM.

According to the DFT multiplexing device provided by the embodiment of the invention, the input N-point data is split according to the number of stages, the split data is written into the memory, the data processing module reads the N-point data to perform DFT operation, frequency domain data is obtained, the obtained frequency domain data is written back into the same memory, multiplexing of the input data and the write-back data to the same memory is realized, storage resources are effectively saved, and resource consumption is reduced.

Furthermore, the IFFT after DFT can also adopt M IFFT sub-modules with the same structure, so that the DFT module and the IFFT module can be integrated on one module, multiplexing of logic resources is realized, and the chip area is reduced.

For example, in one non-limiting embodiment, the DFT multiplexing device may further comprise the following modules:

the mapping module is used for reading the N-point frequency domain data from the memory and carrying out subcarrier mapping on the N-point frequency domain data;

and the IFFT module is used for performing IFFT transformation on the mapped N-point frequency domain data by using the IFFT module to obtain transmission data.

The IFFT module and the DFT module are in a multiplexing structure mode.

Further, a plurality of IFFT sub-modules may be provided in the IFFT module, and perform IFFT operation on the N-point frequency domain data in parallel. Accordingly, one DFT sub-module and one IFFT sub-module can be integrated in one module, so that resource consumption can be reduced, and chip area can be saved.

Other relevant descriptions of the DFT multiplexing device may refer to those in the foregoing embodiments, and are not repeated here.

Correspondingly, the embodiment of the invention also provides communication equipment, and the terminal equipment comprises the DFT multiplexing device.

In a specific implementation, the above-mentioned apparatus may correspond to a Chip of a corresponding function in the network device and/or the user device, such as an SOC (System-On-a-Chip), a baseband Chip, a Chip module, etc.

In a specific implementation, regarding each apparatus and each module/unit included in each product described in the above embodiments, it may be a software module/unit, or a hardware module/unit, or may be a software module/unit partially, or a hardware module/unit partially.

For example, for each device or product applied to or integrated on a chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least part of the modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the rest (if any) of the modules/units may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module/unit contained in the device and product can be realized in a hardware manner such as a circuit, different modules/units can be located in the same component (such as a chip, a circuit module and the like) or different components of the chip module, or at least part of the modules/units can be realized in a software program, the software program runs on a processor integrated in the chip module, and the rest (if any) of the modules/units can be realized in a hardware manner such as a circuit; for each device, product, or application to or integrated with the terminal, each module/unit included in the device, product, or application may be implemented by using hardware such as a circuit, different modules/units may be located in the same component (for example, a chip, a circuit module, or the like) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program, where the software program runs on a processor integrated inside the terminal, and the remaining (if any) part of the modules/units may be implemented by using hardware such as a circuit.

The embodiment of the invention also discloses a storage medium, which is a computer readable storage medium, and a computer program is stored on the storage medium, and the computer program can execute all or part of the steps of the method shown in fig. 3 when running. The storage medium may include Read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic or optical disks, and the like. The storage medium may also include non-volatile memory (non-volatile) or non-transitory memory (non-transitory) or the like.

Referring to fig. 10, the embodiment of the invention further provides a hardware structure schematic diagram of the communication device. The communication device comprises a processor 1001, a memory 1002 and a transceiver 1003.

The processor 1001 may be a general purpose central processing unit (central processing unit, CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. The processor 1001 may also include a plurality of CPUs, and the processor 1001 may be one single-core (single-CPU) processor or may be a multi-core (multi-CPU) processor. A processor herein may refer to one or more devices, circuits, or processing cores for processing data (e.g., computer program instructions).

The memory 1002 may be a ROM or other type of static storage device, a RAM or other type of dynamic storage device that can store static information and instructions, or that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disk read-only memory (CD-ROM) or other optical disk storage, optical disk storage (including compact disk, laser disk, optical disk, digital versatile disk, blu-ray disk, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, as embodiments of the invention are not limited in this regard. The memory 1002 may be provided separately (in this case, the memory 1002 may be provided outside the apparatus or inside the apparatus), or may be integrated with the processor 1001. Wherein the memory 1002 may contain computer program code. The processor 1001 is configured to execute computer program code stored in the memory 1002, thereby implementing the method provided by the embodiment of the present invention.

The processor 1001, the memory 1002, and the transceiver 1003 are connected by a bus. The transceiver 1003 is used to communicate with other devices or communication networks. Alternatively, the transceiver 1003 may include a transmitter and a receiver. The means for implementing the receiving function in the transceiver 1003 may be regarded as a receiver for performing the steps of receiving in an embodiment of the invention. The means for implementing the transmit function in the transceiver 1003 may be considered a transmitter for performing the transmit steps in embodiments of the present invention.

While the schematic structural diagram shown in fig. 10 is used to illustrate the structure of the terminal device according to the above embodiment, the processor 1001 is used to control and manage the actions of the terminal device, for example, the processor 1001 is used to support the terminal device to perform the steps in fig. 3, and/or the actions performed by the terminal device in other processes described in the embodiments of the present invention. The processor 1001 may communicate with other network entities, such as with the network devices described above, through the transceiver 1003. The memory 1002 is used for storing program codes and data of the terminal device.

It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship.

The term "plurality" as used in the embodiments of the present invention means two or more.

The first, second, etc. descriptions in the embodiments of the present invention are only used for illustrating and distinguishing the description objects, and no order is used, nor is the number of the devices in the embodiments of the present invention limited, and no limitation on the embodiments of the present invention should be construed.

It should be understood that, in various embodiments of the present invention, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Embodiments of the invention may be implemented, in whole or in part, in software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions described in accordance with embodiments of the present invention are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired or wireless means. It should be understood that, in various embodiments of the present invention, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

In the several embodiments provided in the present invention, it should be understood that the disclosed method, apparatus and system may be implemented in other manners. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only one logic function division, and other division modes can be adopted in actual implementation; for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may be physically disposed separately, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.

The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform part of the steps of the method according to the embodiments of the present invention.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A DFT multiplexing method, the method comprising:

and writing the frequency domain data back into the memory.

2. The method of claim 1, wherein the data processing module comprises a DFT module comprising an M-way DFT sub-module;

the writing of the split data into the memory includes:

3. The method according to claim 1, wherein the method further comprises:

and controlling the read-write operation of the memory in a ping-pong mode.

4. The method of claim 1, wherein the memory is dual port RAM or ping pong RAM.

5. The method of claim 2, wherein the M-way DFT sub-module performs M-point DFT operations on N-point data in the memory in parallel, and finally obtaining N-point frequency domain data comprises:

6. The method of claim 5, wherein the method further comprises:

and obtaining the twiddle factors of the points in a table look-up mode.

7. The method of claim 6, wherein storing the list of twiddle factors in ROM comprises:

setting M paths of ROM corresponding to the M paths of DFT sub-modules;

and respectively placing the twiddle factor lists into M paths of ROM.

8. The method of claim 6, wherein storing the list of twiddle factors in ROM comprises:

setting ROM corresponding to the first path DFT sub-module;

and placing the twiddle factor list in the ROM.

9. The method according to any one of claims 2 to 8, further comprising:

reading the N-point frequency domain data from the memory;

carrying out subcarrier mapping on the N-point frequency domain data;

10. The method of claim 9, wherein the IFFT module and the DFT module are in a multiplexed structure mode.

11. A DFT multiplexing device, said device comprising: the device comprises an input module, a memory and a data processing module;

12. The apparatus of claim 11, wherein the data processing module comprises a DFT module comprising an M-way DFT sub-module;

13. The apparatus of claim 11, wherein the apparatus further comprises:

and the memory control module is used for controlling the read-write operation of the memory in a ping-pong mode.

14. The apparatus of claim 12, wherein the data processing module further comprises: a computing module;

15. The apparatus of claim 14, wherein the apparatus further comprises: m paths of storage units corresponding to the M paths of DFT sub-modules or storage units corresponding to the first paths of DFT sub-modules, wherein a twiddle factor list is stored in the storage units;

16. A communication device comprising DFT multiplexing means as claimed in any one of claims 11 to 15.

17. A computer readable storage medium having stored thereon a computer program, which when executed by a processor performs the steps of the DFT multiplexing method according to any of claims 1 to 10.

18. A communication device comprising a memory and a processor, the memory having stored thereon a computer program executable on the processor, the processor executing the steps of the DFT multiplexing method according to any of claims 1 to 10 when the computer program is executed.