CN115080915A - Vectorized decomposition method, device, chip, chip module and storage medium - Google Patents

Abstract

The present application discloses a vectorized decomposition method, device, chip, chip module and storage medium. The method is applied to the vectorized decomposition of N-point data, and the method includes: inputting N-point data into a memory; respectively reading L-point data from the memory, and buffering them into M sub-discrete Fourier transform DFT units, N=M*L; and performing L-point DFT operations in each of the M sub-DFT units to obtain M first vectorized decomposition results. Corresponding devices, chips, chip modules and storage media are also disclosed. By adopting the solution of the present application, high-speed and low-latency DFT calculation is realized.

Description

Vectorized decomposition method, device, chip, chip module and storage medium

technical field

The present application relates to the field of computers, and in particular, to a vectorized decomposition method, device, chip, chip module and storage medium.

Background technique

In the fifth generation ( ^5th generation, 5G) communication system, it is necessary to complete discrete Fourier transform (discrete Fourier transform, DFT) (non-power of 2) transform, and fast Fourier transform (fast Fourier transform, FFT) / Inverse fast Fourier transform (inverse fast Fourier transform) is a power transform of 2, which requires extremely high latency and strict resource consumption. However, there is currently no high-speed, low-latency computing method.

SUMMARY OF THE INVENTION

The present application provides a vectorized decomposition method, device, chip, chip module and storage medium, so as to realize high-speed and low-latency DFT calculation.

In a first aspect, a vectorized decomposition method is provided, which is applied to the vectorized decomposition of N-point data, and the method includes:

Input N point data to the memory;

L points of data are respectively read from the memory, and buffered into M sub-discrete Fourier transform DFT units, where N=M*L;

L-point DFT operations are performed in each of the M sub-DFT units to obtain M first vectorized decomposition results.

In a possible implementation, the method further includes:

The M first vectorized decomposition results are respectively multiplied by a twiddle factor to obtain M second vectorized decomposition results.

In another possible implementation, the method further includes:

Perform a radix-6 butterfly operation on the M second vectorized decomposition results to obtain a third vectorized decomposition result, and store the third vectorized decomposition result in the memory.

In yet another possible implementation, the method further includes:

Perform a radix-8 butterfly operation on the M second vectorized decomposition results to obtain a fourth vectorized decomposition result, and store the fourth vectorized decomposition result in the memory.

In yet another possible implementation, the method further includes:

The M second vectorized decomposition results are stored in the memory.

In yet another possible implementation, the N is 24, the M is 6, and the L is 4; or

The N is 24, the M is 8, and the L is 3.

In yet another possible implementation, the N is 720, the M is 8, and the L is 90, and the L-point DFT operation is performed in each sub-DFT unit to obtain M first vectorization Decomposition results, including:

9 numbers are serially extracted every 10 points to perform a 9-point DFT operation to obtain the M first vectorized decomposition results.

In yet another possible implementation, the N is 720, the M is 6, the L is 120, and the L-point DFT operation is performed in each sub-DFT unit to obtain M first vectorization Decomposition results, including:

Serially extract 12 numbers every 10 points to perform a 12-point DFT operation to obtain the M first vectorized decomposition results.

In a second aspect, a vectorized decomposition device is provided, which is applied to the vectorized decomposition of N-point data, and the device includes:

Input unit, used to input N point data to the memory;

a cache unit, configured to respectively read L point data from the memory, and cache them into M sub-discrete Fourier transform DFT units, where N=M*L;

A first operation unit, configured to perform L-point DFT operation in each of the M sub-DFT units to obtain M first vectorized decomposition results.

In a possible implementation, the apparatus further includes:

The second operation unit is configured to multiply the M first vectorized decomposition results by a twiddle factor, respectively, to obtain M second vectorized decomposition results.

In another possible implementation, the apparatus further includes:

a third operation unit, configured to perform a radix-6 butterfly operation on the M second vectorized decomposition results to obtain a third vectorized decomposition result; a first storage unit, configured to store the third vectorized decomposition result to the memory.

In yet another possible implementation, the apparatus further includes:

The fourth operation unit is used for performing radix 8 butterfly operation on the M second vectorization decomposition results to obtain the fourth vectorization decomposition result; the second storage unit is used for storing the fourth vectorization decomposition result to the memory.

In yet another possible implementation, the apparatus further includes:

A third storage unit, configured to store the M second vectorization decomposition results in the memory.

In yet another possible implementation, the N is 24, the M is 6, and the L is 4; or

The N is 24, the M is 8, and the L is 3.

In yet another possible implementation, the N is 720, the M is 8, the L is 90, and the first operation unit is used to serially extract 9 numbers every 10 points to perform 9 points DFT operation to obtain the M first vectorized decomposition results.

In yet another possible implementation, the N is 720, the M is 6, the L is 120, and the first operation unit is used to serially extract 12 numbers every 10 points to perform 12 points DFT operation to obtain the M first vectorized decomposition results.

In a third aspect, a vectorization decomposition device is provided, comprising a memory, a processor, and a computer program stored on the memory and running on the processor, and the processor implements when the computer program is executed:

Input N point data to the memory;

L points of data are respectively read from the memory, and buffered into M sub-discrete Fourier transform DFT units, where N=M*L;

L-point DFT operations are performed in each of the M sub-DFT units to obtain M first vectorized decomposition results.

In a possible implementation, the processor is also used to implement:

The M first vectorized decomposition results are respectively multiplied by a twiddle factor to obtain M second vectorized decomposition results.

In another possible implementation, the processor is also used to implement:

Perform a radix-6 butterfly operation on the M second vectorized decomposition results to obtain a third vectorized decomposition result, and store the third vectorized decomposition result in the memory.

In yet another possible implementation, the processor is further used to implement:

Perform a radix-8 butterfly operation on the M second vectorized decomposition results to obtain a fourth vectorized decomposition result, and store the fourth vectorized decomposition result in the memory.

In yet another possible implementation, the processor is further used to implement:

The M second vectorized decomposition results are stored in the memory.

In yet another possible implementation, the N is 24, the M is 6, and the L is 4; or

The N is 24, the M is 8, and the L is 3.

In yet another possible implementation, the N is 720, the M is 8, and the L is 90, and the processor performs the L-point DFT operation in each sub-DFT unit to obtain M A first step of quantizing the decomposition result, including:

9 numbers are serially extracted every 10 points to perform a 9-point DFT operation to obtain the M first vectorized decomposition results.

In yet another possible implementation, the N is 720, the M is 6, and the L is 120, and the processor performs the L-point DFT operation in each sub-DFT unit to obtain M A first step of quantizing the decomposition result, including:

Serially extract 12 numbers every 10 points to perform a 12-point DFT operation to obtain the M first vectorized decomposition results.

In a fourth aspect, a chip is provided, the chip is configured to perform the method according to the first aspect or any one of the first aspects.

In a fifth aspect, a chip module is provided, including an interface component and a chip, and the chip is configured to execute the method according to the first aspect or any one of the first aspects.

In a sixth aspect, a computer-readable storage medium is provided, and a computer program or instruction is stored in the storage medium. When the computer program or instruction is executed by the vectorization decomposition device, the first aspect or the first aspect is implemented. Any of the methods described above are implemented.

Adopting the vectorized decomposition scheme provided by this application has the following beneficial effects:

When vectorizing and decomposing N-point data, input N-point data to the memory; respectively read L-point data from the memory, and buffer them into M sub-discrete Fourier transform DFT units, where N=M*L; L-point DFT operations are performed in each of the sub-DFT units to obtain M first vectorized decomposition results. High-speed, low-latency DFT calculation is realized.

Description of drawings

1 is a schematic flowchart of a vectorized decomposition method provided by an embodiment of the present application;

FIG. 2 is a schematic flowchart of a generation process of a DFT-s-OFDM symbol in NR provided by an embodiment of the present application;

FIG. 3a is a schematic structural diagram of a vectorization decomposition apparatus provided by an embodiment of the present application;

3b is a schematic structural diagram of another vectorized decomposition apparatus provided by an embodiment of the present application;

4 is a schematic diagram of a 720-point DFT operation provided by an embodiment of the present application;

5 is a schematic diagram of an incoming number flow diagram of a vectorized decomposition scheme provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram of another vectorization decomposition apparatus provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another vectorization decomposition apparatus provided by an embodiment of the present application.

Detailed ways

In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

It should be clear that the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. As used in the embodiments of this application and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

The embodiment of the present application provides a vectorized decomposition scheme, inputting N point data into a memory; respectively reading L point data from the memory and buffering them into M sub-discrete Fourier transform DFT units, where N=M*L; L-point DFT operations are performed in each of the M sub-DFT units to obtain M first vectorized decomposition results. High-speed, low-latency DFT calculation is realized.

Please refer to FIG. 1, which is a schematic flowchart of a vectorized decomposition method provided by an embodiment of the present application, and the method may include the following steps:

S101. Input N point data into a memory.

After the N-point data is acquired, the N-point data is input into the memory. The memory may be, for example, random access memory (RAM).

S102: Read L point data from the memory respectively, and buffer them into M sub-DFT units, where N=M*L.

As shown in FIG. 2 , it is a schematic diagram of the generation process of a DFT-s-OFDM symbol in NR. In Figure 2, for orthogonal frequency division multiplexing (OFDM) waveforms, modulation symbols are directly mapped to subcarriers, and the subcarrier mapped vectors are formed by IFFT and adding a cyclic prefix (CP) an OFDM symbol. For the DFT-s-OFDM waveform, the modulation symbol is first subjected to DFT, and then sub-carrier mapping is performed. The sub-carrier mapped vector is subjected to IFFT and CP is added to form a DFT-s-OFDM symbol.

As shown in Figure 2, the DFT-s-OFDM waveform contains an additional DFT operation at the transmitting device (aka "transmitter") relative to the OFDM waveform. Correspondingly, an additional inverse discrete Fourier transformation (IDFT) operation needs to be performed at the receiving device (also called a "receiver").

Therefore, DFT transformation needs to be completed in the 5G system, and a 6-point to 4096-point FFT/IFFT processor needs to be used to realize the OFDM transformation and inverse transformation of the signal. For the transmitting device and the receiving device, the DFT processor is very critical. It needs to meet the ultra-low delay characteristics of the 5G technology, and the resource consumption needs to be as little as possible. The DFT processor in this embodiment can complete the Fourier transform and Compatible with the completion of 6-point to 4096-point FFT/IFFT transformation, which is very challenging to implement.

This embodiment is applied to the vectorized decomposition of N-point data, and it is assumed that the N-point DFT contains a factor M, so the N-point DFT can be divided into M parts of the same length. M parts of the same length correspond to M sub-DFT units (sub_DFT). The M sub-DFT units have the same data stream form. Therefore, L points of data are respectively read from the memory and buffered into M sub-DFT units, where N=M*L.

For example, the N-point DFT contains a factor of 6, so the length of the DFT can be divided into 6 parts of the same length. The 6 parts of the same length correspond to 6 sub-DFT units. The 6 sub-DFT units have the same data stream form.

For another example, the FFT/IFFT of N-point data both contain a factor of 8, so the length of the DFT can be divided into 8 parts of the same length. These 8 parts of the same length correspond to 8 sub-DFT units. The 8 sub-DFT units have the same data stream form.

As shown in FIG. 3a , which is a schematic structural diagram of a vectorization decomposition apparatus provided by an embodiment of the present application, the length of the DFT is divided into 8 parts of the same length. The eight parts of the same length correspond to eight sub-DFT units (sub_DFT0 to sub_DFT7). The 8 sub-DFT units have the same data stream form. Before the vectorization decomposition, the data is input into RAM sequentially from top to bottom and from left to right. When performing vectorization decomposition, the data of the same number of points is read from RAM and buffered into the 8 sub-DFT units.

As shown in FIG. 3b , which is a schematic structural diagram of another vectorization decomposition apparatus provided by an embodiment of the present application, the length of the DFT is divided into 6 parts of the same length. The six parts of the same length correspond to six sub-DFT units (sub_DFT0 to sub_DFT5). The 6 sub-DFT units have the same data stream form. Before the vectorization decomposition, the data is input into RAM sequentially from top to bottom and from left to right. When performing vectorization decomposition, the data of the same number of points is read from RAM and buffered into the 6 sub-DFT units.

As shown in Figure 3a, there are a total of 8 sub-DFT units with the same structure. They work at the same time, which is the vectorization of DFT. As shown in Figure 3b, there are a total of 6 sub-DFT units with the same structure. They work at the same time, which is the vectorization of DFT.

Each sub-DFT unit operates in serial mode. The above-mentioned L point data read from each memory is input to each sub-DFT unit, respectively.

S103. Perform L-point DFT operations in each of the M sub-DFT units to obtain M first vectorized decomposition results.

After each sub-DFT unit acquires L-point data, L-point DFT operations are performed in the sub-DFT unit to obtain M first vectorized decomposition results.

The M sub-DFT units perform L-point DFT operations respectively in parallel.

After one or more rounds of operations, the DFT points corresponding to each buffer are calculated.

Further, the method may also include the following steps (represented by dotted lines in the figure):

S104: Multiply the M first vectorized decomposition results by the twiddle factors to obtain M second vectorized decomposition results.

After obtaining the first vectorized decomposition result of each sub-DFT unit, the first vectorized decomposition result may be multiplied by a twiddle factor to obtain M second vectorized decomposition results. Among them, the twiddle factor is also called the unit root of the N-point DFT operation. As shown in Fig. 3a, after obtaining the 8 first vectorized decomposition results of the 8 sub-DFT units, the 8 first vectorized decomposition results can be multiplied by a twiddle factor respectively to obtain 8 second vectorized decomposition results. As shown in Fig. 3b, after obtaining the six first vectorized decomposition results of the six sub-DFT units, the six first vectorized decomposition results can be multiplied by a twiddle factor respectively to obtain six second vectorized decomposition results.

As shown in FIG. 3a and FIG. 3b , after obtaining the second vectorized decomposition result, one of the following steps S105a or S105b is executed. Therefore, after step S104, the following steps S105a or S105b can be executed alternatively:

S105a: Perform a radix-6 butterfly operation on the M second vectorized decomposition results to obtain a third vectorized decomposition result, and store the third vectorized decomposition result in a memory.

In the last round of operation, the operation result can be directly input into the radix 6 butterfly operation node (rdx6), which reduces the write-back and extraction of data. Obviously, rdx6 is a parallel operation structure, and the operation result is directly written back to the memory to obtain the final operation result.

For example, for a 6-point to 4096-point FFT/IFFT, the last round of operation will be an rdx6 operation with a factor of 6; for a DFT (not a power of 2) transformation, the last round of operation can be an operation of rdx6.

After the above vectorized decomposition, the hardware structure will be regularized, and the data does not need to be packaged multiple times. The rdx6 of the last round of operation will realize resource multiplexing.

Exemplarily, step S105a may also be replaced by: performing a radix-8 butterfly operation on the M second vectorization decomposition results to obtain a fourth vectorization decomposition result, and storing the fourth vectorization decomposition result in a memory.

In the last round of operation, the operation result can be directly input into the radix 8 butterfly operation node (rdx8), which reduces the write-back and extraction of data. Obviously, rdx8 is a parallel operation structure, and the operation result is directly written back to the memory to obtain the final operation result.

For example, for a 6-point to 4096-point FFT/IFFT, the last round of operation will be an rdx8 operation with a factor of 8; for a DFT transform, the last round of operation can be an operation of rdx8.

After the above vectorized decomposition, the hardware structure will be regularized, and the data does not need to be packaged multiple times. The rdx8 of the last round of operation will realize resource multiplexing.

S105b: Store the M second vectorization decomposition results in the memory.

As shown in Figure 3a or Figure 3b, if the rdx8 or rdx6 operation is not required, after obtaining the second vectorized decomposition result, the data can be written back directly, and the second vectorized decomposition result can be stored in the corresponding sub-DFT unit. memory.

Wherein, after step S105a or S105b is performed, one channel is selected to write back the vectorized decomposition result to the memory.

An example is given below:

In one example, N=24. For a 24-point DFT, it can be decomposed into 3*8 and 4*6. Here is a brief description of the DFT vectorization decomposition operation process by decomposing into 4*6: read 6 RAMs at the same time, and serially send the read data to sub_DFT0, sub_DFT1, sub_DFT2, sub_DFT3, sub_DFT4, sub_DFT5. The 6 sub-DFT units process 4-point DFT operations serially respectively. The operation result is multiplied by the twiddle factor and then sent to rdx6 at the same time, and the parallel operation result is written back to 6 RAMs at the same time. By adopting this method, the processing time of the system link is minimized and resource consumption is saved.

In another example, N=720. As shown in FIG. 4 , which is a schematic diagram of a 720-point DFT operation provided by an embodiment of the present application, for a 720-point DFT, it can be decomposed into 9*10*8. Its DFT vectorization decomposition operation process is as follows: First, each RAM must complete the 90-point DFT operation serially. Specifically, firstly extract 9 numbers every 10 points to do 9-point DFT, and do 10 9-point DFT in total, multiply the calculation result by the twiddle factor serially and write back to the memory (RAM0~RAM7 as shown in the figure). ). Then, sequentially and serially extract 10 points of data to do 10-point DFT, and do 9 10-point DFTs in total. The calculation results are multiplied by the twiddle factor and sent to the original (primitive) rdx module for 8-point parallel DFT operation, and the operation results are written back in parallel 8 On-chip RAM (RAM0 to RAM7 as shown in the figure).

In yet another example, N=720. For a 720-point DFT, it can be decomposed into 6*10*12. Its DFT vectorization decomposition operation process is as follows: First, each RAM must first complete the 120-point DFT operation serially. Specifically, 12 numbers are serially extracted every 10 points to do 12-point DFT, and 10 12-point DFTs are performed in total. The calculation result is serially multiplied by the twiddle factor and written back to the memory. Then, sequentially and serially extract 12-point data to do 12-point DFT, and do 9 10-point DFT in total. The calculation result is multiplied by the twiddle factor and sent to the primitive rdx module for 6-point parallel DFT operation, and the operation result is written back to 6 slices of RAM in parallel.

As shown in FIG. 5 , it is a schematic diagram of an incoming flow diagram of a vectorized decomposition solution provided by an embodiment of the present application. It is assumed that the length of the DFT is divided into 8 parts of the same length, and the 8 parts of the same length correspond to 8 RAMs (RAM0 to RAM7). Before the vectorized decomposition, the data is input into 8 RAMs in order from top to bottom and left to right. In the above example, when the data is sequentially and serially extracted, the data is sequentially and serially extracted according to the order in which the data is input.

The processing flow of the above 24-point DFT and 720-point DFT is just an example, and the processing flow of other points is similar.

As shown in Table 1 below, the decomposition of some DFT points for the example:

Table 1

It can be seen that the above DFT contains a factor of 6 or 8 after the point decomposition. There are 67 types of points, and the minimum number of supported points is 6. Therefore, a similar DFT vector decomposition structure described above can be used for vector decomposition.

According to a vectorization decomposition method provided by an embodiment of the present application, input data of N points into a memory; read data of L points from the memory, respectively, and buffer them into M buffers, where N=M*L; The L-point data read by each buffer in the buffer is respectively input to the sub-DFT unit corresponding to each buffer; and L-point DFT operation is performed in each sub-DFT unit to obtain M first vectorized decomposition results. High-speed, low-latency DFT calculation is realized.

It can be understood that, in order to realize the functions in the above embodiments, the vectorization decomposition apparatus includes corresponding hardware structures and/or software modules for performing each function. Those skilled in the art should easily realize that the units and method steps of each example described in conjunction with the embodiments disclosed in the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is performed by hardware or computer software-driven hardware depends on the specific application scenarios and design constraints of the technical solution.

FIG. 6 and FIG. 7 are schematic structural diagrams of a possible vectorization decomposition apparatus provided by an embodiment of the present application. These vectorization decomposition apparatuses can be used to implement the functions of the vectorization decomposition apparatuses in the foregoing method embodiments, and thus can also achieve the beneficial effects possessed by the foregoing method embodiments. In the embodiments of the present application, the vectorized decomposition apparatus may be an electronic device, or may be a module (eg, a chip or a chip module) applied to the electronic device. Exemplarily, the vectorization decomposition device may be a modem in a communication system.

Please refer to FIG. 6 , which is a schematic structural diagram of another vectorized decomposition apparatus provided by an embodiment of the present application. The apparatus 600 includes:

Input unit 601, for inputting N point data to memory;

a buffering unit 602, configured to read data of L points from the memory respectively, and buffer them into M sub-DFT units, where N=M*L;

The first operation unit 603 is configured to perform L-point DFT operation in each of the M sub-DFT units to obtain M first vectorized decomposition results.

In a possible implementation, the apparatus further includes (indicated by dotted lines in the figure):

The second operation unit 604 is configured to multiply the M first vectorized decomposition results by a twiddle factor, respectively, to obtain M second vectorized decomposition results.

In another possible implementation, the apparatus further includes (indicated by dotted lines in the figure):

The third operation unit 605 is configured to perform a radix-6 butterfly operation on the M second vectorized decomposition results to obtain a third vectorized decomposition result; the first storage unit 606 is configured to perform the third vectorized decomposition The results are stored to the memory.

In yet another possible implementation, the apparatus further includes (not shown in the figure):

a third operation unit, configured to perform a radix-8 butterfly operation on the M second vectorized decomposition results to obtain a fourth vectorized decomposition result; a second storage unit, configured to store the fourth vectorized decomposition result to the memory.

In yet another possible implementation, the apparatus further includes (indicated by dotted lines in the figure):

The third storage unit 607 is configured to store the M second vectorization decomposition results in the memory.

In yet another possible implementation, the N is 24, the M is 6, and the L is 4; or

The N is 24, the M is 8, and the L is 3.

In yet another possible implementation, the N is 720, the M is 8, the L is 90, and the first operation unit 603 is configured to serially extract 9 numbers every 10 points to perform 9 Point DFT operation to obtain the M first vectorized decomposition results.

In yet another possible implementation, the N is 720, the M is 6, the L is 120, and the first operation unit 603 is configured to serially extract 12 numbers every 10 points to perform 12 Point DFT operation to obtain the M first vectorized decomposition results.

For the specific implementation of the above units, reference may be made to the description of the embodiment shown in FIG. 1 , which will not be repeated here.

According to a vectorization decomposition device provided by an embodiment of the present application, N points of data are input into a memory; L points of data are respectively read from the memory, and buffered into M sub-DFT units, where N=M*L; L-point DFT operations are performed in each sub-DFT unit in the unit to obtain M first vectorized decomposition results. High-speed, low-latency DFT calculation is realized.

Please refer to FIG. 7 , which is a schematic structural diagram of another vectorized decomposition apparatus provided by an embodiment of the present application. The apparatus 700 includes at least a processor 701 , an input device 702 , an output device 703 and a computer storage medium 704 . The processor 701 , the input device 702 , the output device 703 and the computer storage medium 704 in the apparatus may be connected through a bus or other means.

A computer storage medium 704 may be stored in the memory of the device, the computer storage medium 704 for storing a computer program including program instructions, and the processor 701 for executing the program instructions stored in the computer storage medium 704 . The processor 701 is the computing core and the control core of the device, which is suitable for implementing one or more instructions, and specifically suitable for loading and executing one or more instructions to implement corresponding method processes or corresponding functions.

In one embodiment, the processor 701 described in this embodiment of the present application may be configured to load and execute the method steps in the embodiment shown in FIG. 1 .

Specifically, when the processor 701 executes the computer program, it realizes:

Input N point data to the memory;

L points of data are respectively read from the memory and buffered into M sub-DFT units, where N=M*L;

L-point DFT operations are performed in each of the M sub-DFT units to obtain M first vectorized decomposition results.

In a possible implementation, the processor 701 is further configured to implement:

The M first vectorized decomposition results are respectively multiplied by a twiddle factor to obtain M second vectorized decomposition results.

In another possible implementation, the processor 701 is further configured to implement:

Perform a radix-6 butterfly operation on the M second vectorized decomposition results to obtain a third vectorized decomposition result, and store the third vectorized decomposition result in the memory.

In yet another possible implementation, the processor 701 is further configured to implement:

Perform a radix-8 butterfly operation on the M second vectorized decomposition results to obtain a fourth vectorized decomposition result, and store the fourth vectorized decomposition result in the memory.

In yet another possible implementation, the processor 701 is further configured to implement:

The M second vectorized decomposition results are stored to each of the memories.

In yet another possible implementation, the N is 24, the M is 6, and the L is 4; or

The N is 24, the M is 8, and the L is 3.

In yet another possible implementation, the N is 720, the M is 8, and the L is 90, and the processor 701 performs the L-point DFT operation in each sub-DFT unit to obtain The M steps of the first vectorized decomposition result include:

9 numbers are serially extracted every 10 points to perform a 9-point DFT operation to obtain the M first vectorized decomposition results.

In yet another possible implementation, the N is 720, the M is 6, and the L is 120, and the processor 701 performs the L-point DFT operation in each sub-DFT unit to obtain The M steps of the first vectorized decomposition result include:

Serially extract 12 numbers every 10 points to perform a 12-point DFT operation to obtain the M first vectorized decomposition results.

According to a vectorization decomposition device provided by an embodiment of the present application, N points of data are input into a memory; L points of data are respectively read from the memory, and buffered into M sub-DFT units, where N=M*L; L-point DFT operations are performed in each sub-DFT unit in the unit to obtain M first vectorized decomposition results. High-speed, low-latency DFT calculation is realized.

It should be noted that, one or more of the above units or units may be implemented by software, hardware or a combination of both. When any of the above units or units are implemented in software, the software exists in the form of computer program instructions and is stored in the memory, and the processor can be used to execute the program instructions and implement the above method flow. The processor may be built in a system on chip (system on chip, SoC) or an application specific integrated circuit (application specific integrated circuit, ASIC), or may be an independent semiconductor chip. The internal processing of the processor is used for executing software instructions to perform operations or processing, and may further include necessary hardware accelerators, such as field programmable gate array (FPGA), programmable logic device (programmable logic device). , PLD), or a logic circuit that implements dedicated logic operations.

When the above units or units are implemented in hardware, the hardware may be a CPU, a microprocessor, a digital signal processing (DSP) chip, a microcontroller unit (MCU), an artificial intelligence processor, an ASIC, Any or any combination of SoCs, FPGAs, PLDs, dedicated digital circuits, hardware accelerators, or non-integrated discrete devices that may or may not run the necessary software to perform the above method flows.

Regarding each module/unit included in each device and product described in the above-mentioned embodiments, it may be a software module/unit or a hardware module/unit; or may be partly a software module/unit and partly a hardware module/unit . For example, for each device or product applied to or integrated in a chip, each module/unit included therein may be implemented by hardware such as circuits, or at least some of the modules/units may be implemented by a software program. Running on the processor integrated inside the chip, the remaining (if any) part of the modules/units can be implemented by hardware such as circuits; for each device and product corresponding to or integrated in the chip module, the modules/units contained therein can be They are all implemented by hardware such as circuits, and different modules/units can be located in the same component of the chip module (such as chips, circuit modules, etc.) or in different components, or at least some of the modules/units can be implemented by software programs. The software program runs on the processor integrated inside the chip module, and the remaining (if any) part of the modules/units can be implemented by hardware such as circuits; for each device and product applied to or integrated in the terminal, each module contained in it The units/units may all be implemented in hardware such as circuits, and different modules/units may be located in the same component (eg, chip, circuit module, etc.) or in different components in the terminal, or at least some of the modules/units may be implemented by software programs Realization, the software program runs on the processor integrated inside the terminal, and the remaining (if any) part of the modules/units can be implemented in hardware such as circuits.

The method steps in the embodiments of the present application may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions. Software instructions may be composed of corresponding software modules, and software modules may be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory memory, registers, hard disk, removable hard disk, CD-ROM or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium may reside in an ASIC. Alternatively, the ASIC may be located in an access network device or terminal. Of course, the processor and the storage medium may also exist in the access network device or terminal as discrete components.

In the above-mentioned embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented in software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are executed in whole or in part. The computer may be a general purpose computer, special purpose computer, computer network, access network equipment, user equipment, or other programmable apparatus. The computer program or instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instructions may be downloaded from a website site, computer, A server or data center transmits by wire or wireless to another website site, computer, server or data center. The computer-readable storage medium may be any available media that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable media may be magnetic media, such as floppy disks, hard disks, magnetic tapes; optical media, such as digital video discs; and semiconductor media, such as solid-state drives.

In the various embodiments of the present application, if there is no special description or logical conflict, the terms and/or descriptions between different embodiments are consistent and can be referred to each other, and the technical features in different embodiments are based on their inherent Logical relationships can be combined to form new embodiments.

In this application, "at least one" means one or more, and "plurality" means two or more. "And/or", which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can indicate: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural. In the text description of this application, the character "/" generally indicates that the related objects are a kind of "or" relationship; in the formula of this application, the character "/" indicates that the related objects are a kind of "division" Relationship.

It can be understood that, the various numbers and numbers involved in the embodiments of the present application are only for the convenience of description, and are not used to limit the scope of the embodiments of the present application. The size of the sequence numbers of the above processes does not imply the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic.

Claims (14)

1. A vectorization decomposition method applied to vectorization decomposition of N-point data, the method comprising:

inputting N point data to a memory;

respectively reading L point data from the memories, and caching the L point data to M sub Discrete Fourier Transform (DFT) units, wherein N is M L;

and performing L-point DFT operation in each sub DFT unit of the M sub DFT units to obtain M first vector quantization decomposition results.

2. The method of claim 1, further comprising:

and multiplying the M first vector quantization decomposition results by a twiddle factor respectively to obtain M second vector quantization decomposition results.

3. The method of claim 2, further comprising:

performing radix-6 butterfly operation on the M second vectorial decomposition results to obtain a third vectorial decomposition result;

storing the third vectorized decomposition result to the memory.

4. The method of claim 2, further comprising:

performing radix-8 butterfly operation on the M second directional quantized decomposition results to obtain a fourth directional quantized decomposition result;

storing the fourth direction quantized decomposition result to the memory.

5. The method of claim 2, further comprising:

storing the M second quantized decomposition results to the memory.

6. A vectorization decomposition apparatus applied to vectorization decomposition of N-point data, the apparatus comprising:

an input unit for inputting the N-point data to the memory;

the cache unit is used for respectively reading L point data from the memory and caching the L point data to M sub Discrete Fourier Transform (DFT) units, wherein N is M L;

and the first operation unit is used for performing L-point DFT operation in each sub-DFT unit in the M sub-DFT units to obtain M first vector quantization decomposition results.

7. The apparatus of claim 6, further comprising:

and the second operation unit is used for multiplying the M first vector quantization decomposition results by twiddle factors respectively to obtain M second vector quantization decomposition results.

8. The apparatus of claim 7, further comprising:

the third operation unit is used for carrying out radix-6 butterfly operation on the M second vectorization decomposition results to obtain a third vectorization decomposition result;

a first storage unit to store the third vectorized decomposition result to the memory.

9. The apparatus of claim 7, further comprising:

the fourth operation unit is used for carrying out radix-8 butterfly operation on the M second directional quantized decomposition results to obtain a fourth directional quantized decomposition result;

a second storage unit, configured to store the fourth directional quantized decomposition result in the memory.

10. The apparatus of claim 7, further comprising:

a third storage unit, configured to store the M second quantized decomposition results into the memory.

11. A vectorization decomposition apparatus comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method according to any of claims 1 to 5 when executing the computer program.

12. A chip for performing the method of any one of claims 1-5.

13. A chip module comprising an interface component and a chip for performing the method of any one of claims 1-5.

14. A computer-readable storage medium, in which a computer program or instructions are stored which, when executed by a vectorization decomposition apparatus, implement the method according to any one of claims 1 to 5.

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