KR100697539B1 - Apparatus of parallel signal processing in high-speed wideband modem - Google Patents

Abstract

A parallel processing apparatus of a high speed wideband modem signal is provided to simplify wideband modem design and to reduce power consumption by processing fast-transmitted/received data in parallel with a low speed in the wideband modem. In a parallel processing apparatus of a high speed wideband modem signal, a receiver part comprises a serial/parallel conversion part(220) to convert A bit serial data of a digitally-converted base band signal into N number of A bit parallel data to reduce an operation frequency to 1/N, and a first storing part(230) storing N number of A bit parallel data outputted from the serial/parallel conversion part, and more than one demodulation part performing demodulation as to the N number of A bit parallel data. A transmitter part comprises more than one modulation part performing modulation as to the N number of A bit parallel data, and a second storing part storing the N number of A bit parallel modulation data, and a parallel/serial conversion part converting the N number of A bit parallel modulation data into N number of A bit serial modulation data by increasing the operation frequency to N.

Description

Parallel Processing Unit for High-Speed Broadband Modem Signals {APPARATUS OF PARALLEL SIGNAL PROCESSING IN HIGH-SPEED WIDEBAND MODEM}

1 is an exemplary configuration diagram of a conventional MB-OFDM transceiver.

2 is an exemplary configuration diagram of a receiver in a parallel processing apparatus for a high speed broadband modem signal according to the present invention.

3 is a block diagram of a transmitter in a parallel processing apparatus for a high speed broadband modem signal according to the present invention;

4 is a diagram illustrating an exemplary internal structure and input / output data of a memory used in a receiving unit of a parallel processing apparatus for a high speed broadband modem signal according to the present invention.

Fig. 5 is a diagram showing an exemplary internal structure and input / output data of a memory used in a transmitting unit of a parallel processing apparatus for a high speed broadband modem signal according to the present invention.

<Description of the symbols for the main parts of the drawings>

110: reference PLL 120: clock generator

130: modulator 135: demodulator

140: DAC 145: ADC

150: frequency up converter 155: frequency down converter

160: drive amplifier 165: low noise amplifier

170: transmit / receive switch 180: RF filter

190: antenna 210: A / D conversion unit

220: serial / parallel converter 230: memory

240: FFT 310: D / A converter

320: parallel / serial converter 330: memory

340: IFFT

The present invention relates to a parallel processing apparatus for a high-speed broadband modem signal, and more particularly, a complicated configuration is required using a high input / output frequency in a conventional broadband modem design, thereby improving the disadvantage that power consumption is increased, thereby improving high-speed data. The present invention relates to a parallel processing apparatus for a high speed broadband modem signal for simplifying a broadband modem design and reducing power consumption by lowering an operating frequency by processing data transmitted and received at high speed in parallel in a broadband modem processing a high speed modem.

Recently, UWB (Ultra Wide Band) technology has emerged as a communication method capable of transmitting and receiving broadband multimedia contents of 100 Mbps or more in the near field. For example, considering the transmission loss and control information in the home network, the speed required for the transmission of multimedia contents is at least 10 Mbps, and the transmission of high definition (HD) multimedia contents requires a bandwidth of 19 to 24 Mbps per channel. It is expected that guarantees for transmission rates of 100 Mbps and beyond will be required.

However, among current short-range wireless technologies currently available, the wireless LAN scheme guarantees a transmission rate of up to 54 Mbps, for example, for 802.11 a / g, but is relatively expensive and has a quality of service (QoS) function required for multimedia stream transmission. In addition, Bluetooth also guarantees a bandwidth of up to 4Mbps even under the V1.2 specification.

Therefore, in order to implement a wireless networking function for multimedia contents, in particular, high definition multimedia contents, application of short-range wireless technology capable of low cost, low power, and large capacity transmission is essential.

UWB has the advantage of being able to transmit large capacity of 480Mbps or more at short distance of up to 20m, fundamentally guaranteeing QoS, and being less susceptible to signal interference due to multi-path. Due to these technical features, UWB is expected to be used mainly in multimedia home entertainment home appliances such as digital camcorders / cameras, set-top boxes, digital TVs, DVRs, MP3 players and home servers.

Standardization for the use of UWB for short-range broadband communications is primarily discussed in IEEE 802.15.3a. The main proposals currently discussed are the single-band approach to wider frequency bands and the MB-OFDM ( It can be divided into Multi-Band Orthogonal Frequency Division Multiplexing), but in multi-band communication environment such as home network, users must use a limited frequency basically, so MB-OFDM is the most realistic way to implement UWB in consideration of interference environment of various devices. It is attracting attention.

The MB-OFDM scheme has 13 bands with 528 MHz bandwidth, ie, 3.168 to 3.696 MHz band and 3.696 to 4.224 MHz band, in order to avoid interference among all the UWB frequency bands of 3.168 to 10.296 MHz, except for the 5.280 to 5.544 MHz band. It is divided into 13 bands and data is transmitted through frequency hopping in each band.

1 is an exemplary configuration diagram of an MB-OFDM transceiver. Since the MB-OFDM transceiver has not been specifically discussed in terms of standardization, only a conceptual configuration is shown, and components of coding and decoding parts and other interfaces are omitted.

The reference PLL 110 from the clock generator 120 generates a reference signal for generating the MB-OFDM signal of the signal.

In the case of the MB-OFDM transmitter, the signal generated by the modulator 130 is analog-converted through the DAC 140 and passes through the frequency up-converter 150 and the driving amplifier 160 and then the transmit / receive switch 170. It is selected by and transmitted through the RF filter 180 and the antenna 190.

In the case of the MB-OFDM receiver, the signal received from the antenna 190 and passed through the RF filter 180 is selected by the transmit / receive switch 170 and amplified through the low noise amplifier (LNA) 165 and the frequency downconverter ( The signal is converted to baseband through 155, sampled by the ADC 145, and demodulated by a demodulator 135.

In the MB-OFDM transceiver with reference to FIG. 1, data to be transmitted is transmitted using an OFDM modulation scheme in each band, for example, 3.168 to 3.696 MHz, which is expected to be commercialized first, and an OFDM carrier is transmitted through 128 IFFT or 256 IFFT. Is generated.

In the MB-OFDM broadband modems 135 and 130, the bandwidth of the transmission signal is 528 MHz, and the input / output frequency is 1056 MHz assuming twice the oversampling. In addition, assuming oversampling more than twice, the operating frequency is further increased.

Therefore, when such high-speed data is directly processed by the MB-OFDM broadband modems 135 and 130, the operating frequency of components used in the MB-OFDM broadband modems 135 and 130 becomes very high. Due to such a high operating frequency, a complicated configuration is required in the design of the MB-OFDM broadband modems 135 and 130, and the disadvantage of increasing the amount of power consumption is expected.

Accordingly, there is a growing need for a method of lowering an operating frequency, particularly in an apparatus for processing high data rate such as MB-OFDM broadband modems 135 and 130.

An object of the present invention is to improve the disadvantage that the complex configuration is required by using a high input and output frequency in the conventional broadband modem design, thereby increasing the power consumption to reduce the data transmitted and received at a high speed in a broadband modem processing high speed data at a low speed By processing in parallel, the present invention provides a parallel processing apparatus for high-speed broadband modem signals to reduce the operating frequency, simplify broadband modem design, and reduce power consumption.

In order to achieve the above technical problem, the present invention is a parallel processing apparatus of a high-speed broadband modem signal, the N (A is a natural number of two or more) bit serial data of the digitally converted baseband signal by merging N pieces of operating frequency 1 / N (N is a natural number of 2 or more) A serial / parallel conversion unit for converting to N A-bit parallel data reduced by a multiple, and a first storage unit for sequentially storing the N A-bit parallel data output from the serial / parallel conversion unit. And a receiving unit having at least one demodulating unit for performing modulation by reading the N A-bit parallel data from the first storage unit in a demodulation order; At least one modulator for modulating and outputting N A-bit parallel modulation data, a second storage unit for sequentially storing the N A-bit parallel modulation data, and the N A-bits from the second storage unit A parallel processing apparatus for a high-speed broadband modem signal including a transmitter having a parallel / serial converter for reading parallel modulated data and outputting N-bit serial modulated data of which the operating frequency is increased by N times.

In the parallel processing apparatus for a high speed broadband modem signal according to the present invention, A is preferably 4 or 6.

In the parallel processing apparatus for a high-speed broadband modem signal according to the present invention, N is preferably 4.

In the parallel processing apparatus for a high-speed broadband modem signal according to the present invention, the demodulator includes two FFT demodulators, and each of the FFT demodulators shares and modulates the N A-bit parallel data.

In the parallel processing apparatus for a high-speed broadband modem signal according to the present invention, it is preferable that the modulator includes two IFFT demodulators, each of which outputs N A-bit parallel modulated data by sharing a modulation rule. .

In the parallel processing apparatus for a high-speed broadband modem signal according to the present invention, the first storage unit is preferably composed of 2N memory blocks for storing and outputting the N A-bit parallel data.

In the parallel processing apparatus for high-speed broadband modem signals according to the present invention, the second storage unit is preferably composed of 2N memory blocks for storing and outputting the N A-bit parallel modulated data.

In the parallel processing apparatus for high-speed broadband modem signals according to the present invention, it is preferable that the high-speed broadband modem is a modem for multi-band orthogonal frequency division multiplexing (MB-OFDM).

In the parallel processing apparatus for a high-speed broadband modem signal according to the present invention, the receiver further converts the baseband signal to digital to generate the A-bit serial data and outputs the A / D converter to the serial / parallel converter. Preferably, the transmission unit further includes a D / A converter for converting the A-bit serial modulation data into an analog output.

Hereinafter, a parallel processing apparatus for a high speed broadband modem signal of the present invention will be described in more detail with reference to the accompanying drawings.

2 is an exemplary configuration diagram of a receiver in a parallel processing apparatus for a high speed broadband modem signal according to the present invention.

The configuration of the receiver shown in FIG. 2 is shown only for the characteristic part of the parallel processing apparatus for the high speed broadband modem signal according to the present invention, and the illustration of decoding related components and the like is omitted.

As shown, the receiving unit of the parallel processing apparatus for a high-speed broadband modem signal according to the present invention receives a signal after being converted to baseband by receiving a signal, for example, in the MB-OFDM transceiver described with reference to FIG. 1.

The A / D converter 210 converts the baseband converted signal into a digital signal. In this case, it is assumed that the data passed through the A / D converter 210 has a size of 6 bits. The A / D converter 210 of the high-speed broadband modem is expected to use 4 bits or 6 bits to reduce power consumption and reduce the cost, but for convenience of description, the A / D converter 210 has a data size of 6 bits. Assume that we have The data passed through the A / D converter 210 is a signal having an operating frequency of 1056 MHz.

Thereafter, the serial / parallel converter 220 collects four pieces of output data of the A / D converter 210 and converts the output data into 24-bit parallel data. In this case, the operating frequency drops to a quarter from 1056 MHz to 264 MHz. Such 24-bit parallel data is sequentially stored in the memory 230, and the 24-bit parallel data stored in the memory 230 is read and processed in consideration of the butterfly operation in the FFTs 240a and 240b performing demodulation. do.

In this case, since the FFTs (Fast Fourier Transform, 240a, 340a) can process two 6-bit data at the same time, two FFTs 240a, 340a can be used to process 24-bit data at once.

3 is a block diagram of a transmitter in a parallel processing apparatus for a high speed broadband modem signal according to the present invention.

The configuration of the transmitter shown in FIG. 3 is shown only for the characteristic part of the parallel processing apparatus of the high speed broadband modem signal according to the present invention, and the illustration of coding related components and the like is omitted.

As in FIG. 2, the D / A converter 310 converts a digital signal into a baseband. In this case, it is assumed that data passing through the D / A converter 310 has a size of 6 bits. That is, the D / A converter 310 of the high-speed broadband modem is expected to use 4 bits or 6 bits to reduce power consumption and reduce the cost, but for convenience of description, the D / A converter 310 uses 6 bits of data. Assume that it has a size. The data passed through the D / A converter 310 is a signal having an operating frequency of 1056 MHz.

 Inverse FFTs 340a and 340b perform data modulation. In this case, the output data on the IFFT is assumed to be parallel data of 24 bits in consideration of the fact that the aforementioned D / A converter 310 has a data size of 6 bits.

The memory 330 stores data output from the two IFFTs 340a and 340b. Since the 24-bit parallel data output from the IFFTs 340a and 340b are not arranged in order, they are stored in the memory 330 and addressed in consideration of the order in reading.

In this case, the 24-bit parallel data has an operating frequency of 264 MHz.

Thereafter, the parallel / serial converter 320 receives 24 bits of parallel data having an operating frequency of 264 MHz from the memory 330 and converts the serial data into 6 bits of serial data having an operating frequency of 1056 MHz.

Thereafter, the 6-bit serial data having the converted operating frequency of 1056 MHz is converted into a baseband signal through the D / A converter 340.

2 to 3, the A / D converter 210 and the D / A converter 310 are configured to be included in the parallel processing apparatus for the high speed broadband modem signal according to the present invention. It should be noted that it can be implemented in a separate configuration.

4 is a diagram illustrating an exemplary internal structure and input / output data of a memory used in a receiving unit of a parallel processing apparatus for a high speed broadband modem signal according to the present invention.

As shown, 24-bit parallel data, which is output data of the serial / parallel converter 220, is stored by 6 bits in each block 230a to 230h in the memory 230. In this case, for example, it is configured to be stored in each of the blocks 230a to 230d in the horizontal direction. Thereafter, 12 bits of parallel data are input to the FFTs 240a and 240 by 6 bits from each block 230a to 230h in the memory 230 to perform demodulation. In this case, two pieces of data are extracted from the vertical block and input to the FFTs 240a and 240. For example, the FFT 240a extracts 6-bit data from blocks 230c and 230g so that a total of 12 bits of data are input, and the FFT 240b is 6 bits from blocks 230d and 230h adjacent to the blocks 230c and 230g. Data is extracted and a total of 12 bits of data are input.

The reason that the memory 230 is divided into eight blocks 230a to 230h is that four data are simultaneously inputted and outputted, and the data input and output addressing methods are different, so it is preferable to divide the data into eight blocks for efficient data input and output. Because.

5 is a diagram illustrating an exemplary internal structure and input / output data of a memory used in a transmitting unit of a parallel processing apparatus for a high speed broadband modem signal according to the present invention.

12 bits of data input from each of the IFFTs 340a and 340b are stored in each memory block. In this case, the 12-bit output data of the IFFT 340a and the 12-bit output data of the IFFT 340b are stored in an adjacent block. For example, IFFT 340a inputs 6 bits of data into blocks 330c and 330g, and IFFT 340b inputs 6 bits of data into blocks 330d and 330h adjacent to blocks 330c and 330g. .

The data input to each block is then outputted at the same time four data is input to the parallel / serial converter 320. In this case, the outputs are simultaneously output from the horizontal blocks 30a to 30d and input to the parallel / serial conversion unit 320.

4 to 5, the memory 230 or 330 is divided into eight blocks 230a through 230h and 330a through 330h. The four data are simultaneously input and output, and the addressing method is different when inputting and outputting data. This is because it is preferable to divide the data into eight blocks for efficient data input / output.

Although the present invention has been described in detail, this is for illustrative purposes only, and the protection scope of the present invention is not limited thereto, and the protection scope of the present invention is defined through the description of the claims.

As described above, according to the present invention, a complicated configuration is required by using a high input / output frequency when designing a conventional broadband modem, thereby improving the disadvantage of increasing power consumption, thereby transmitting and receiving at a high speed in a broadband modem processing high speed data. By processing the data in parallel at low speed, the operating frequency can be lowered to simplify broadband modem design and reduce power consumption.

Claims (9)

A parallel processing unit for a high speed broadband modem signal, Serial / parallel that merges N A (A is a natural number of two or more) bit serial data of a digitally converted baseband signal into N A bit parallel data whose operating frequency is reduced by 1 / N (N is a natural number of two or more) times A conversion unit, a first storage unit for sequentially storing the N A-bit parallel data output from the serial / parallel conversion unit, and the N A-bit parallel data from the first storage unit so as to conform to the demodulation order. A receiver having at least one demodulator for reading and performing modulation; At least one modulator for modulating and outputting N A-bit parallel modulation data, a second storage unit for sequentially storing the N A-bit parallel modulation data, and the N A-bits from the second storage unit Transmitter including parallel / serial conversion section for reading parallel modulated data and outputting N-bit serial modulated data whose operating frequency is increased by N times. Parallel processing apparatus for a high-speed broadband modem signal comprising a. The method of claim 1, Wherein A is 4 or 6; The method of claim 1, N is 4, wherein the parallel processing apparatus of the high-speed broadband modem signal. The method of claim 1, The demodulator includes two FFT demodulators, Wherein each of the FFT demodulators divides and modulates the N A-bit parallel data. The method of claim 1, The modulator includes two IFFT demodulators, Wherein each of the IFFT modulators outputs N A-bit parallel modulated data by sharing a modulation rule. The method of claim 1, And the first storage unit is composed of 2N memory blocks for storing and outputting the N A-bit parallel data. The method of claim 1, And the second storage unit comprises 2N memory blocks for storing and outputting the N A-bit parallel modulated data. The method of claim 1, And said high speed broadband modem is a modem for multi-band orthogonal frequency division multiplexing (MB-OFDM). The method of claim 1, The receiving unit further comprises an A / D conversion unit for converting the baseband signal to digital to generate the A-bit serial data to output to the serial / parallel conversion unit, And the transmitter further comprises a D / A converter converting the A-bit serially modulated data into analog and outputting the analog bit.

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