KR20040002272A - A method for forming a metal line of semiconductor device - Google Patents
A method for forming a metal line of semiconductor device Download PDFInfo
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- KR20040002272A KR20040002272A KR1020020037722A KR20020037722A KR20040002272A KR 20040002272 A KR20040002272 A KR 20040002272A KR 1020020037722 A KR1020020037722 A KR 1020020037722A KR 20020037722 A KR20020037722 A KR 20020037722A KR 20040002272 A KR20040002272 A KR 20040002272A
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- forming
- metal wiring
- semiconductor device
- etching process
- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 239000002184 metal Substances 0.000 title claims abstract description 57
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000010410 layer Substances 0.000 claims abstract description 45
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims abstract description 7
- 238000000206 photolithography Methods 0.000 claims abstract description 3
- 238000001020 plasma etching Methods 0.000 claims description 22
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 claims description 3
- 239000000654 additive Substances 0.000 claims description 3
- 230000000996 additive effect Effects 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- UPSOBXZLFLJAKK-UHFFFAOYSA-N ozone;tetraethyl silicate Chemical compound [O-][O+]=O.CCO[Si](OCC)(OCC)OCC UPSOBXZLFLJAKK-UHFFFAOYSA-N 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 238000005530 etching Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 제1금속배선의 콘택공정시 플레이트전극의 펀치 ( punch ) 현상의 유발을 방지하여 콘택특성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming metal wirings in a semiconductor device, and more particularly, to a technique of improving contact characteristics by preventing the occurrence of a punch phenomenon in a plate electrode during a contact process of a first metal wiring.
일반적으로 반도체소자를 구동하기 위하여, 이들을 전기적으로 동작시킬 수 있는 회로를 구성하여야 한다.In general, in order to drive semiconductor devices, a circuit capable of electrically operating them should be configured.
상기한 회로는 소자의 주변회로부에서 반도체소자의 각각 구성물을 전기적으로 콘택하는 금속배선을 예정된 형태로 형성한 것이다.The circuit described above is formed in a predetermined shape with a metal wiring for electrically contacting each component of the semiconductor device in the peripheral circuit portion of the device.
가장 하부에 형성되는 금속배선을 제1금속배선이라 하며 그 상부에 다수의 금속배선이 형성될 수 있다.The metal wiring formed at the bottom is called a first metal wiring, and a plurality of metal wirings may be formed thereon.
현재, 제1금속배선 콘택 공정시 스톱되는 층은 반도체기판, 워드라인, 비트라인 및 플레이트전극이다.Currently, the layers stopped during the first metal wiring contact process are semiconductor substrates, word lines, bit lines, and plate electrodes.
상기 플레이트전극은 타층보다 상부에 형성되어 상기 제1금속배선의 콘택 공정시 먼저 오픈 ( open ) 되고 비트라인, 워드라인 및 반도체기판의 순서로 오픈되기 때문에 플레이트 쪽의 표면은 과도하게 식각된다.Since the plate electrode is formed above the other layer and is first opened during the contact process of the first metal wiring, the plate electrode is opened in the order of the bit line, the word line, and the semiconductor substrate, so that the surface of the plate side is excessively etched.
특히, 워드라인이나 비트라인 상부에는 버퍼질화막을 적용하므로 폴리실리콘으로 형성되는 상기 플레이트 전극의 식각 정도는 상대적으로 심할 수 밖에 없다.In particular, since the buffer nitride film is applied to the word line or the bit line, the etching degree of the plate electrode formed of polysilicon is relatively severe.
따라서, 상기 제1금속배선을 형성하기 위한 콘택공정시 상기 플레이트전극의 펀치가 발생되어 플레이트전극 쪽에서 콘택 저항이 높아지므로 소자 특성을 열화시키게 된다.Therefore, during the contact process for forming the first metal wiring, the punch of the plate electrode is generated to increase the contact resistance at the plate electrode side, thereby deteriorating device characteristics.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도로서, 플레이트전극과 반도체기판의 금속배선 콘택만을 예로 들어 도시한 것이다.1A to 1C are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art, and show only metal wiring contacts of a plate electrode and a semiconductor substrate as an example.
도 1a를 참조하면, 반도체기판(11) 상부에 하부절연층(13)을 형성한다.Referring to FIG. 1A, a lower insulating layer 13 is formed on the semiconductor substrate 11.
그리고, 상기 하부절연층(13)을 통하여 상기 반도체기판(11)에 접속되는 캐패시터(도시안됨)를 형성한다.Then, a capacitor (not shown) connected to the semiconductor substrate 11 is formed through the lower insulating layer 13.
이때, 상기 캐패시터는 저장전극(도시안됨), 유전체막(도시안됨) 및 플레이트전극(15)으로 형성된 것이다.In this case, the capacitor is formed of a storage electrode (not shown), a dielectric film (not shown), and a plate electrode 15.
여기서, 상기 저장전극은 반도체소자의 고집적화에 충분한 정전용량을 확보할 수 있도록 삼차원적인 구조로 형성한 것이다.Here, the storage electrode is formed in a three-dimensional structure so as to secure a capacitance sufficient for high integration of the semiconductor device.
그 다음, 전체표면상부를 평탄화시키는 층간절연막(17)을 형성한다.Then, an interlayer insulating film 17 is formed to planarize the entire upper surface portion.
그리고, 상기 층간절연막(17) 상부에 감광막패턴(19)을 형성한다.A photosensitive film pattern 19 is formed on the interlayer insulating film 17.
이때, 상기 감광막패턴(19)은 상기 층간절연막(17) 상부에 감광막을 도포하고 제1금속배선 콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한 것이다.In this case, the photoresist layer pattern 19 is formed by applying a photoresist layer on the interlayer insulating layer 17 and exposing and developing using a first metal wiring contact mask (not shown).
도 1b를 참조하면, 상기 감광막패턴(19)을 마스크로 하여 상기 층간절연막(17) 및 하부절연층(13)을 식각하여 상기 플레이트전극(15) 및 반도체기판(11)에 접속되는 제1콘택홀(21)과 제2콘택홀(23)을 형성한다.Referring to FIG. 1B, a first contact connected to the plate electrode 15 and the semiconductor substrate 11 by etching the interlayer insulating layer 17 and the lower insulating layer 13 using the photosensitive film pattern 19 as a mask. The hole 21 and the second contact hole 23 are formed.
이때, 상기 제1콘택홀(21)은 상기 플레이트전극(15)가 펀치되어 상기 하부절연층(13)의 일부까지 식각된 형태로 형성된 것이다.In this case, the first contact hole 21 is formed by punching the plate electrode 15 to a part of the lower insulating layer 13.
도 1c를 참조하면, 상기 제1,2콘택홀(21,23) 표면을 포함한 전체표면상부에 장벽금속층(25)을 형성하고 상기 콘택홀(21,23)을 매립하는 제1금속배선(27)을 형성한다.Referring to FIG. 1C, the first metal wiring 27 may be formed on the entire surface including the first and second contact holes 21 and 23 and the buried metal layer 25 may be buried in the contact holes 21 and 23. ).
이때, 상기 장벽금속층(25)은 Ti/TiN 으로 형성한 것이다.At this time, the barrier metal layer 25 is formed of Ti / TiN.
상기한 바와 같이 종래기술에 따른 반도체소자의 금속배선 형성방법은, 플레이트 전극이 펀치되는 현상이 유발되고, 금속층으로 콘택홀을 형성하는 경우 반드시 사용되는 Ti/TiN 과 같은 장벽금속층의 단차피복성이 나빠 상기 콘택홀의 측벽에만 형성되고, 그로 인하여 콘택 저항이 증가되고 콘택홀의 경사가 약간만 변하여도 증착되는 장벽금속층의 두께가 급격하게 증가하여 일정한 콘택 저항을 유지하기가 어려우므로 반도체소자의 특성 및 신뢰성이 저하되는 문제점이 있다.As described above, in the method of forming a metal wiring of a semiconductor device according to the prior art, a phenomenon in which a plate electrode is punched is caused, and when the contact hole is formed of a metal layer, the step coverage of a barrier metal layer such as Ti / TiN is necessarily used. It is badly formed only on the sidewalls of the contact hole, thereby increasing the contact resistance and even slightly changing the inclination of the contact hole, so that the thickness of the deposited barrier metal layer increases rapidly, so that it is difficult to maintain a constant contact resistance. There is a problem of deterioration.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 플레이트전극이 펀치되더라도 콘택 저항을 감소시킬 수 있도록 하여 소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention is to provide a method for forming a metal wiring of a semiconductor device that can improve the characteristics and reliability of the device by reducing the contact resistance even if the plate electrode is punched to solve the above problems of the prior art. have.
도 1a 내지 도 1c 는 종래기술에 반도체소자의 금속배선 형성방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a metal wiring forming method of a semiconductor device in the prior art.
도 2a 내지 도 2d 는 종래기술에 반도체소자의 금속배선 형성방법을 도시한 단면도.2A to 2D are cross-sectional views showing a metal wiring formation method of a semiconductor device in the prior art.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
11,31 : 반도체기판13,33 : 하부절연층11,31: semiconductor substrate 13,33: lower insulating layer
15,35 : 플레이트전극17,37 : 층간절연막15,35 plate electrode 17,37 interlayer insulating film
19,39 : 감광막패턴21,41 : 제1콘택홀19,39 photoresist pattern 21,41 first contact hole
23,43 : 제2콘택홀25,45 : 장벽금속층23,43: second contact hole 25,45: barrier metal layer
27,47 : 제1금속배선27,47: first metal wiring
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은,In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,
하부절연층이 형성된 반도체기판 상부에 플레이트전극이 구비되는 캐패시터를 형성하는 공정과,Forming a capacitor including a plate electrode on the semiconductor substrate on which the lower insulating layer is formed;
전체표면상부에 층간절연막을 형성하되, 상기 하부절연층보다 식각선택비가 낮게 형성하는 공정과,Forming an interlayer insulating film over the entire surface, and forming an etch selectivity lower than that of the lower insulating layer;
금속배선 콘택마스크를 이용한 사진식각공정으로 제1금속배선 콘택홀을 형성하되, 플라즈마 식각공정으로 실시하는 공정과,Forming a first metal wiring contact hole by a photolithography process using a metal wiring contact mask, and performing the plasma etching process;
상기 콘택홀을 이루는 층간절연막을 습식 식각하여 상기 콘택홀의 CD를 증가시키는 공정과,Wet etching the interlayer insulating film forming the contact hole to increase the CD of the contact hole;
상기 콘택홀 표면에 장벽금속층을 형성하고 후속 공정으로 상기 콘택홀을 매립하는 제1금속배선을 형성하는 공정을 포함하는 것과,Forming a barrier metal layer on the surface of the contact hole and forming a first metal wiring to fill the contact hole in a subsequent process;
상기 하부절연층은 BPSG ( boro phospho silicate glass ), PSG ( phosphorous silicate glass ) 또는 O3-TEOS ( ozone-tetra ethyl ortho silicate ) 절연막으로 형성하는 것과,The lower insulating layer is formed of a boro phospho silicate glass (BPSG), phosphorous silicate glass (PSG) or ozone-tetra ethyl ortho silicate (O 3 -TEOS) insulating film,
상기 층간절연막은 BPSG, PSG 또는 O3-TEOS 절연막으로 형성하는 것과,The interlayer insulating film is formed of a BPSG, PSG or O3-TEOS insulating film,
상기 층간절연막은 상온 ∼ 450 ℃ 온도에서 형성된 PECVD 절연막으로 형성하는 것과,The interlayer insulating film is formed of a PECVD insulating film formed at room temperature to 450 ℃ temperature,
상기 플라즈마 식각공정은 RIE ( reactive ion etching ) , ICP, TCP, Helicon, Helical, ECR 또는 파라렐 플레이트 타입 ( parallel plate type ) 의 플라즈마를 이용하여 실시하는 것과,The plasma etching process may be performed using plasma of reactive ion etching (RIE), ICP, TCP, Helicon, Helical, ECR or parallel plate type (parallel plate type),
상기 플라즈마 식각공정은 주식각 가스로 CF 계열이나 CHF 계열의 가스를 단독 또는 혼합하여 사용하는 것과,The plasma etching process is to use a single or mixed gas of CF series or CHF series as a stock angle gas,
상기 플라즈마 식각공정은 보조 첨가 가스로 Ar, N2, CO, O2및 이들의 조합 중에서 선택된 임의의 한가지를 사용하는 것과,The plasma etching process is to use any one selected from Ar, N 2 , CO, O 2 and combinations thereof as an auxiliary addition gas,
상기 플라즈마 식각공정은 보조 첨가 가스를 주식각 가스의 10 ∼ 100 퍼센트 범위로 조절하여 사용하는 것과,The plasma etching process is used to adjust the auxiliary additive gas in the range of 10 to 100 percent of the stock angle gas,
상기 플라즈마 식각공정은 압력을 1 ∼ 1000 mTorr 로 조절하고 전극의 온도를 0 ∼ 300 ℃ 로 조절하여 실시하는 것과,The plasma etching process is performed by adjusting the pressure to 1 to 1000 mTorr and the temperature of the electrode to 0 to 300 ℃,
상기 플라즈마 식각공정은 사용되는 각각의 가스를 1 ∼ 200 sccm 의 유량만큼만 사용하는 것과,The plasma etching process is to use each gas used only in the flow rate of 1 to 200 sccm,
상기 플라즈마 식각공정은 소오스 전력과 바이어스 전력을 각각 10 ∼ 3000 와트로 조절하여 실시하는 것과,The plasma etching process is performed by adjusting the source power and the bias power to 10 to 3000 watts, respectively,
상기 습식 식각공정은 HF 용액이나 BOE ( buffered oxide etchant ) 용액을 이용하여 실시하는 것을 특징으로 한다.The wet etching process may be performed using HF solution or BOE (buffered oxide etchant) solution.
한편, 본 발명의 원리는 다음과 같다.On the other hand, the principle of the present invention is as follows.
금속배선 콘택 공정후 플레이트전극 상부의 층간절연막과 그 하부의 절연막과의 식각선택비 차이를 이용하여 상기 플레이트전극 상부를 층간절연막을 습식 식각함으로써 상기 플레이트전극에 형성되는 콘택홀의 상측 CD를 크게 형성하여 장벽금속층의 증착 두께 조절이 용이하도록 하여 소자의 콘택 저항을 일정하게 확보할 수 있도록 하는 것이다.After the metal wiring contact process, the upper CD of the contact hole formed in the plate electrode is formed by wet etching the interlayer insulating layer on the plate electrode by using the difference in the etching selectivity between the interlayer insulating layer on the plate electrode and the insulating layer under the metal electrode. By controlling the deposition thickness of the barrier metal layer is to ensure a constant contact resistance of the device.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.2A through 2D are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 2a 를 참조하면, 반도체기판(31) 상부에 하부절연층(33)을 형성한다. 이때, 상기 하부절연층(33)은 BPSG ( boro phospho silicate glass ), PSG (phosphorous silicate glass ) 또는 O3-TEOS ( ozone-tetra ethyl ortho silicate ) 절연막으로 형성한다.Referring to FIG. 2A, a lower insulating layer 33 is formed on the semiconductor substrate 31. In this case, the lower insulating layer 33 is formed of boro phospho silicate glass (BPSG), phosphorous silicate glass (PSG) or ozone-tetra ethyl ortho silicate (O 3 -TEOS) insulating film.
그리고, 상기 하부절연층(33)을 통하여 상기 반도체기판(31)에 접속되는 캐패시터(도시안됨)를 형성한다.Then, a capacitor (not shown) connected to the semiconductor substrate 31 is formed through the lower insulating layer 33.
이때, 상기 캐패시터는 저장전극(도시안됨), 유전체막(도시안됨) 및 플레이트전극(35)으로 형성된 것이다.In this case, the capacitor is formed of a storage electrode (not shown), a dielectric film (not shown), and a plate electrode 35.
여기서, 상기 저장전극은 반도체소자의 고집적화에 충분한 정전용량을 확보할 수 있도록 삼차원적인 구조로 형성한 것이다.Here, the storage electrode is formed in a three-dimensional structure so as to secure a capacitance sufficient for high integration of the semiconductor device.
그 다음, 전체표면상부를 평탄화시키는 층간절연막(37)을 형성한다.Then, an interlayer insulating film 37 is formed to planarize the entire upper surface portion.
이때, 상기 층간절연막(37)은 상기 하부절연층(33)보다 습식 식각 속도가 빠른 절연물질로 형성한 것이다.In this case, the interlayer insulating layer 37 is formed of an insulating material having a faster wet etching rate than the lower insulating layer 33.
예를 들면, BPSG ( boro phospho silicate glass ), PSG ( phosphorous silicate glass ) 또는 O3-TEOS ( ozone-tetra ethyl ortho silicate ) 절연막으로 형성하되, 상기 BPSG 절연막의 불순물 량을 조절하여 식각선택비 차이를 갖도록 형성하거나 상기 하부절연층(33)으로 사용되는 층보다 식각이 잘되는 물질로 형성한다.For example, boro phospho silicate glass (PSP), phosphorous silicate glass (PSG), or ozone-tetra ethyl ortho silicate (O 3 -TEOS) insulating film may be formed, and the difference in etching selectivity may be adjusted by controlling the amount of impurities in the BPSG insulating film. It is formed of a material having a better etching than the layer used to form or to the lower insulating layer 33.
또한, 상기 층간절연막(37)은 상온 ∼ 450 ℃ 온도에서 형성된 PECVD 절연막으로 형성할 수도 있다.In addition, the interlayer insulating film 37 may be formed of a PECVD insulating film formed at room temperature to 450 ° C.
도 2b 를 참조하면, 상기 층간절연막(37) 상부에 감광막패턴(39)을 형성한다.Referring to FIG. 2B, a photosensitive film pattern 39 is formed on the interlayer insulating film 37.
이때, 상기 감광막패턴(39)은 상기 층간절연막(37) 상부에 감광막을 도포하고 제1금속배선 콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한 것이다.In this case, the photoresist layer pattern 39 is formed by applying a photoresist layer on the interlayer insulating layer 37 and using an exposure and development process using a first metal wiring contact mask (not shown).
그 다음, 상기 감광막패턴(39)을 마스크로 하는 플라즈마 건식 식각공정으로 상기 플레이트전극(41) 및 반도체기판(43)을 노출시키는 제1,2콘택홀(41,43)을 형성한다. 이때, 상기 제1콘택홀(41)은 상기 플레이트전극(35)을 펀치하여 형성된 것이다.Next, first and second contact holes 41 and 43 exposing the plate electrode 41 and the semiconductor substrate 43 are formed by a plasma dry etching process using the photoresist pattern 39 as a mask. In this case, the first contact hole 41 is formed by punching the plate electrode 35.
여기서, 상기 플라즈마 식각공정은 RIE, ICP, TCP, Helicon, Helical, ECR 또는 파라렐 플레이트 타입의 플라즈마를 이용하여 실시한 것이다.Here, the plasma etching process is performed using a plasma of RIE, ICP, TCP, Helicon, Helical, ECR or Pararell plate type.
상기 플라즈마 식각공정은 다음과 같은 조건으로 실시한다.The plasma etching process is performed under the following conditions.
1. 주식각 가스는 CF 계열이나 CHF 계열의 가스를 단독 또는 혼합으로 사용한다.1. For each stock gas, CF series or CHF series gas may be used alone or in combination.
2. 보조 첨가 가스는 Ar, N2, CO, O2및 이들의 조합 중에서 선택된 임의의 한가지를 사용한다.2. The auxiliary addition gas uses any one selected from Ar, N 2 , CO, O 2, and combinations thereof.
3. 압력은 1 ∼ 1000 mTorr 로 조절한다.3. The pressure is adjusted to 1 to 1000 mTorr.
4. 식각공정시 사용되는 각각의 가스는 1 ∼ 200 sccm 의 유량만큼만 사용한다.4. Each gas used in the etching process is used only at a flow rate of 1 to 200 sccm.
5. 보조 첨가 가스는 주식각 가스의 10 ∼ 100 퍼센트 범위로 조절한다.5. The auxiliary additive gas is adjusted in the range of 10 to 100 percent of the stock gas.
6. 소오스 전력과 바이어스 전력은 각각 10 ∼ 3000 와트로 조절한다.6. Adjust the source and bias power to 10 to 3000 watts respectively.
7. 전극의 온도를 0 ∼ 300 ℃ 로 조절한다.7. Adjust the temperature of the electrode to 0-300 degreeC.
도 2c 를 참조하면, 상기 감광막패턴(39)을 제거하고 상기 층간절연막(37)을 습식 식각하여 제1,2콘택홀(41,43)의 상측 CD를 증가시킨다.Referring to FIG. 2C, the upper CD of the first and second contact holes 41 and 43 is increased by removing the photoresist pattern 39 and wet etching the interlayer insulating layer 37.
이때, 상기 습식 식각공정은 HF 용액이나 BOE 용액을 이용하여 실시한다.In this case, the wet etching process is performed using HF solution or BOE solution.
도 2d 를 참조하면, 상기 제1,2콘택홀(41,43)을 포함한 전체표면상부에 장벽금속층(45)인 Ti/TiN을 증착하고 상기 콘택홀(41,43)을 매립하는 제1금속배선(27)을 형성한다.Referring to FIG. 2D, a first metal depositing Ti / TiN, the barrier metal layer 45, and filling the contact holes 41 and 43 on the entire surface including the first and second contact holes 41 and 43. The wiring 27 is formed.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 제1금속배선 콘택 식각공정으로 형성된 콘택홀의 상측 CD를 습식 식각 방법으로 증가시켜 후속 공정으로 형성되는 장벽금속층의 증착 공정을 용이하게 실시할 수 있도록 함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, the method for forming the metal wiring of the semiconductor device according to the present invention facilitates the deposition process of the barrier metal layer formed by the subsequent process by increasing the upper CD of the contact hole formed by the first metal wiring contact etching process by the wet etching method. The present invention provides an effect of improving the characteristics and reliability of the semiconductor device and thereby enabling high integration of the semiconductor device.
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