KR20040002151A - Method for forming metal line using dual damascene process - Google Patents
Method for forming metal line using dual damascene process Download PDFInfo
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- KR20040002151A KR20040002151A KR1020020037590A KR20020037590A KR20040002151A KR 20040002151 A KR20040002151 A KR 20040002151A KR 1020020037590 A KR1020020037590 A KR 1020020037590A KR 20020037590 A KR20020037590 A KR 20020037590A KR 20040002151 A KR20040002151 A KR 20040002151A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 듀얼 다마신(Dual Damascene)공정을 이용한 금속배선 형성방법에 관한 것으로, 보다 상세하게는, 감광막 패턴 상에 실리레이션(silylation)막을 형성하여 원하는 에치 타켓(ethc taget)의 프로파일(profile)을 구현하는 듀얼 다마신 공정을 이용한 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming metal wirings using a dual damascene process, and more particularly, to form a silicide film on a photoresist pattern to profile a desired ethc taget. It relates to a metal wiring forming method using a dual damascene process to implement.
반도체 메모리 소자의 집적도가 증가함에 따라, 메모리 셀들은 스택(Stack) 구조화되고 있으며, 이에 따라, 각 셀들간의 전기적 연결을 위한 금속배선도 배선 설계를 용이하게 할 수 있는 다층 구조로 형성되고 있다.As the degree of integration of semiconductor memory devices increases, memory cells are stacked in structure, and thus, metal wiring diagrams for electrical connection between the cells are formed in a multi-layer structure that can facilitate wiring design.
이러한 다층금속배선 구조는 배선 설계가 자유롭고, 배선저항 및 전류용량 등의 설정을 여유있게 할 수 있다는 잇점이 있다.Such a multilayer metal wiring structure has advantages in that the wiring design can be freely set and the setting of the wiring resistance and the current capacity can be made free.
한편, 금속배선 물질로서는 전기 전도도가 비교적 우수한 알루미늄(Al) 또는 그의 합금막이 주로 사용되어 왔으며, 최근에는 텅스텐은 물론, 알루미늄에 비해 전기 전도도가 더 우수한 구리(Cu)를 이용하려는 연구가 진행되고 있다.Meanwhile, aluminum (Al) or an alloy film thereof having relatively high electrical conductivity has been mainly used as a metal wiring material, and recently, studies have been conducted to use tungsten as well as copper (Cu) having better electrical conductivity than aluminum. .
그러나, 종래 기술에 의해 금속배선을 형성할 경우에는 금속막의 식각 특성과 관련하여 금속막의 건식 식각 후에 인접하는 금속배선들간에 브릿지(bridge)가 발생할 수 있고, 금속막이 화합물 형태로 잔류됨으로써 소자의 전기적 특성에 악영향을 미치는 문제점이 있다. 특히, 이러한 문제는 반도체 소자의 고집적화가 진행됨에 따라, 더욱 심각할 것으로 예상된다.However, in the case of forming metal wirings according to the prior art, a bridge may occur between adjacent metal wirings after dry etching of the metal film in relation to the etching characteristics of the metal film, and the metal film remains in the form of a compound, thereby causing electrical There is a problem that adversely affects the characteristics. In particular, this problem is expected to be more serious as the integration of semiconductor devices proceeds.
또한, 최종에는 상기와 같은 문제점들을 해결하기 위하여 듀얼 다마신 공정을 이용한 금속배선 형성방법이 제안되었다.In addition, finally, in order to solve the above problems, a method of forming a metal wiring using a dual damascene process has been proposed.
도 1a 내지 도 1e는 종래 기술에 따른 듀얼 다마신 공정을 이용한 금속배선 형성방법을 설명하기 위한 단면도이다.1A to 1E are cross-sectional views illustrating a method for forming metal wirings using a dual damascene process according to the prior art.
도 1a를 참조하면, 소정의 하지층이 구비된 반도체 기판(1) 상에 층간절연막(3)을 형성한후, 감광막을 도포하고, 콘택 형성 영역을 한정하도록 상기 감광막 부분을 선택적으로 노광 및 현상하여 제1감광막 패턴(5)을 형성한다.Referring to FIG. 1A, after forming an interlayer insulating film 3 on a semiconductor substrate 1 provided with a predetermined underlayer, a photosensitive film is coated, and the photosensitive film portion is selectively exposed and developed to define a contact forming region. The first photosensitive film pattern 5 is formed.
상기 제1감광막 패턴(5) 상에 감광막을 도포하고, 금속배선 형성 영역을 한정하도록 감광막 부분을 노광 및 현상하여 제2감광막 패턴(7)을 형성한다. 이 결과로서, 전체적으로 T자형의 감광막 패턴(9)을 형성한다.A photoresist film is coated on the first photoresist pattern 5, and a second photoresist pattern 7 is formed by exposing and developing the photoresist part to define a metal wiring formation region. As a result, the T-shaped photosensitive film pattern 9 is formed as a whole.
그런다음, 감광막 패턴(9)과 그 하부에 배치된 층간절연막(3)간의 식각 선택비(etch selectivity)를 조절하기 위해 E-빔(11)을 조사시켜 상기 감광막 패턴(9)을 경화(curing)시킨다.Then, curing the photoresist pattern 9 by irradiating an E-beam 11 to adjust the etch selectivity between the photoresist pattern 9 and the interlayer insulating layer 3 disposed thereunder. )
도 1b를 참조하면, 감광막 패턴(9)을 이용해서 노출된 층간절연막(3) 부분을 1차로 건식식각한다. 이때, 감광막과 층간절연막간의 식각선택비에 의해, 상기 층간절연막(3)의 일부 두께가 식각되며, 동시에, 노출된 제1감광막 패턴(5)의 일부 두께가 함께 식각된다.Referring to FIG. 1B, the exposed portion of the interlayer insulating film 3 is primarily dry-etched using the photosensitive film pattern 9. At this time, the thickness of the interlayer insulating layer 3 is etched by the etching selectivity between the photosensitive layer and the interlayer insulating layer, and at the same time, the part of the exposed first photosensitive layer pattern 5 is etched together.
도 1c를 참조하면, 상기 결과물에 대해 2차로 건식식각을 수행하여 노출된 제1감광막 패턴(5)의 일부를 완전히 제거하고, 동시에, 층간절연막(3)의 일부 두께를 추가로 더 식각한다.Referring to FIG. 1C, a second dry etching is performed on the resultant to completely remove a part of the exposed first photoresist pattern 5, and at the same time, a part of the thickness of the interlayer insulating layer 3 is further etched.
도 1d를 참조하면, 잔류된 감광막 패턴(9)을 이용해서 층간절연막(3)을 3차로 건식식각한다. 이 과정에서, 2회에 걸쳐 식각된 층간절연막(3) 부분이 재차 식각되어 기판을 노출시키는 콘택홀(13)이 형성되고, 동시에, 노출된 층간절연막(3)의 상면 일부 두께가 함께 식각되어 금속배선 형성 영역을 한정하는 트렌치(15)가 형성된다.Referring to FIG. 1D, the interlayer insulating film 3 is dry-etched in the third order using the remaining photosensitive film pattern 9. In this process, the portion of the interlayer insulating film 3 etched twice is etched again to form a contact hole 13 exposing the substrate, and at the same time, the thickness of a portion of the upper surface of the exposed interlayer insulating film 3 is etched together. The trench 15 defining the metal wiring formation region is formed.
도 1e를 참조하면, 잔류된 감광막 패턴을 제거한 상태에서, 상기 콘택홀(13) 및 트렌치(15)가 완전 매립되도록 층간절연막(3)상에 금속막을 층착하고, 이어, 상기 층간절연막(3)이 노출될 때까지 상기 금속막을 CMP 공정으로 연마하여 상기 콘택홀(13) 및 트렌치(15) 내에 기판, 또는, 하지층과 전기적으로 콘택되는 콘택플러그를 포함한 금속배선(17)을 형성한다.Referring to FIG. 1E, a metal film is deposited on the interlayer insulating film 3 so that the contact hole 13 and the trench 15 are completely filled in a state where the remaining photoresist pattern is removed, and then the interlayer insulating film 3 is formed. The metal film is polished by the CMP process until the metal film is exposed, thereby forming a metal wiring 17 including a contact plug electrically contacting the substrate or the underlying layer in the contact hole 13 and the trench 15.
그러나, 종래 기술에 따라 금속배선을 형성할 경우에는, 제1감광막 패턴의 두께가 일정치 않은 문제점과 동시에 제1감광막 패턴이 완전히 제거될때까지 층간절연막을 식각하여 콘택홀을 형성해야 하므로, 상기 제1감광막 패턴의 두께에 의하여 콘택홀의 깊이가 달라진다.However, in the case of forming the metal wiring according to the prior art, since the thickness of the first photoresist pattern is not fixed, the interlayer insulating layer must be etched to form contact holes until the first photoresist pattern is completely removed. 1 The depth of the contact hole varies depending on the thickness of the photoresist pattern.
또한, 감광막 패턴을 이용하여 층간절연막을 식각할때 정확한 식각 정지점을 조절하기 어려워 금속배선의 두께를 정확히 조절할 수 없어, 결국 금속배선 형성공정의 안정성이 부족하고 소자의 신뢰성 및 수율 저하를 초래하는 문제가 발생한다.In addition, when the interlayer insulating layer is etched using the photoresist pattern, it is difficult to precisely control the etch stop point, so that the thickness of the metal wiring cannot be precisely controlled, resulting in a lack of stability of the metal wiring forming process and a decrease in reliability and yield of the device. A problem arises.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 원하는 에치 타겟(etch target)의 프로파일(profile)를 형성 할 수 있는 듀얼 다마신 공정을 이용한 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring using a dual damascene process that can be formed to solve the above problems, to form a profile of a desired etch target. have.
도 1a 내지 도 1e는 종래의 기술에 따른 듀얼 다마신 공정을 이용한 금속배선 형성방법을 도시한 공정별 단면도.1A to 1E are cross-sectional views illustrating a method of forming metal wirings using a dual damascene process according to the related art.
도 2a 내지 도 2g는 본 발명에 따른 듀얼 다마신 공정을 이용한 금속배선 형성방법을 도시한 공정별 단면도.Figure 2a to 2g is a cross-sectional view showing a process for forming a metal wiring using a dual damascene process according to the present invention.
-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing
21 : 반도체 기판 23 : 층간절연막21 semiconductor substrate 23 interlayer insulating film
25 : 제1감광막 패턴 27 : 제1실리레이션막25: first photosensitive film pattern 27: first silicide film
29 : 제2감광막 패턴 31 : 제2실리레이션막29: second photosensitive film pattern 31: second silicide film
33 : 콘택홀 35 : 트렌치33: contact hole 35: trench
37a : 금속막 37 : 금속배선37a: metal film 37: metal wiring
상기와 같은 목적을 달성하기 위한 본 발명의 듀얼 다마신 공정을 이용한 금속배선 형성방법은, 하지층이 구비된 반도체 기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막 상에 콘택영역에 대응하는 제1감광막 패턴을 형성하는 단계;상기 제1감광막 패턴 상에 제1실리레이션막을 형성하는 단계; 상기 제1실리레이션 막 상에 금속배선에 대응하는 제2감광막 패턴을 형성하는 단계; 상기 제2감광막 패턴 상에 제1실리레이션막을 형성하는 단계; 상기 제2실리레이션막 및 상기 제2실리레이션막으로 가려지지 않는 제1실리레이션막을 제거하면서 콘택홀 영역을 한정하도록 상기 층간절연막을 식각하는 단계; 상기 제1실리레이션막에 의해 가려지지 않은 감광막 패턴을 제거하는 단계; 상기 1실리레이션막과 함께 상기 제1실리레이션막에 의해 가려지지 않은 층간절연막을 식각하여, 금속배선이 형성될 트렌치와 동시에 기판을 노출시키는 콘택홀을 형성하는 단계; 상기 감광막 패턴을 제거하는 단계; 상기 콘택홀 및 트렌치가 매립되도록 상기 결과물 상에 금속막을 증착하는 단계; 및 상기 층간절연막이 노출될 때까지 상기 금속막을 연마하는 단계를 포함한다.Metal interconnection forming method using a dual damascene process of the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a semiconductor substrate provided with a base layer; Forming a first photoresist layer pattern corresponding to a contact region on the interlayer insulating layer; forming a first silicide layer on the first photoresist layer pattern; Forming a second photoresist film pattern corresponding to the metal wiring on the first silicide film; Forming a first silicide film on the second photoresist film pattern; Etching the interlayer insulating film to define a contact hole region while removing the second silicide film and the first silicide film not covered by the second silicide film; Removing the photoresist pattern that is not covered by the first silicide film; Etching the interlayer insulating film not covered by the first silicide film together with the first silicide film to form a contact hole for exposing a substrate simultaneously with a trench in which metal wiring is to be formed; Removing the photoresist pattern; Depositing a metal film on the resultant material to fill the contact hole and the trench; And polishing the metal film until the interlayer insulating film is exposed.
본 발명에 따르면, 듀얼 다마신 공정을 이용하여 금속배선의 형성공정에서, 제1감광막 패턴 상에 제1실리레이션막을 형성하고, 제2감광막 패턴 상에도 같은 방법으로 제2실리레이션막을 형성 함으로써, 원하는 에치 타겟(etch target)의 프로파일(profile)을 구현 할 수가 있다.According to the present invention, in the process of forming a metal wiring by using the dual damascene process, by forming a first silicide film on the first photosensitive film pattern, and forming a second silicide film on the second photosensitive film pattern in the same manner, You can implement a profile of the desired etch target.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 자세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도2g는 본 발명의 실시예에 따른 듀얼 다마신 공정을 이용한 금속배선 형성방법을 설명하기 위한 공정별 단면도이다.2A to 2G are cross-sectional views illustrating processes for forming metal wirings using a dual damascene process according to an exemplary embodiment of the present invention.
도 2a를 참조하면, 트랜지스터 및 하부 금속배선 등을 포함한 소정의 하지층 (도시안됨)이 구비된 반도체 기판(21)을 마련하고, 상기 반도체 기판(21) 상에 HDP(High Density Plasma) 방식으로 증착된 산화막으로 이루어지면서 후속하는 CMP(Chemical Mechanical Polishing) 공정을 통해 표면 평탄화가 이루어진 층간절연막(23)을 형성한다.Referring to FIG. 2A, a semiconductor substrate 21 having a predetermined underlayer (not shown) including a transistor, a lower metal wiring, and the like is provided, and a high density plasma (HDP) method is formed on the semiconductor substrate 21. The interlayer insulating film 23 having the surface planarization is formed through a subsequent chemical mechanical polishing (CMP) process, which is made of the deposited oxide film.
그런다음, 상기 층간절연막(23) 상에 감광막을 도포하고, 상기 감광막의 소정 부분을 노광 및 현상하여 후속의 콘택 영역을 한정하는 제1감광막 패턴(25)을 형성한다. 이어, 상기 제1감광막 패턴(25) 상에 제1실리레이션막(27)을 형성한다.Then, a photoresist film is applied on the interlayer insulating film 23, and a predetermined portion of the photoresist film is exposed and developed to form a first photoresist film pattern 25 defining a subsequent contact region. Subsequently, a first silicide film 27 is formed on the first photoresist pattern 25.
도 2b를 참조하면, 상기 제1실리레이션막(27) 상에 후속의 금속배선 영역을 한정하는 제2감광막 패턴(29)을 형성하고, 상기 제2감광막 패턴(29) 상에 제2실리레이션막(31)을 형성한다.Referring to FIG. 2B, a second photoresist pattern 29 defining a subsequent metallization region is formed on the first silicide layer 27, and a second silicide is formed on the second photoresist layer pattern 29. A film 31 is formed.
도 2c를 참조하면, 상기 제2실리레이션막 및 상기 제2실리레이션막으로 가려지지 않는 제1실리레이션막(27)과 함께 콘택홀 영역을 한정하도록 상기 층간절연막 (23)을 C2F6/O2/Ar 개스를 사용하여 건식식각한다.Referring to FIG. 2C, the interlayer insulating layer 23 is formed of C 2 F 6 so as to define a contact hole region together with the second silicing layer and the first silicing layer 27 not covered by the second silicing layer. Dry etch using / O 2 / Ar gas.
도 2d를 참조하면, 상기 제1실리레이션막(27)에 의해 가려지지 않은 제1감광막 패턴을 SO2/O2/He 개스를 사용하여 건식식각으로 제거한다. 이때, 상기 제1실리레이션막(27)에서 확산된 Si이 O2개스와 반응하여, 제1실리레이션막(27)에 가려져 있는 감광막 패턴(25)은 제거되지 않는다.Referring to FIG. 2D, the first photoresist layer pattern not covered by the first silicide layer 27 is removed by dry etching using SO 2 / O 2 / He gas. At this time, Si diffused from the first silicide film 27 reacts with the O 2 gas so that the photoresist pattern 25 covered by the first silicide film 27 is not removed.
도 2e를 참조하면, 상기 제1실리레이션막(27)과 함께 상기 제1실리레이션막(24)에 의해 가려지지 않은 층간절연막(23)을 C2F6/O2/Ar 개스를 사용하여 건식식각하여, 금속배선이 형성될 트렌치(35)와 동시에 기판을 노출시키는 콘택홀(33)을 형성한다.Referring to FIG. 2E, an interlayer insulating film 23 not covered by the first silicide film 24 together with the first silicide film 27 is formed using C 2 F 6 / O 2 / Ar gas. By dry etching, a contact hole 33 exposing the substrate is formed at the same time as the trench 35 in which metal wiring is to be formed.
도 2f를 참조하면, 상기 감광막 패턴을 제거한 상태에서 상기 콘택홀 및 트렌치가 매립되도록 상기 결과물 상에 금속막(37a)을 증착한다. 여기서, 상기 감광막 패턴 제거시, 산화막(Oxide)으로 이루어진 층간절연막(23)은 상기 감광막 패턴에 비하여 50：1 정도의 낮은 선택비를 가지기 때문에 거의 식각되지 않는다.Referring to FIG. 2F, a metal film 37a is deposited on the resultant so that the contact hole and the trench are filled with the photoresist pattern removed. Here, when the photosensitive film pattern is removed, the interlayer insulating film 23 made of oxide is almost etched because it has a selectivity of about 50: 1 lower than that of the photosensitive film pattern.
도 2g를 참조하면, 상기 층간절연막(23)이 노출될 때까지 상기 금속막(37a)에 CMP 공정을 수행하여 금속배선(37)을 형성한다.Referring to FIG. 2G, the metal line 37 is formed by performing a CMP process on the metal layer 37a until the interlayer insulating layer 23 is exposed.
본 발명에 따르면 감광막 더블 코팅(double coating)을 이용한 금속배선 형성공정시 제1감광막 패턴 상에 형성된 제 1실리레이션막과 제2감광막 패턴 상에 형성된 제2실리레이션막은 선택적으로 감광막 패턴 식각 및 층간절연막 식각을 실시 하므로 소망하는 에치 타겟의 프로파일을 형성 할 수 있다.According to the present invention, the first silicide film formed on the first photoresist film pattern and the second silicide film formed on the second photoresist film pattern may be selectively etched and interlayered during the metallization formation process using the photoresist double coating. Since the insulating film is etched, a desired etch target profile can be formed.
이상에서와 같이, 본 발명은 듀얼 다마신 공정을 이용하여 금속배선을 형성하는 공정에 있어서, 제1감광막 패턴 상에 제1실리레이션막을 형성하고 제2감광막 패턴 상에 같은 방법으로 제2실리레이션막을 형성하여 선택적으로 감광막 패턴 식각 및 층간절연막 식각을 실시하므로 원하는 에치 타겟(etch target)의 프로파일 (profile)을 형성할 수 있어 금속배선 형성공정의 안정성을 개선하고 소자의 신뢰성 및 수율을 향상시킬 수 있다.As described above, according to the present invention, in the process of forming the metal wiring by using the dual damascene process, the first silicide film is formed on the first photosensitive film pattern and the second silicide is formed on the second photosensitive film pattern in the same manner. By forming a film and selectively performing photoresist pattern etching and interlayer insulating film etching, it is possible to form a profile of a desired etch target, thereby improving the stability of the metallization process and improving the reliability and yield of the device. have.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시 할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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| KR101105252B1 (en) * | 2009-06-02 | 2012-01-17 | 주식회사 알엠에스기산 | Stopper mount dynamic damper |
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| KR100303779B1 (en) * | 1999-06-28 | 2001-11-01 | 박종섭 | Method for forming pattern using double photoresist silylation |
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