KR20040001949A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of preventing attacks of a bit line due to wet-cleaning. CONSTITUTION: A bit line contact hole(43) is formed to expose a substrate(40) by selectively etching the first insulating layer(42). A conductive layer(45) is filled into the contact hole. A nitride hard mask(46) is formed on the conductive layer by using PECVD(Plasma Enhanced CVD). A fluidity insulating layer(47) is deposited on the nitride hard mask so as to improve topology and to prevent attacks of the conductive layer due to wet-cleaning. A bit line pattern is then formed by selectively etching the fluidity insulating layer, the nitride hard mask and the conductive layer. After forming the second insulating layer on the resultant structure, a plurality of contact plugs as storage nodes are formed. Wet-cleaning is then performed to remove defects.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for preventing attack of a bit line according to a cleaning process performed after a storage node contact plug separation process.

In general, a semiconductor device includes a plurality of semiconductor devices therein. As semiconductor devices become highly integrated, semiconductor devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of semiconductor devices, for example, transistors and capacitors. In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule is reduced, the size of semiconductor devices formed inside the cell is gradually decreasing. In fact, the minimum line width of the recent semiconductor DRAM device is formed to 0.115㎛ or less. Therefore, many difficulties have arisen in the manufacturing process of the semiconductor devices forming the cell.

1 is a plan view schematically illustrating a conductive film pattern including a word line and a bit line.

Referring to FIG. 1, a plurality of gate electrodes, for example, word lines W / L are disposed in one direction, and bit lines B / L are disposed in a direction crossing the word lines W / L. The bit line B / L is contacted through an active region (not shown) and a bit line contact (BLC) of the substrate through a landing plug contact (hereinafter referred to as LPC) process. Storage node contacts (SNCs) are formed to form capacitors.

Hereinafter, a method of forming a bit line B / L, a bit line contact BLC, and a storage node contact SNC in a semiconductor memory device will be described.

First, a gate electrode pattern including a gate electrode is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the entire surface of the semiconductor substrate including the gate electrode pattern, and then a self alignment contact pattern is formed through a self alignment contact (hereinafter, referred to as a SAC) process. Next, polysilicon is formed on the self-aligned contact pattern and planarized to form a bit line contact pad and a storage node contact pad.

On the other hand, the formation of such contact pads may vary depending on each process specification, so the contact pad forming process may be excluded.

Next, an etch stop layer and a second interlayer insulating layer are formed on the entire surface of the semiconductor substrate including the bit line contact pads and the storage node contact pads to form bit line contact holes. A barrier metal is deposited along the entire profile including the bit line contact hole, and then a conductive material for bit line formation is formed on the barrier metal.

In this case, a method of forming a bit line contact by planarizing the barrier metal and the conductive material on the second interlayer insulating film by Chemical Mechanical Polishing (hereinafter referred to as CMP) method may also be used.

A nitride layer hard mask material is deposited on the conductive material, and then a bit line pattern is formed through a photolithography process.

Here, the above-mentioned barrier metal TiN is mainly used, and may be formed as a double layer of Ti / TiN in order to form ohmic contact. In addition, the bit line conductive material may be made of metal such as tungsten (W).

Meanwhile, the above-mentioned hard mask nitride film mainly uses plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD), and thus has a disadvantage of poor step coverage. Therefore, the upper layer of the conductive material film such as tungsten formed in the bit line contact hole may not be completely capped.

Subsequently, a third interlayer dielectric layer is deposited on the bit line, and then, as shown in FIG. 1, a SAC pattern of a line type in a direction perpendicular to the bit line B / L, that is, a storage node contact SNC After forming the contact hole for), and using the polysilicon or the like to form a storage node contact plug. Subsequently, a CMP process is performed for isolation between plugs, and then a wet cleaning process is performed to suppress defects caused by etching residues.

At this time, the chemical used is mainly a mixed chemical of H ₂ SO ₄ / H ₂ O ₂ / NH ₄ OH. As described above, the chemicals are exposed after the CMP process due to the poor capping characteristics of the nitride film for hard mask. The tungsten material forming the bitline is attacked.

FIG. 2 is a planar scanning electron microscope (SEM) photograph showing an attack of a bit line using tungsten as an electrode material, and FIG. 3 is a cross-sectional SEM photograph. Decap shows the bit line (B / L) damaged by the attack.

2 and 3, the attack (X) of the tungsten bit line (B / L) by the penetration of the wet chemical (Y) into the tungsten bit line (B / L) exposed at the bit line contact (BLC) site. ) Can be seen.

The present invention has been proposed to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor device capable of preventing the wet attack of the bit line according to the separation between the plug and wet cleaning after the storage node contact plug is formed. There is this.

1 is a plan view schematically showing a conductive film pattern including a word line and a bit line.

Figure 2 is a planar SEM photograph showing the attack of the bit line using tungsten as an electrode material.

3 is a cross-sectional SEM photograph showing the attack of the bit line using tungsten as an electrode material.

4A to 4C are cross-sectional views illustrating a semiconductor device manufacturing process according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

40 substrate 41 active region

42: first insulating film 43: contact hole

44: barrier film 47: flowable insulating film

45: conductive material film for forming the bit line

46: nitride film for hard mask

In order to achieve the above object, the present invention comprises the steps of selectively etching the first insulating film on the substrate to form a bit line contact hole for exposing a portion of the substrate surface; Filling the contact hole to form a conductive film for the bit line conductive with the exposed surface of the substrate; Forming a nitride film for a hard mask on the conductive film by using plasma chemical vapor deposition; Depositing a flowable insulating film on the nitride film to improve poor tarology on top of the nitride film and to prevent attack of the conductive film by subsequent cleaning; Selectively etching the flowable insulating film, the nitride film, and the conductive film to form a bit line pattern; Forming a second insulating layer on the entire structure where the bit line pattern is formed; Forming a plurality of contact plugs for storage nodes penetrating through the second insulating layer and the first insulating layer to be in contact with other portions of the surface of the substrate and separated from each other; And performing a cleaning process to remove the defects.

The present invention improves the poor top morphology by depositing a nitride film for hard mask having poor step coverage on the bit line, and improves the poor top morphology and caps the upper part of the bit line, thereby forming a subsequent wetted storage node contact plug. It is intended to prevent attack of the bit line by cleaning.

Hereinafter, in order to explain in detail enough to enable those skilled in the art to easily carry out the technical idea of the present invention, refer to FIGS. 4A to 4C attached to the most preferred embodiment of the present invention. It will be described in detail.

4A to 4C are cross-sectional views illustrating a semiconductor device manufacturing process according to an embodiment of the present invention, which will be described in detail with reference to the drawings.

First, as shown in FIG. 4A, a gate electrode pattern (not shown) including a gate electrode is formed on a substrate 40 on which various elements for forming a semiconductor device are formed. The first insulating layer 42 is formed on the entire surface of the semiconductor substrate 40 including the gate electrode pattern, and then a self-aligned contact pattern that exposes the surface of the substrate 40 through a SAC etching process, that is, the contact hole 43 is formed. Form.

In the embodiment of the present invention, the reference numeral '41' indicates an active region on the substrate 40, for example, a source / drain junction, etc., and a process of forming a pad for a storage node contact and a bit line contact may be performed. In this case, reference numeral 41 denotes such a contact pad.

Subsequently, the contact hole 43 is buried to form a bit line conductive film that is in contact with the exposed surface of the substrate 40.

Specifically, the barrier layer 44 is formed along the entire profile including the contact hole 43 for forming the bit line, and then the conductive material layer 45 for forming the bit line is formed on the barrier layer 44.

The hard mask nitride film 46 is deposited on the conductive material film 45 using PECVD. The material TiN for the barrier film 44 described above is mainly used, and a double layer of Ti / TiN may be formed to form an ohmic contact. In addition, the bit line conductive material may be made of metal such as tungsten (W).

On the other hand, the above-mentioned hard mask nitride film 46 mainly uses a PECVD method, and has a disadvantage in that step coverage is poor, so that the upper layer of the conductive material film 45 such as tungsten formed in the bit line contact hole is not completely capped. can not do it.

Accordingly, the present invention provides a flowable insulating film 47 on the nitride film 46 having excellent fluidity and self-planarization properties in order to improve the upper topology of the nitride film 46 and to prevent attack of the conductive material film 45 by subsequent cleaning. To form.

The fluid insulating layer 47 is an oxide-based material, and examples thereof include an Advanced Planarization Layer (APL) film and a spin on glass (SOG) film.

Particularly in the APL film technology, a self-planarized chemical vapor deposition (CVD) film is applied, and the self-planarized CVD film forms a highly flowable reaction intermediate, which can achieve excellent fill planarization during film formation.

The self-planarizing CVD film, that is, the fluid insulating film 47, is a silicon oxide film formed by CVD by SiH ₄ and H ₂ O ₂ by a Low Pressure Chemical Vapor Deposition (LPCVD) method. It has excellent fillability and flatness, and the film formed is of high quality due to the low moisture content in the film.

Looking at the deposition process in more detail, before forming the flow insulating film 47, a plasma treatment is required to improve the adhesion and gap-fill characteristics of the subsequent flow insulating film 47, wherein N Use a plasma containing ₂ O.

Subsequently, the flowable insulating film 47 is formed on the nitride film 46, and formed to have an appropriate thickness by using an LPVCD method using a reaction source containing nitrogen such as N ₂ O. In this case, the flowable insulating film 47 is formed. SiO _x H _y and (x is 0 to 3, y is from 0 to 1) contain components.

Specifically, the reaction source containing nitrogen described above includes SiH ₄ , SiHa (CH ₃ ) b (a, b is 0 to 4), H ₂ O ₂ , O ₂ , H ₂ O and N ₂ O. Using such a reaction source, it is carried out under a low pressure of 100 mTorr to 2 Torr and a temperature of 0 ° C to 10 ° C, and it is preferable to use N ₂ O of 100SCCM to 3000SCCM.

Meanwhile, water remaining in the fluid insulating film 47 due to the formation of the fluid insulating film 47 is removed, and plasma treatment or heat treatment is further performed for densification of the film.

Specifically, the plasma treatment is a gas such as SiH ₄ , SiH _a (CH 3) _b (a, b is 0 to 4), N ₂ , NH ₃ , O ₂ , O ₃ , Ar, He, Ne or N ₂ O The mixture is carried out for 5 seconds to 200 seconds, and the heat treatment is performed for 10 seconds to 200 seconds under a gas atmosphere such as O ₂ , N ₂ , O ₃ , N ₂ O, or H ₂ and a temperature of 600 ° C. to 800 ° C. desirable.

Subsequently, an antireflection film 48 such as a silicon oxynitride film is deposited, and a bit line structure of a stack structure is formed through a photolithography process as shown in FIG. 4B.

Subsequently, the second insulating layer 49 is deposited on the bit line, and as shown in FIG. 1, the SAC pattern, that is, the storage node contact (SNC) in a line shape perpendicular to the bit line B / L. After forming a contact hole for the), the storage node contact plug 50 is formed using polysilicon or the like. Subsequently, the CMP process is performed to separate the plugs, and then, as shown in FIG. 4C, the wet cleaning process is performed to suppress the occurrence of defects due to the etching residue.

On the other hand, Figure 1b is a view showing a peripheral circuit region of a semiconductor memory device, the storage node contact plug 49 of Figure 4b is completely removed in Figure 4c when the plug separation process is completed.

The cleaning process of FIG. 4C is for removing defects such as various particles generated after a process such as CMP. In this case, as the chemical used, a mixed chemical of H ₂ SO ₄ / H ₂ O ₂ / NH ₄ OH is mainly used. In this process, in the conventional case, the tungsten material forming the exposed bit line after the CMP process is attacked by the poor capping property of the nitride film for hard mask. However, in the present invention, the fluid insulating film 47 compensates for the capping, thereby preventing attack of the bit line made of tungsten or the like.

The present invention described above, by depositing and capping a fluid insulating film having excellent gap-fill characteristics and film flatness on the nitride film for bit line hard mask, thereby preventing the attack of the bit line by the cleaning process performed after the storage node contact plug is formed. It can be seen through the examples that it can.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can prevent the attack of the bit line due to wet cleaning, and can expect an excellent effect of improving the yield of the semiconductor device.

Claims (9)

Selectively etching a first insulating layer on a substrate to form a bit line contact hole exposing a portion of the surface of the substrate; Filling the contact hole to form a conductive film for the bit line conductive with the exposed surface of the substrate; Forming a nitride film for a hard mask on the conductive film by using plasma chemical vapor deposition; Depositing a flowable insulating film on the nitride film to improve poor tarology on top of the nitride film and to prevent attack of the conductive film by subsequent cleaning; Selectively etching the flowable insulating film, the nitride film, and the conductive film to form a bit line pattern; Forming a second insulating layer on the entire structure where the bit line pattern is formed; Forming a plurality of contact plugs for storage nodes penetrating through the second insulating layer and the first insulating layer to be in contact with other portions of the surface of the substrate and separated from each other; And Performing cleaning process to remove defects Semiconductor device manufacturing method comprising a. The method of claim 1, A method of manufacturing a semiconductor device, characterized in that the flowable insulating film is formed to a thickness of 100 Å to 1000 Å. The method of claim 1, In the forming of the flowable insulating film, using a reaction source including SiH ₄ , SiHa (CH ₃ ) b (a, b is 0 to 4), H ₂ O ₂ , O ₂ , H ₂ O and N ₂ O A semiconductor device manufacturing method characterized in that. The method of claim 3, wherein Forming the flowable insulating film is a semiconductor device manufacturing method, characterized in that carried out under a low pressure of 100mTorr to 2Torr and a temperature of 0 ℃ to 10 ℃. The method of claim 4, wherein The method of manufacturing a semiconductor device, characterized in that using the N ₂ O 100SCCM to 3000SCCM. The method of claim 1, And a plasma treatment including N ₂ O prior to forming the flowable insulating film. The method of claim 1, And forming a flowable insulating film, and then performing plasma treatment or heat treatment for water removal and film densification. The method of claim 7, wherein The plasma treatment may include at least one of SiH ₄ , SiH _a (CH 3) _b (a, b is 0 to 4), N ₂ , NH ₃ , O ₂ , O ₃ , Ar, He, Ne, or N ₂ O. Method of manufacturing a semiconductor device, characterized in that carried out for 5 seconds to 200 seconds using a gas of. The method of claim 7, wherein The heat treatment may be performed for 10 seconds to 200 seconds under a gas atmosphere of 500 ° C. to 1200 ° C. in any one of O ₂ , N ₂ , O ₃ , N ₂ O or H ₂ . Way.