KR20040001871A - Method for fabricating semiconductor device having metal-gate electrode - Google Patents
Method for fabricating semiconductor device having metal-gate electrode Download PDFInfo
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- KR20040001871A KR20040001871A KR1020020037205A KR20020037205A KR20040001871A KR 20040001871 A KR20040001871 A KR 20040001871A KR 1020020037205 A KR1020020037205 A KR 1020020037205A KR 20020037205 A KR20020037205 A KR 20020037205A KR 20040001871 A KR20040001871 A KR 20040001871A
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 83
- 229920005591 polysilicon Polymers 0.000 claims abstract description 82
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 75
- 239000010937 tungsten Substances 0.000 claims abstract description 75
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 claims abstract description 69
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 49
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 10
- -1 tungsten nitride Chemical class 0.000 claims description 30
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 29
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 20
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 17
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 17
- 239000007789 gas Substances 0.000 claims description 15
- 238000004544 sputter deposition Methods 0.000 claims description 12
- 229910052786 argon Inorganic materials 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 238000011066 ex-situ storage Methods 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 238000010405 reoxidation reaction Methods 0.000 abstract description 22
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 10
- 238000000059 patterning Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 description 13
- 230000008021 deposition Effects 0.000 description 13
- 238000006243 chemical reaction Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- 239000000376 reactant Substances 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910008938 W—Si Inorganic materials 0.000 description 6
- 125000004429 atom Chemical group 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 4
- 229910018516 Al—O Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910052735 hafnium Inorganic materials 0.000 description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910008807 WSiN Inorganic materials 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 금속게이트전극을 구비한 반도체소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a metal gate electrode.
최근에 반도체소자가 고집적화됨에 따라 소스 및 드레인영역으로 이용되는 불순물영역과 게이트전극의 폭이 감소되고 있다. 이에 따라, 반도체소자는 불순물영역의 접촉 저항 및 게이트전극의 시트저항(Sheet resistance; Rs)이 증가하여 동작 속도가 저하되는 문제점이 발생되었다.Recently, as semiconductor devices have been highly integrated, the widths of impurity regions and gate electrodes used as source and drain regions have decreased. Accordingly, the semiconductor device has a problem in that an operating speed decreases due to an increase in contact resistance of an impurity region and sheet resistance (Rs) of a gate electrode.
그러므로, 반도체소자 내의 소자들의 배선을 알루미늄 합금 및 텅스텐 등의 저저항 물질로 형성하거나, 또는, 게이트전극과 같이 다결정실리콘으로 형성하는 경우에 실리사이드층(silicide)을 형성하여 저항을 감소시킨다.Therefore, in the case where the wirings of the elements in the semiconductor element are formed of low-resistance materials such as aluminum alloy and tungsten, or formed of polycrystalline silicon such as the gate electrode, a silicide layer is formed to reduce the resistance.
한편, 게이트전극으로 폴리실리콘막을 적용하는 반도체소자 제조에서는 폴리실리콘막 식각시에 드러나는 게이트산화막이 손상되므로, 게이트전극의 저항은 그대로 유지하면서 손상된 게이트산화막을 회복하기 위해 폴리실리콘막의 측면을 선택적으로 산화시키는 재산화(Re-oxidation) 공정이 수반된다.On the other hand, in the semiconductor device fabrication using the polysilicon film as the gate electrode, since the gate oxide film exposed during the polysilicon film etching is damaged, the side surface of the polysilicon film is selectively oxidized to recover the damaged gate oxide film while maintaining the resistance of the gate electrode. Re-oxidation is involved.
여기서, 게이트산화막의 재산화 공정은 게이트전극 식각시 게이트산화막에 발생된 마이크로트렌치(microtrench) 및 손실을 회복시켜 주며, 게이트산화막상에 잔류하는 폴리실리콘막 잔막을 산화시키며, 게이트전극의 에지에 있는 게이트산화막의 두께를 증가시켜 신뢰성을 향상시키기 위한 목적으로 진행되고 있다.Here, the reoxidation process of the gate oxide film recovers microtrench and loss generated in the gate oxide film during etching of the gate electrode, oxidizes the remaining polysilicon film remaining on the gate oxide film, and at the edge of the gate electrode. In order to improve the reliability by increasing the thickness of the gate oxide film, progress is being made.
특히, 게이트전극의 에지쪽에 있는 게이트산화막은 그 두께 및 막의 품질에 의해 핫캐리어 특성, 서브 문턱전압(sub-threshold voltage) 특성[누설전류, 게이트유도드레인누설(GIDL)], 펀치쓰루(punchthrough) 특성, 소자 동작 속도에 많은 영향을 미친다.In particular, the gate oxide film on the edge of the gate electrode has hot carrier characteristics, sub-threshold voltage characteristics (leakage current, gate induced drain leakage (GIDL)) and punchthrough depending on the thickness and film quality. Characteristics, device operation speed.
그렇기 때문에 게이트전극 에지쪽의 게이트산화막은 일정한 두께 이상으로 성장시켜야 되며, 이렇게 성장된 산화막을 그레이디드게이트산화막(Graded Gate Oxide; 이하 'GGO막'이라 약칭함) 또는 SBO(Spacer Bottom Oxide)막이라고 부른다.재산화공정은 필수적으로 진행되어야 한다.Therefore, the gate oxide film at the edge of the gate electrode should be grown to a certain thickness or more, and the oxide film thus grown is called a graded gate oxide film (hereinafter, referred to as a 'GGO film') or a spacer bottom oxide (SBO) film. The reprocessing process must proceed essentially.
최근에는 게이트전극의 저항을 낮추기 위해 폴리실리콘막과 금속막의 적층구조를 적용하고 있다.Recently, in order to lower the resistance of the gate electrode, a laminated structure of a polysilicon film and a metal film is applied.
도 1은 종래기술에 따른 반도체소자의 제조 방법을 개략적으로 도시한 도면이다.1 is a view schematically showing a method for manufacturing a semiconductor device according to the prior art.
도 1을 참조하면, 반도체기판(11)상에 게이트산화막(12)을 형성하고, 게이트산화막(12)상에 폴리실리콘막(13), 텅스텐막(14), 하드마스크(15)를 차례로 증착한다. 다음으로, 하드마스크(15)를 먼저 식각한 후, 텅스텐막(14)과 폴리실리콘막(13)을 차례로 식각하여 게이트패턴을 형성한다.Referring to FIG. 1, a gate oxide film 12 is formed on a semiconductor substrate 11, and a polysilicon film 13, a tungsten film 14, and a hard mask 15 are sequentially deposited on the gate oxide film 12. do. Next, after the hard mask 15 is etched first, the tungsten film 14 and the polysilicon film 13 are sequentially etched to form a gate pattern.
상술한 게이트패턴 형성시, 폴리실리콘막(13) 식각으로 드러난 게이트산화막 (12)의 일부분이 손상을 받는다.When forming the gate pattern described above, a part of the gate oxide film 12 exposed by etching the polysilicon film 13 is damaged.
이러한 게이트산화막(12)의 손상을 회복시켜 주기 위해 수소부화(H2rich) 분위기에서 선택적 재산화 공정을 수행한다. 선택적 재산화 과정에서게이트산화막(12)은 최초 증착두께보다 증가된 두께를 갖는 GGO막(12a)으로 개질되고, 아울러 폴리실리콘막(13)의 노출된 측면이 산화됨에 따라 폴리실리콘막(13)의 측면에 산화막(16)이 형성된다.In order to recover the damage of the gate oxide film 12, a selective reoxidation process is performed in a hydrogen rich (H 2 rich) atmosphere. In the selective reoxidation process, the gate oxide film 12 is modified to a GGO film 12a having an increased thickness than the initial deposition thickness, and the polysilicon film 13 as the exposed side of the polysilicon film 13 is oxidized. An oxide film 16 is formed on the side of the.
상술한 바와 같이, 종래기술에서는 폴리실리콘막(13)과 텅스텐막(14)의 적층 게이트전극이 후속의 높은 열공정 또는 산화공정에서 급격한 부피 팽창, 표면저항의 증가 등의 문제가 발생하는 것을 방지하고, 특히 게이트 재산화공정의 산화분위기에서 텅스텐막이 산화되는 것이 방지하기 위해 선택적 재산화(Selective reoxidation) 공정을 적용하고 있다.As described above, in the prior art, the stacked gate electrode of the polysilicon film 13 and the tungsten film 14 prevents problems such as rapid volume expansion and increase in surface resistance during subsequent high thermal or oxidation processes. In particular, a selective reoxidation process is applied to prevent the tungsten film from being oxidized in the oxidation atmosphere of the gate reoxidation process.
즉, 도 1에 도시된 바와 같이, 수소(H2)가 다량 함유된(H2rich) 산화분위기에서 텅스텐막(14)은 산화를 시키지 않고 폴리실리콘막(13)만을 산화시켜 폴리실리콘막(13)의 측면에 산화막(16)을 형성시키는 공정이다.That is, the hydrogen (H 2) a (H 2 rich) tungsten film 14 in an oxidizing atmosphere containing a large amount as shown in Figure 1 was without the oxide only the polysilicon film 13, a polysilicon film ( It is a process of forming the oxide film 16 in the side surface of 13).
그러나, 선택적 재산화 공정시 금속막인 텅스텐막은 산화되지 않지만, 폴리실리콘막과 텅스텐막의 계면에서 얇은 SiO2막(17)이 형성되고, 이렇게 형성된 산화막(17)은 반도체소자의 동작특성을 크게 저하시키는 문제가 있다. 특히, 선택적 재산화 공정은 O2또는 H2O 성분이 포함된 고온의 산화 공정이므로 폴리실리콘막과 텅스텐막의 계면에 SiO2와 같은 반응물을 더 많이 형성시킬 가능성이 높다.However, during the selective reoxidation process, the tungsten film, which is a metal film, is not oxidized, but a thin SiO 2 film 17 is formed at the interface between the polysilicon film and the tungsten film, and the oxide film 17 thus formed greatly degrades the operation characteristics of the semiconductor device. There is a problem. In particular, since the selective reoxidation process is a high temperature oxidation process containing an O 2 or H 2 O component, there is a high possibility of forming more reactants such as SiO 2 at the interface between the polysilicon film and the tungsten film.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 게이트 재산화공정시 게이트전극을 이루는 금속막의 산화를 방지하면서, 게이트전극을 이루는 금속막과 폴리실리콘막의 계면에 산화막 또는 반응층이 형성되는 것을 방지하는데 적합한 반도체소자의 제조 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, an oxide film or a reaction layer is formed at the interface between the metal film and the polysilicon film forming the gate electrode while preventing the oxidation of the metal film forming the gate electrode during the gate reoxidation process It is an object of the present invention to provide a method for manufacturing a semiconductor device which is suitable for preventing it from becoming.
도 1은 종래기술에 따른 반도체소자의 제조 방법을 개략적으로 도시한 도면,1 is a view schematically showing a method for manufacturing a semiconductor device according to the prior art;
도 2a 내지 도 2c는 본 발명의 제1 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도,2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention;
도 3a 내지 도 3c는 본 발명의 제2 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도,3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention;
도 4a 내지 도 4c는 본 발명의 제3 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도.4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 게이트산화막31 semiconductor substrate 32 gate oxide film
32a : GGO막 33a : 폴리실리콘막32a: GGO film 33a: polysilicon film
34a : 텅스텐실리콘나이트라이드막 35a : 텅스텐나이트라이드막34a: tungsten nitride film 35a: tungsten nitride film
36a : 텅스텐막 38 : 산화막36a: tungsten film 38: oxide film
상기 목적을 달성하기 위한 본 발명의 반도체소자의 제조 방법은 반도체기판상에 게이트산화막을 형성하는 단계, 상기 게이트산화막상에 폴리실리콘막을 형성하는 단계, 상기 폴리실리콘막상에 텅스텐실리콘나이트라이드막을 형성하는 단계, 상기 텅스텐실리콘나이트라이드막상에 텅스텐막을 형성하는 단계, 상기 텅스텐막, 상기 텅스텐실리콘나이트라이드막과 상기 폴리실리콘막을 순차적으로 패터닝하여 게이트전극을 형성하는 단계, 및 상기 게이트전극 형성후 드러난 상기 게이트산화막을 선택적으로 재산화시키는 단계를 포함함을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a gate oxide film on a semiconductor substrate, forming a polysilicon film on the gate oxide film, forming a tungsten silicon nitride film on the polysilicon film Forming a tungsten film on the tungsten silicon nitride film; patterning the tungsten film, the tungsten silicon nitride film, and the polysilicon film sequentially to form a gate electrode; and forming the gate electrode after forming the gate electrode. Selectively reoxidizing the oxide film.
또한, 본 발명의 반도체소자의 제조 방법은 반도체기판상에 게이트산화막을 형성하는 단계, 상기 게이트산화막상에 폴리실리콘막을 형성하는 단계, 상기 폴리실리콘막상에 텅스텐실리사이드막을 형성하는 단계, 상기 텅스텐실리사이드막상에 텅스텐나이트라이드막과 텅스텐막을 차례로 형성하는 단계, 상기 텅스텐막, 텅스텐나이트라이드막, 텅스텐실리사이드막과 상기 폴리실리콘막을 순차적으로 패터닝하여 게이트전극을 형성하는 단계, 및 상기 게이트전극 형성후 드러난 상기 게이트산화막을 선택적으로 재산화시키는 산화과정을 수행하여 상기 텅스텐실리사이드막을 텅스텐실리콘나이트라이드막으로 개질시키는 단계를 포함함을 특징으로 한다.In addition, the method of manufacturing a semiconductor device of the present invention comprises the steps of forming a gate oxide film on a semiconductor substrate, forming a polysilicon film on the gate oxide film, forming a tungsten silicide film on the polysilicon film, on the tungsten silicide film Forming a tungsten nitride film and a tungsten film in order, patterning the tungsten film, tungsten nitride film, tungsten silicide film and the polysilicon film sequentially to form a gate electrode, and forming the gate electrode after forming the gate electrode And performing a oxidation process to selectively reoxidize an oxide film to modify the tungsten silicide film into a tungsten silicon nitride film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.
도 2a 내지 도 2c는 본 발명의 제1 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(21)상에 게이트산화막(22)을 형성하고, 게이트산화막(22)상에 폴리실리콘막(23)을 형성한다. 여기서, 게이트산화막(22)으로는 SiO2, SiOxNy, x=0.03∼3, y=0.03∼3) 등의 실리콘산화막, HfO2, ZrO2, Hf-Al-O, Hf-실리케이트, Zr-실리케이트 등의 하프늄(Hf) 또는 지르코늄(Zr)을 포함하는 고유전 금속산화물을 이용한다.As shown in FIG. 2A, the gate oxide film 22 is formed on the semiconductor substrate 21, and the polysilicon film 23 is formed on the gate oxide film 22. Here, as the gate oxide film 22, silicon oxide films such as SiO 2 , SiO x N y , x = 0.03 to 3, y = 0.03 to 3), HfO 2 , ZrO 2 , Hf-Al-O, Hf-silicate, A high dielectric metal oxide containing hafnium (Hf) or zirconium (Zr) such as Zr-silicate is used.
다음으로, 폴리실리콘막(23) 형성시 생성된 자연산화막을 제거하기 위해 HF를 포함한 용액을 이용한 세정을 실시하고, 세정된 폴리실리콘막(23)상에 30Å∼200Å 두께의 텅스텐실리콘나이트라이드막(WSixNy)(24)을 형성한 후 연속해서 300Å∼1000Å 두께의 텅스텐막(25)을 증착한다.Next, in order to remove the natural oxide film generated when the polysilicon film 23 is formed, washing is performed using a solution containing HF, and a tungsten silicon nitride film having a thickness of 30 kPa to 200 kPa is washed on the cleaned polysilicon film 23. After forming (WSi x N y ) 24, a tungsten film 25 of 300 mW to 1000 mW is continuously deposited.
이때, 텅스텐실리콘나이트라이드막(24)은 텅스텐막(25)과 폴리실리콘막(23)간의 반응 배리어막으로서, 텅스텐-실리콘 타겟(W-Si target) 또는 텅스텐-실리콘 소스(W-Si source)를 이용하여 스퍼터링법(sputtering), 화학기상증착법(CVD), 원자층증착법(ALD)을 통해 형성한다.At this time, the tungsten silicon nitride film 24 is a reaction barrier film between the tungsten film 25 and the polysilicon film 23, and is a tungsten-silicon target (W-Si target) or a tungsten-silicon source (W-Si source). It is formed by sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD).
예컨대, 스퍼터링법을 이용하는 경우, 먼저 고전압이 걸린 진공상태에서 증착챔버내의 텅스텐-실리콘 타겟과 반도체기판(21) 사이에 아르곤(Ar) 가스와 질소(N2) 가스의 혼합 가스를 공급한 다음, 아르곤 가스를 이온화시켜 아르곤 플라즈마를 형성하고, 플라즈마를 구성하는 Ar+이온들을 텅스텐-실리콘 타겟으로 전기장에 의해 가속시켜 텅스텐-실리콘 타겟의 표면과 충돌시킨다. 이러한 충돌에 의한 운동량의 교환에 의하여 텅스텐-실리콘 타겟의 표면 원자나 분자가 튀어나오고, 튀어나온 원자나 분자들(Si+, W+)은 반응가스인 질소(N2) 가스와 화학반응하여 반도체기판(21), 즉 폴리실리콘막(23)상에 텅스텐실리콘나이트라이드막(WSiN)을 증착시킨다.For example, in the case of using the sputtering method, first, a mixed gas of argon (Ar) gas and nitrogen (N 2 ) gas is supplied between the tungsten-silicon target and the semiconductor substrate 21 in the deposition chamber under a high voltage applied vacuum. The argon gas is ionized to form an argon plasma, and the Ar + ions constituting the plasma are accelerated by an electric field with a tungsten-silicon target to collide with the surface of the tungsten-silicon target. The surface atoms or molecules of the tungsten-silicon target are protruded by the exchange of momentum due to such collision, and the protruding atoms or molecules (Si + , W + ) are chemically reacted with nitrogen (N 2 ) gas, which is a reactant gas, A tungsten silicon nitride film WSiN is deposited on the substrate 21, that is, on the polysilicon film 23.
전술한 스퍼터링법 이용시, 질소 가스의 플로우량을 5%∼40%로 유지하고, 파워는 50W∼10000W를 유지하며, 기판온도는 200℃∼400℃를 유지한다. 여기서, 질소 가스의 플로우량, 즉 텅스텐실리콘나이트라이드막(24)내 질소 함량을 40% 이하로 유지하는 이유는 텅스텐실리콘나이트라이드막(24)내 질소의 함량이 낮을수록 비저항이 낮기 때문이다.When using the above-mentioned sputtering method, the flow amount of nitrogen gas is maintained at 5% to 40%, the power is maintained at 50W to 10000W, and the substrate temperature is maintained at 200 ° C to 400 ° C. The reason why the flow rate of nitrogen gas, that is, the nitrogen content in the tungsten silicon nitride film 24 is maintained at 40% or less is because the lower the nitrogen content in the tungsten silicon nitride film 24, the lower the specific resistance.
한편, 텅스텐실리콘나이트라이드막(24)과 텅스텐막(25)의 증착은 인시튜(in-situ) 또는 엑시튜(ex-situ) 상태로 이루어진다.Meanwhile, deposition of the tungsten silicon nitride film 24 and the tungsten film 25 is performed in-situ or ex-situ.
도 2b에 도시된 바와 같이, 텅스텐막(25)상에 게이트패터닝을 위한 감광막패턴(26)을 형성한 후, 감광막패턴(26)을 식각마스크로 텅스텐막(25), 텅스텐실리콘나이트라이드막(24), 폴리실리콘막(23)을 차례로 식각하여 폴리실리콘막(23a), 텅스텐실리콘나이트라이드막(24a), 텅스텐막(25a)의 순서로 적층된 게이트전극을 형성한다.As shown in FIG. 2B, after the photosensitive film pattern 26 for gate patterning is formed on the tungsten film 25, the photosensitive film pattern 26 is used as an etch mask, and the tungsten film 25 and the tungsten silicon nitride film ( 24), the polysilicon film 23 is sequentially etched to form a gate electrode stacked in the order of the polysilicon film 23a, the tungsten silicon nitride film 24a, and the tungsten film 25a.
상술한 게이트전극 형성시, 폴리실리콘막(23a) 식각으로 드러난 게이트산화막(22)의 일부분이 손상을 받는다.When forming the above-described gate electrode, a part of the gate oxide film 22 exposed by etching the polysilicon film 23a is damaged.
도 2c에 도시된 바와 같이, 감광막패턴(26)을 제거한 후, 게이트산화막(22)의 손상을 회복시켜 주기 위해 850℃∼950℃의 온도와 수소가 많은(H2-rich) H2O 또는 O2분위기에서 선택적 재산화 공정을 수행한다. 선택적 재산화 과정에서 폴리실리콘막(23a)의 에지 및 반도체기판(21)상에 위치하는 게이트산화막(22)은 초기 증착두께보다 증가된 두께를 갖는 GGO막(22a)으로 개질되고, 아울러 폴리실리콘막(23a)의 노출된 측면이 산화됨에 따라 폴리실리콘막(23a)의 측면에 산화막(27)이 형성된다.As shown in FIG. 2C, after the photoresist pattern 26 is removed, the H 2 O or H 2 -rich or H 2 -rich temperature or 850 ° C. to 950 ° C. is used to recover the damage of the gate oxide layer 22. The selective reoxidation process is carried out in an O 2 atmosphere. In the selective reoxidation process, the gate oxide film 22 positioned on the edge of the polysilicon film 23a and the semiconductor substrate 21 is modified into a GGO film 22a having an increased thickness than the initial deposition thickness. As the exposed side of the film 23a is oxidized, an oxide film 27 is formed on the side of the polysilicon film 23a.
여기서, GGO막(22a)은 초기 증착두께보다 증가된 두께로 형성되면서 폴리실리콘막(23a)의 에지를 소정 부분 침투한 형태를 갖고, 또한 폴리실리콘막(23a) 하부에 위치하는 초기 게이트산화막(22)보다 그 두께가 더 두껍다.Here, the GGO film 22a is formed to have a thickness that is greater than the initial deposition thickness and has a form that partially penetrates the edge of the polysilicon film 23a, and is also located at the lower portion of the polysilicon film 23a. 22) thicker than that.
상술한 선택적 재산화 공정시, 텅스텐막(25a)과 폴리실리콘막(23a) 사이에 형성된 텅스텐실리콘나이트라이드막(24a)은 텅스텐막(25a)과 폴리실리콘막(23a)간의 반응을 억제하는 반응배리어막 역할을 수행하며, 또한 그 형태를 유지하면서 텅스텐막(25a)과 폴리실리콘막(23a)의 계면에 실리콘나이트라이드막, 실리콘옥시나이트라이드막, 실리콘산화막과 같은 반응물이 형성되는 것을 억제한다.In the selective reoxidation process described above, the tungsten silicon nitride film 24a formed between the tungsten film 25a and the polysilicon film 23a suppresses the reaction between the tungsten film 25a and the polysilicon film 23a. It serves as a barrier film and maintains its shape and suppresses the formation of reactants such as silicon nitride film, silicon oxynitride film and silicon oxide film at the interface between tungsten film 25a and polysilicon film 23a. .
후속 공정으로, 도면에 도시되지 않았지만, LDD 영역을 형성하기 위한 저농도 불순물 이온주입을 실시하고, 게이트전극 패턴의 양측벽에 접하는 스페이서를 형성한 후 소스/드레인영역을 형성하기 위한 고농도 불순물 이온주입을 실시한다.In a subsequent process, although not shown in the drawing, a low concentration impurity ion implantation for forming an LDD region is performed, and a high concentration impurity ion implantation for forming a source / drain region is formed after forming a spacer in contact with both side walls of the gate electrode pattern. Conduct.
그리고, 각각의 트랜지스터들을 절연시켜주기 위한 층간절연막을 형성하고, 소스, 드레인 및 게이트전극을 외부단자와 연결시켜주기 위한 금속화 공정을 실시한다.Then, an interlayer insulating film is formed to insulate each transistor, and a metallization process is performed to connect the source, drain, and gate electrodes with external terminals.
도 3a 내지 도 3c는 본 발명의 제2 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도이다.3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
도 3a에 도시된 바와 같이, 반도체기판(31)상에 게이트산화막(32)을 형성하고, 게이트산화막(32)상에 폴리실리콘막(33)을 형성한다. 여기서, 게이트산화막(32)으로는 SiO2, SiOxNy, x=0.03∼3, y=0.03∼3) 등의 실리콘산화막, HfO2, ZrO2, Hf-Al-O, Hf-실리케이트, Zr-실리케이트 등의 하프늄(Hf) 또는 지르코늄(Zr)을 포함하는 고유전 금속산화물을 이용한다.As shown in FIG. 3A, the gate oxide film 32 is formed on the semiconductor substrate 31, and the polysilicon film 33 is formed on the gate oxide film 32. Here, as the gate oxide film 32, silicon oxide films such as SiO 2 , SiO x N y , x = 0.03 to 3, y = 0.03 to 3), HfO 2 , ZrO 2 , Hf-Al-O, Hf-silicate, A high dielectric metal oxide containing hafnium (Hf) or zirconium (Zr) such as Zr-silicate is used.
다음으로, 폴리실리콘막(33) 형성시 생성된 자연산화막을 제거하기 위해 HF를 포함한 용액을 이용한 세정을 실시하고, 세정된 폴리실리콘막(33)상에 30Å∼200Å 두께의 텅스텐실리콘나이트라이드막(WSixNy)(34)을 형성한다. 계속해서, 텅스텐실리콘나이트라이드막(34)상에 30Å∼200Å 두께의 텅스텐나이트라이드막(WNx)(35)과 텅스텐막(36)을 차례로 형성한다.Next, in order to remove the natural oxide film generated when the polysilicon film 33 is formed, a cleaning using a solution containing HF is performed, and a tungsten silicon nitride film having a thickness of 30 kPa to 200 kPa is formed on the cleaned polysilicon film 33. (WSi x N y ) 34 is formed. Subsequently, a tungsten nitride film (WN x ) 35 and a tungsten film 36 having a thickness of 30 kPa to 200 kPa are sequentially formed on the tungsten silicon nitride film 34.
여기서, 텅스텐실리콘나이트라이드막(34)과 텅스텐나이트라이드막(35)은 텅스텐막(36)과 폴리실리콘막(33)간의 반응 배리어막이다.Here, the tungsten silicon nitride film 34 and the tungsten nitride film 35 are reaction barrier films between the tungsten film 36 and the polysilicon film 33.
먼저, 텅스텐실리콘나이트라이드막(34)은 텅스텐-실리콘 타겟(W-Si target) 또는 텅스텐-실리콘 소스(W-Si source)를 이용하여 스퍼터링법, 화학기상증착법, 원자층증착법을 통해 형성한다.First, the tungsten silicon nitride film 34 is formed by sputtering, chemical vapor deposition, or atomic layer deposition using a tungsten-silicon target (W-Si target) or a tungsten-silicon source (W-Si source).
예컨대, 스퍼터링법을 이용하는 경우, 먼저 고전압이 걸린 진공상태에서 증착챔버내의 텅스텐-실리콘 타겟과 반도체기판(31) 사이에 아르곤(Ar) 가스와 질소(N2) 가스의 혼합 가스를 공급한 다음, 아르곤 가스를 이온화시켜 아르곤 플라즈마를 형성하고, 플라즈마를 구성하는 Ar+이온들을 텅스텐-실리콘 타겟으로 전기장에 의해 가속시켜 텅스텐-실리콘 타겟의 표면과 충돌시킨다. 이러한 충돌에 의한 운동량의 교환에 의하여 텅스텐-실리콘 타겟의 표면 원자나 분자가 튀어나오고, 튀어나온 원자나 분자들(Si+, W+)은 반응가스인 질소(N2) 가스와 화학반응하여 반도체기판(31), 즉 폴리실리콘막(33)상에 텅스텐실리콘나이트라이드막(WSiN)을 증착시킨다.For example, in the case of using the sputtering method, first, a mixed gas of argon (Ar) gas and nitrogen (N 2 ) gas is supplied between the tungsten-silicon target and the semiconductor substrate 31 in the deposition chamber under a high voltage applied vacuum. The argon gas is ionized to form an argon plasma, and the Ar + ions constituting the plasma are accelerated by an electric field with a tungsten-silicon target to collide with the surface of the tungsten-silicon target. The surface atoms or molecules of the tungsten-silicon target are protruded by the exchange of momentum due to such collision, and the protruding atoms or molecules (Si + , W + ) are chemically reacted with nitrogen (N 2 ) gas, which is a reactant gas, A tungsten silicon nitride film WSiN is deposited on the substrate 31, that is, on the polysilicon film 33.
전술한 스퍼터링법 이용시, 질소 가스의 플로우량을 5%∼40%로 유지하고, 파워는 50W∼10000W를 유지하며, 기판온도는 200℃∼400℃를 유지한다. 여기서, 질소 가스의 플로우량, 즉 텅스텐실리콘나이트라이드막(34)내 질소 함량을을 40% 이하로 유지하는 이유는 텅스텐실리콘나이트라이드막(34)내 질소의 함량이 낮을수록 비저항이 낮기 때문이며, 이러한 질소가스의 플로우량에 의해 텅스텐나이트라이드막(35)의 비저항과 비슷한 수준을 제공한다.When using the above-mentioned sputtering method, the flow amount of nitrogen gas is maintained at 5% to 40%, the power is maintained at 50W to 10000W, and the substrate temperature is maintained at 200 ° C to 400 ° C. The reason why the flow rate of nitrogen gas, that is, the nitrogen content in the tungsten silicon nitride film 34 is maintained at 40% or less is because the lower the nitrogen content in the tungsten silicon nitride film 34, the lower the specific resistance. The flow amount of nitrogen gas provides a level similar to the specific resistance of the tungsten nitride film 35.
한편, 텅스텐실리콘나이트라이드막(34), 텅스텐나이트라이드막(35)과 텅스텐막(36)의 증착은 인시튜 또는 엑시튜 상태로 이루어진다.On the other hand, the deposition of the tungsten silicon nitride film 34, the tungsten nitride film 35 and the tungsten film 36 takes place in-situ or ex-situ.
상술한 바와 같이, 폴리실리콘막(33)과 텅스텐막(36) 사이에 반응배리어막으로서 텅스텐실리콘나이트라이드막(34)과 텅스텐나이트라이드막(35)의 적층물을 삽입하므로써 텅스텐나이트라이드막(35)만 삽입되었을 경우에 폴리실리콘막(33)과 텅스텐나이트라이드막(35)의 계면에 반응물이 형성되는 것을 방지한다.As described above, the tungsten nitride film 35 is formed by inserting a laminate of the tungsten silicon nitride film 34 and the tungsten nitride film 35 as the reaction barrier film between the polysilicon film 33 and the tungsten film 36. When only 35 is inserted, the reactants are prevented from being formed at the interface between the polysilicon film 33 and the tungsten nitride film 35.
예컨대, 비록 반응배리어막으로서 텅스텐나이트라이드막이 삽입되었다고는 하나, 후속 선택적 재산화 공정이 O2또는 H2O 성분이 포함된 고온의 산화 공정이므로 폴리실리콘막(33)과 텅스텐나이트라이드막(35)의 계면에 SiON과 같은 반응물이 형성될 가능성이 높다. 따라서, 추가로 텅스텐실리콘나이트라이드막(34)을 삽입하므로써 SiON의 형성을 억제한다.For example, although the tungsten nitride film is inserted as the reaction barrier film, the polysilicon film 33 and the tungsten nitride film 35 are subsequently subjected to the selective reoxidation process because it is a high temperature oxidation process containing an O 2 or H 2 O component. It is highly likely that a reactant such as SiON is formed at the interface of). Therefore, the formation of SiON is further suppressed by inserting the tungsten silicon nitride film 34 further.
도 3b에 도시된 바와 같이, 텅스텐막(36)상에 게이트패터닝을 위한 감광막패턴(37)을 형성한 후, 감광막패턴(37)을 식각마스크로 텅스텐막(36), 텅스텐나이트라이드막(35), 텅스텐실리콘나이트라이드막(34) 및 폴리실리콘막(33)을 차례로 식각하여 폴리실리콘막(33a), 텅스텐실리콘나이트라이드막(34a), 텅스텐나이트라이드막(35a), 텅스텐막(36a)의 순서로 적층된 게이트전극을 형성한다.As shown in FIG. 3B, after the photosensitive film pattern 37 for gate patterning is formed on the tungsten film 36, the tungsten film 36 and the tungsten nitride film 35 are formed using the photosensitive film pattern 37 as an etching mask. ), The tungsten silicon nitride film 34 and the polysilicon film 33 are sequentially etched to form the polysilicon film 33a, the tungsten silicon nitride film 34a, the tungsten nitride film 35a, and the tungsten film 36a. The stacked gate electrodes are formed in the order of.
상술한 게이트전극 형성시, 폴리실리콘막(33a) 식각으로 드러난 게이트산화막(32)의 일부분이 손상을 받는다.When forming the above-described gate electrode, a portion of the gate oxide film 32 exposed by etching the polysilicon film 33a is damaged.
도 3c에 도시된 바와 같이, 감광막패턴(37)을 제거한 후, 게이트산화막(32)의 손상을 회복시켜 주기 위해 850℃∼950℃의 온도와 수소가 많은(H2-rich) H2O 또는 O2분위기에서 선택적 재산화 공정을 수행한다. 선택적 재산화 과정에서 폴리실리콘막(33a)의 에지 및 반도체기판(31)상에 위치하는 게이트산화막(32)은 초기 증착두께보다 증가된 두께를 갖는 GGO막(32a)으로 개질되고, 아울러 폴리실리콘막(33a)의 노출된 측면이 산화됨에 따라 폴리실리콘막(33a)의 측면에 산화막(38)이 형성된다.A, after removing the photoresist pattern 37, in order to restore damage to the gate oxide film 32, the temperature and the hydrogen of 850 ℃ ~950 ℃ many (H 2 -rich) as shown in Figure 3c H 2 O or The selective reoxidation process is carried out in an O 2 atmosphere. In the selective reoxidation process, the gate oxide film 32 positioned on the edge of the polysilicon film 33a and the semiconductor substrate 31 is modified into a GGO film 32a having an increased thickness than the initial deposition thickness. As the exposed side of the film 33a is oxidized, an oxide film 38 is formed on the side of the polysilicon film 33a.
여기서, GGO막(32a)은 초기 증착두께보다 증가된 두께로 형성되면서 폴리실리콘막(33a)의 에지를 소정 부분 침투한 형태를 갖고, 또한 폴리실리콘막(33a) 하부에 위치하는 초기 게이트산화막(32)보다 그 두께가 더 두껍다.Here, the GGO film 32a is formed to have a thickness that is greater than the initial deposition thickness, and has a form that partially penetrates the edge of the polysilicon film 33a, and is also located at the lower portion of the polysilicon film 33a. 32) thicker than that.
상술한 선택적 재산화 공정시, 텅스텐나이트라이드막(35a)과 폴리실리콘막(33a) 사이에 형성된 텅스텐실리콘나이트라이드막(34a)은 텅스텐막(36a)과 폴리실리콘막(33a)간의 반응을 억제하는 반응배리어막 역할을 수행하며, 또한 그 형태를 유지하면서 텅스텐나이트라이드막(35a)과 폴리실리콘막(33a)의 계면에 실리콘나이트라이드막, 실리콘옥시나이트라이드막, 실리콘산화막과 같은 반응물이 형성되는 것을 억제한다.In the selective reoxidation process described above, the tungsten silicon nitride film 34a formed between the tungsten nitride film 35a and the polysilicon film 33a suppresses the reaction between the tungsten film 36a and the polysilicon film 33a. And a reactant such as a silicon nitride film, a silicon oxynitride film, or a silicon oxide film is formed at the interface between the tungsten nitride film 35a and the polysilicon film 33a while maintaining its shape. Suppress what happens.
후속 공정으로, 도면에 도시되지 않았지만, LDD 영역을 형성하기 위한 저농도 불순물 이온주입을 실시하고, 게이트전극 패턴의 양측벽에 접하는 스페이서를 형성한 후 소스/드레인영역을 형성하기 위한 고농도 불순물 이온주입을 실시한다.In a subsequent process, although not shown in the drawing, a low concentration impurity ion implantation for forming an LDD region is performed, and a high concentration impurity ion implantation for forming a source / drain region is formed after forming a spacer in contact with both side walls of the gate electrode pattern. Conduct.
그리고, 각각의 트랜지스터들을 절연시켜주기 위한 층간절연막을 형성하고,소스, 드레인 및 게이트전극을 외부단자와 연결시켜주기 위한 금속화 공정을 실시한다.Then, an interlayer insulating film is formed to insulate each transistor, and a metallization process is performed to connect the source, drain, and gate electrodes with external terminals.
도 4a 내지 도 4c는 본 발명의 제3 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도이다.4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.
도 4a에 도시된 바와 같이, 반도체기판(41)상에 게이트산화막(42)을 형성하고, 게이트산화막(42)상에 폴리실리콘막(43)을 형성한다. 여기서, 게이트산화막(42)으로는 SiO2, SiOxNy, x=0.03∼3, y=0.03∼3) 등의 실리콘산화막, HfO2, ZrO2, Hf-Al-O, Hf-실리케이트, Zr-실리케이트 등의 하프늄(Hf) 또는 지르코늄(Zr)을 포함하는 고유전 금속산화물을 이용한다.As shown in FIG. 4A, the gate oxide film 42 is formed on the semiconductor substrate 41, and the polysilicon film 43 is formed on the gate oxide film 42. Here, as the gate oxide film 42, silicon oxide films such as SiO 2 , SiO x N y , x = 0.03 to 3, y = 0.03 to 3), HfO 2 , ZrO 2 , Hf-Al-O, Hf-silicate, A high dielectric metal oxide containing hafnium (Hf) or zirconium (Zr) such as Zr-silicate is used.
다음으로, 폴리실리콘막(43) 형성시 생성된 자연산화막을 제거하기 위해 HF를 포함한 용액을 이용한 세정을 실시하고, 세정된 폴리실리콘막(43)상에 50Å∼200Å 두께의 텅스텐실리사이드막(WxSiy)(44)을 형성한다. 계속해서, 텅스텐실리사이드막(44)상에 30Å∼200Å 두께의 텅스텐나이트라이드막(45)과 텅스텐막(46)을 차례로 형성한다.Next, in order to remove the natural oxide film generated when the polysilicon film 43 is formed, washing is performed using a solution containing HF, and a tungsten silicide film (W) having a thickness of 50 kPa to 200 kPa is formed on the cleaned polysilicon film 43. x Si y ) 44 is formed. Subsequently, a tungsten nitride film 45 and a tungsten film 46 having a thickness of 30 kPa to 200 kPa are sequentially formed on the tungsten silicide film 44.
먼저, 텅스텐실리사이드막(44)은 텅스텐-실리콘 타겟(W-Si target) 또는 텅스텐-실리콘 소스(W-Si source)를 이용하여 스퍼터링법, 화학기상증착법, 원자층증착법을 통해 형성한다.First, the tungsten silicide layer 44 is formed by sputtering, chemical vapor deposition, or atomic layer deposition using a tungsten-silicon target (W-Si target) or a tungsten-silicon source (W-Si source).
예컨대, 스퍼터링법을 이용하는 경우, 먼저 고전압이 걸린 진공상태에서 증착챔버내의 텅스텐-실리콘 타겟과 반도체기판(31) 사이에 아르곤(Ar) 가스를 공급한 다음, 아르곤 가스를 이온화시켜 아르곤 플라즈마를 형성하고, 플라즈마를 구성하는 Ar+이온들을 텅스텐-실리콘 타겟으로 전기장에 의해 가속시켜 텅스텐-실리콘 타겟의 표면과 충돌시킨다. 이러한 충돌에 의한 운동량의 교환에 의하여 텅스텐-실리콘 타겟의 표면 원자나 분자가 튀어나오고, 튀어나온 원자나 분자들(Si+, W+)은 화학반응하여 반도체기판(41), 즉 폴리실리콘막(43)상에 텅스텐실리사이드막(WSi)을 증착시킨다.For example, in the case of using the sputtering method, first, argon (Ar) gas is supplied between the tungsten-silicon target in the deposition chamber and the semiconductor substrate 31 in a vacuum under high voltage, and then the argon gas is ionized to form an argon plasma. Ar + ions constituting the plasma are accelerated by an electric field with a tungsten-silicon target to collide with the surface of the tungsten-silicon target. The surface atoms or molecules of the tungsten-silicon target are protruded by the exchange of momentum due to such collision, and the protruding atoms or molecules (Si + , W + ) are chemically reacted to form the semiconductor substrate 41, that is, the polysilicon film ( 43, a tungsten silicide film WSi is deposited.
전술한 스퍼터링법 이용시, 파워는 50W∼10000W를 유지하며, 기판온도는 200℃∼400℃를 유지한다.When using the above-mentioned sputtering method, the power is maintained at 50W to 10000W and the substrate temperature is maintained at 200 ° C to 400 ° C.
한편, 텅스텐실리사이드막(44), 텅스텐나이트라이드막(45)과 텅스텐막(46)의 증착은 인시튜 또는 엑시튜 상태로 이루어진다.On the other hand, the deposition of the tungsten silicide film 44, the tungsten nitride film 45 and the tungsten film 46 takes place in-situ or ex-situ.
도 4b에 도시된 바와 같이, 텅스텐막(46)상에 게이트패터닝을 위한 감광막패턴(47)을 형성한 후, 감광막패턴(47)을 식각마스크로 텅스텐막(46), 텅스텐나이트라이드막(45), 텅스텐실리콘나이트라이드막(44) 및 폴리실리콘막(43)을 차례로 식각하여 폴리실리콘막(43a), 텅스텐실리사이드막(44a), 텅스텐나이트라이드막(45a), 텅스텐막(46a)의 순서로 적층된 게이트전극을 형성한다.As shown in FIG. 4B, after the photosensitive film pattern 47 for gate patterning is formed on the tungsten film 46, the tungsten film 46 and the tungsten nitride film 45 are formed by using the photosensitive film pattern 47 as an etching mask. ), The tungsten silicon nitride film 44 and the polysilicon film 43 are sequentially etched in order of the polysilicon film 43a, the tungsten silicide film 44a, the tungsten nitride film 45a, and the tungsten film 46a. The stacked gate electrodes are formed.
상술한 게이트전극 형성시, 폴리실리콘막(43a) 식각으로 드러난 게이트산화막(42)의 일부분이 손상을 받는다.When forming the above-described gate electrode, a part of the gate oxide film 42 exposed by etching the polysilicon film 43a is damaged.
도 4c에 도시된 바와 같이, 감광막패턴(47)을 제거한 후, 게이트산화막(42)의 손상을 회복시켜 주기 위해 850℃∼950℃의 온도와 수소가 많은(H2-rich) H2O 또는 O2분위기에서 선택적 재산화 공정을 수행한다. 선택적 재산화 과정에서 폴리실리콘막(43a)의 에지 및 반도체기판(41)상에 위치하는 게이트산화막(42)은 초기 증착두께보다 증가된 두께를 갖는 GGO막(42a)으로 개질되고, 아울러 폴리실리콘막(43a)의 노출된 측면이 산화됨에 따라 폴리실리콘막(43a)의 측면에 산화막(48)이 형성된다.As shown in FIG. 4C, after the photoresist pattern 47 is removed, a temperature of 850 ° C. to 950 ° C. and H 2 O-rich or H 2 -rich to recover damage of the gate oxide film 42 or The selective reoxidation process is carried out in an O 2 atmosphere. In the selective reoxidation process, the gate oxide film 42 positioned on the edge of the polysilicon film 43a and on the semiconductor substrate 41 is modified into a GGO film 42a having an increased thickness than the initial deposition thickness. As the exposed side of the film 43a is oxidized, an oxide film 48 is formed on the side of the polysilicon film 43a.
여기서, GGO막(42a)은 초기 증착두께보다 증가된 두께로 형성되면서 폴리실리콘막(43a)의 에지를 소정 부분 침투한 형태를 갖고, 또한 폴리실리콘막(43a) 하부에 위치하는 초기 게이트산화막(42)보다 그 두께가 더 두껍다.Here, the GGO film 42a is formed to have a thickness that is greater than the initial deposition thickness, and has a form that partially penetrates the edge of the polysilicon film 43a and is also located at the lower portion of the polysilicon film 43a. 42) thicker than that.
상술한 선택적 재산화 공정시, 텅스텐나이트라이드막(45a)과 폴리실리콘막(43a) 사이에 형성된 텅스텐실리사이드막(44a)이 텅스텐실리콘나이트라이드막(44b)으로 개질된다. 이는 선택적 재산화 공정시 텅스텐나이트라이드막(45a)내 질소가 텅스텐실리사이드막(44a)으로 확산하기 때문이다. 한편, 텅스텐실리콘나이트라이드막(44b)내 질소 함량은 5%∼40%을 유지한다.In the selective reoxidation process described above, the tungsten silicide film 44a formed between the tungsten nitride film 45a and the polysilicon film 43a is modified with the tungsten silicon nitride film 44b. This is because nitrogen in the tungsten nitride film 45a diffuses into the tungsten silicide film 44a during the selective reoxidation process. On the other hand, the nitrogen content in the tungsten silicon nitride film 44b is maintained at 5% to 40%.
결국, 상술한 선택적 재산화 공정시, 텅스텐나이트라이드막(45a)과 폴리실리콘막(43a) 사이에 형성되는 텅스텐실리콘나이트라이드막(44b)은 텅스텐막(46a)과 폴리실리콘막(43a)간의 반응을 억제하는 반응배리어막 역할을 수행하며, 또한 그 형태를 유지하면서 텅스텐나이트라이드막(45a)과 폴리실리콘막(43a)의 계면에 실리콘나이트라이드막, 실리콘옥시나이트라이드막, 실리콘산화막과 같은 반응물이 형성되는 것을 억제한다.As a result, in the above-described selective reoxidation process, the tungsten silicon nitride film 44b formed between the tungsten nitride film 45a and the polysilicon film 43a is formed between the tungsten film 46a and the polysilicon film 43a. It serves as a reaction barrier film that suppresses the reaction, and also maintains its shape at the interface between the tungsten nitride film 45a and the polysilicon film 43a, such as a silicon nitride film, a silicon oxynitride film, and a silicon oxide film. Suppresses the formation of reactants.
후속 공정으로, 도면에 도시되지 않았지만, LDD 영역을 형성하기 위한 저농도 불순물 이온주입을 실시하고, 게이트전극 패턴의 양측벽에 접하는 스페이서를 형성한 후 소스/드레인영역을 형성하기 위한 고농도 불순물 이온주입을 실시한다.In a subsequent process, although not shown in the drawing, a low concentration impurity ion implantation for forming an LDD region is performed, and a high concentration impurity ion implantation for forming a source / drain region is formed after forming a spacer in contact with both side walls of the gate electrode pattern. Conduct.
그리고, 각각의 트랜지스터들을 절연시켜주기 위한 층간절연막을 형성하고, 소스, 드레인 및 게이트전극을 외부단자와 연결시켜주기 위한 금속화 공정을 실시한다.Then, an interlayer insulating film is formed to insulate each transistor, and a metallization process is performed to connect the source, drain, and gate electrodes with external terminals.
한편, 전술한 제1, 제2 및 제3 실시예에서는 금속 게이트전극막으로 텅스텐막을 예로 들었으나, 다른 금속막을 적용하는 경우에도 적용 가능하다.On the other hand, although the tungsten film is taken as the metal gate electrode film as an example in the first, second and third embodiments described above, it is also applicable to the case where other metal films are applied.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 후속 선택적 재산화 및 후속 산화분위기의 열공정에서 폴리실리콘막과 금속막의 계면에 산화막 또는 반응층이 형성되는 것을 억제하므로써 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.The present invention as described above has the effect of improving the reliability of the semiconductor device by suppressing the formation of the oxide film or the reaction layer at the interface between the polysilicon film and the metal film in the subsequent selective reoxidation and thermal process of the subsequent oxidation atmosphere.
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KR101122756B1 (en) * | 2008-06-30 | 2012-03-23 | 주식회사 하이닉스반도체 | Semiconductor device with single layer diffusion barrier and method for fabricating the same |
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KR101122756B1 (en) * | 2008-06-30 | 2012-03-23 | 주식회사 하이닉스반도체 | Semiconductor device with single layer diffusion barrier and method for fabricating the same |
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