KR20040001542A - Method for forming isolation film in semiconductor device - Google Patents
Method for forming isolation film in semiconductor device Download PDFInfo
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- KR20040001542A KR20040001542A KR1020020036774A KR20020036774A KR20040001542A KR 20040001542 A KR20040001542 A KR 20040001542A KR 1020020036774 A KR1020020036774 A KR 1020020036774A KR 20020036774 A KR20020036774 A KR 20020036774A KR 20040001542 A KR20040001542 A KR 20040001542A
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- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000002955 isolation Methods 0.000 title abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000011521 glass Substances 0.000 claims abstract description 5
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 239000000126 substance Substances 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 230000000452 restraining effect Effects 0.000 abstract 1
- 238000000576 coating method Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 상세하게는 마이크로트렌치의 발생을 억제할 수 있는 반도체 소자의 소자분리막 형성방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a device isolation film formation method of a semiconductor device capable of suppressing the generation of micro trenches.
최근의 반도체 제조기술은 고집적화를 요구한다. 따라서, 모스펫(MOSFET)의 게이트 선폭 축소 기술과 더불어 소자의 격리 기술이 반도체 소자의 고집적화에 가장 밀접하게 연관되어 있고 이를 향상시키 위해 각 분야에서 많은 노력을 기울이고 있다.Recent semiconductor manufacturing techniques require high integration. Therefore, isolation technology of the device, in addition to the gate line width reduction technology of the MOSFET (MOSFET) is most closely related to the high integration of the semiconductor device and a lot of efforts in each field to improve it.
이를 위해 소자 격리 기술에서는 주로 리세스 국부산화법(Recessed LOCOS) 기술로 어느 정도 효과를 나타내었으나, 0.25㎛ 이하부터는 거의 모든 소자에 트렌치(Trench) 형성기술을 이용하고 있다.To this end, the device isolation technology mainly exhibits a recessed LOCOS technique, but trench forming technology is used in almost all devices from 0.25 µm or less.
종래 기술에 따른 반도체 소자의 소자분리막 형성방법을 개략적으로 설명하면 다음과 같다.A device isolation film forming method of a semiconductor device according to the prior art will be described as follows.
종래 기술에 따른 반도체 소자의 소자분리막 형성방법은, 도 1에 도시된 바와 같이, 실리콘 기판(10)위에 패드 산화막(20)과 질화막(30)을 증착한 후 감광막(미도시)을 코팅한다.In the method of forming a device isolation film of a semiconductor device according to the related art, as illustrated in FIG. 1, a pad oxide film 20 and a nitride film 30 are deposited on a silicon substrate 10 and then coated with a photosensitive film (not shown).
이어서, 상기 감광막(미도시)을 마스크로 하는 건식각을 진행하여 상기 질화막(30)과 패드 산화막(20) 및 기판(10) 일부를 제거하여 트렌치(40)를 형성한다. 그다음, 상기 트렌치(40)를 산화막으로 매립하여 소자분리막(50)을 완성한다.Subsequently, a dry etching process using the photoresist layer (not shown) as a mask is performed to form the trench 40 by removing the nitride layer 30, the pad oxide layer 20, and a part of the substrate 10. Next, the trench 40 is filled with an oxide film to complete the device isolation film 50.
그러나, 종래 기술에 따른 반도체 소자의 소자분리막 형성방법에 있어서는 다음과 같은 문제점이 있다.However, the method of forming a device isolation film of a semiconductor device according to the prior art has the following problems.
종래 기술에 있어서는 트렌치를 매립하기 위하여 산화막을 증착하게 되면 액티브 영역과 필드 영역간에는 트렌치에 따른 산화막 단차가 발생한다. 따라서, 종래에는 산화막 단차를 줄이기 위해 상대적으로 두껍게 증착된 액티브 영역상의 산화막을 제거하여 필드 영역상에 증착된 산화막과 평탄화를 이루는 평탄화 공정을 더 진행한다.In the related art, when an oxide film is deposited to fill a trench, an oxide film step according to a trench occurs between the active region and the field region. Therefore, in order to reduce the oxide film step, the planarization process of removing the oxide film on the active region deposited relatively thick is performed to planarize the oxide film deposited on the field region.
상기와 같은 평탄화 공정을 더 진행하게 되면 전체적으로는 공정수가 증가하게 되고 또한 도 1의 A영역과 같은 마이크로트렌치(microtrench)가 발생하게 된다. 따라서, 후속 공정에서 질화막(30)이 어택(attack)을 받게 되고 이로 인하여 액티브 영역까지도 어택(attack)을 받을 위험성이 있게 된다.If the above planarization process is further performed, the number of processes increases as a whole, and microtrench such as region A of FIG. 1 is generated. Therefore, in the subsequent process, the nitride film 30 is attacked, and thus there is a risk of attacking even the active region.
이에 본 발명은 상기한 종래 기술상의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 별도로 평탄화 공정을 실시하지 않고 코팅방식으로 산화막을 증착하여 1차적으로 평탄화시키고 화학적 기계적 연마로 평탄화시켜 액티브 영역과 필드 영역간의 단차를 없애고 마이크로트렌치 발생을 억제할 수 있는 반도체 소자의 소자분리막 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-mentioned problems in the prior art, and an object of the present invention is to first planarize by depositing an oxide film by a coating method and to planarize by chemical mechanical polishing without performing a planarization process separately. The present invention provides a method of forming a device isolation film of a semiconductor device capable of eliminating a step between a region and a field region and suppressing micro trench generation.
도 1은 종래 기술에 따른 반도체 소자의 소자분리막 형성방법을 도시한 단면도.1 is a cross-sectional view showing a device isolation film forming method of a semiconductor device according to the prior art.
도 2 내지 도 6은 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 도시한 공정별 단면도.2 to 6 are cross-sectional views illustrating processes of forming an isolation layer of a semiconductor device in accordance with the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100; 반도체 기판200,200a; 패드 산화막100; Semiconductor substrates 200 and 200a; Pad oxide
300,300a; 질화막400; 트렌치300,300a; Nitride film 400; Trench
500; 제1산화막500a; 소자분리막500; A first oxide film 500a; Device Separator
600; 제2산화막600; Second oxide film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 소자분리막 형성방법은, 반도체 기판상에 패드 산화막과 질화막을 순차로 형성하는 단계; 상기 질화막과 패드 산화막 및 기판을 선택적으로 제거하여 트렌치를 형성하는 단계; 상기 트렌치를 매립하도록 상기 기판 전면상에 제1산화막을 형성하는 단계; 상기 제1산화막 표면의 단차를 없앨 수 있도록 제2산화막을 형성하는 단계; 및 상기 질화막이 노출되도록 상기 제2산화막 및 제1산화막을 제거하는 단계를 포함하는 것을 특징으로 한다.A device isolation film forming method of a semiconductor device according to the present invention for achieving the above object comprises the steps of sequentially forming a pad oxide film and a nitride film on a semiconductor substrate; Selectively removing the nitride film, the pad oxide film, and the substrate to form a trench; Forming a first oxide film on the entire surface of the substrate to fill the trench; Forming a second oxide film so as to eliminate a step on the surface of the first oxide film; And removing the second oxide film and the first oxide film so that the nitride film is exposed.
상기 제2산화막은 스핀-온-글래스(SOG) 산화막이고 코팅 방식을 이용하는 것을 특징으로 한다.The second oxide film is a spin-on-glass (SOG) oxide film and is characterized by using a coating method.
본 발명에 의하면, 증착된 산화막에 대한 별도의 평탄화 공정을 실시하지 않아도 된다.According to the present invention, it is not necessary to perform a separate planarization process for the deposited oxide film.
이하, 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a device isolation film of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2 내지 도 6은 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 각 공정별 단면도이다.2 to 6 are cross-sectional views of respective processes for explaining a method of forming a device isolation film of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 소자분리막 형성방법은, 도 2에 도시된 바와 같이, 먼저 반도체 기판(100)상에 패드 산화막(200)과 질화막(300)을 순차로 형성한다. 상기 패드 산화막(200)은 상기 질화막(300)에 의한 상기 기판(100)의 응력을 방지하기 위함이다.In the method of forming a device isolation layer of a semiconductor device according to the present invention, as shown in FIG. The pad oxide film 200 is for preventing the stress of the substrate 100 by the nitride film 300.
그다음, 도 3에 도시된 바와 같이, 상기 질화막(300)상에 감광막 패턴(미도시)를 형성한 다음, 상기 감광막 패턴(미도시)을 마스크로 하는 식각 공정으로 상기 질화막(300)과 패드 산화막(200)을 선택적으로 제거한다.Next, as shown in FIG. 3, a photoresist pattern (not shown) is formed on the nitride film 300, and the nitride film 300 and the pad oxide film are formed by an etching process using the photoresist pattern (not shown) as a mask. Optionally remove 200.
이어서, 선택적으로 제거되어 패터닝된 질화막(300a)과 패드 산화막(200a)을 마스크로 하는 식각 공정으로 상기 기판(100)을 선택적으로 제거하여 트렌치(400)를 형성한다.Subsequently, the trench 100 may be formed by selectively removing the substrate 100 by an etching process using the nitride film 300a and the pad oxide film 200a which are selectively removed and patterned.
한편, 트렌치(400) 식각 공정 이후 에지 모우트(edge moat)를 방지하기 위하여 산화 공정을 실시하여 상기 트렌치(400)의 모서리부를 곡선형으로 처리하는 코너 라운딩(corner rounding) 과정을 실시하기도 한다.Meanwhile, a corner rounding process may be performed to process an edge of the trench 400 in a curved manner by performing an oxidation process to prevent edge moats after the trench 400 is etched.
그다음, 도 4에 도시된 바와 같이, 상기 트렌치(400)를 충분히 매립할 수 있을 정도로 상기 기판(100) 전면상에 제1산화막(500)을 형성한다. 상기 제1산화막(500)은 후속 공정에 의해 소자의 절연막 역할을 하는 필드 산화막(field oxide), 즉 소자분리막으로 형성된다.Next, as shown in FIG. 4, the first oxide film 500 is formed on the entire surface of the substrate 100 to sufficiently fill the trench 400. The first oxide film 500 is formed of a field oxide, that is, a device isolation film, serving as an insulating film of the device by a subsequent process.
이때, 상기 제1산화막(500) 표면은 트렌치(400)가 형성된 기판(100)의 굴곡 형태대도 트렌치(400) 부분은 상대적으로 낮은 높이를 가지는 단차가 형성된다.At this time, the surface of the first oxide film 500 may have a step having a relatively low height even in a curved shape of the substrate 100 on which the trench 400 is formed.
이어서, 도 5에 도시된 바와 같이, 상기 제1산화막(500) 표면의 단차를 없앨 수 있도록 제2산화막(600)을 형성한다. 상기 제2산화막(600)은, 예를 들어, 스핀-온-글래스(SOG) 산화막을 코팅(coating) 방식으로 증착하여 형성한다. 일반적인 산화물의 증착은 단차 차이를 그대로 따라서 증착이 되지만 스핀-온-글래스(SOG) 산화막 코팅과 같은 방식은 단차 차이를 줄이고 평탄하게 증착된다.Subsequently, as shown in FIG. 5, the second oxide film 600 is formed to eliminate the step difference on the surface of the first oxide film 500. The second oxide film 600 is formed by, for example, depositing a spin-on-glass (SOG) oxide film by a coating method. In general, the deposition of oxides is performed according to the step difference, but a method such as spin-on-glass (SOG) oxide coating reduces the step difference and is deposited flat.
그다음, 도 6에 도시된 바와 같이, 패터닝된 질화막(300a)이 노출되도록 상기 제2산화막(600) 및 제1산화막(500)을 화학적 기계적 연마(CMP) 공정을 이용하여 평탄화시켜 소자분리막(500a)을 형성한다.Next, as shown in FIG. 6, the second oxide film 600 and the first oxide film 500 are planarized by using a chemical mechanical polishing (CMP) process to expose the patterned nitride film 300a. ).
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 소자분리막 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the device isolation film forming method of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 증착된 산화막에 대한 별도의 평탄화 공정을 실시하지 않아도 되므로 전체적인 공정수를 감소시킬 수 있으며, 공정수의 감소에 따라 불순물 발생과 마이크로트렌치 발생을 억제할 수 있어 액티브 영역에 대한 어택을 미연에 방지할 수 있는 효과가 있다.In the present invention, it is not necessary to perform a separate planarization process for the deposited oxide film, thereby reducing the overall number of processes, and as the number of processes decreases, impurities and micro trenches can be suppressed to attack the active region. There is an effect that can be prevented in advance.
Claims (3)
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| KR1020020036774A KR20040001542A (en) | 2002-06-28 | 2002-06-28 | Method for forming isolation film in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20160069138A (en) * | 2014-12-08 | 2016-06-16 | 주성엔지니어링(주) | Substrate disposition method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20160069138A (en) * | 2014-12-08 | 2016-06-16 | 주성엔지니어링(주) | Substrate disposition method |
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