KR20040001507A - Method for forming borderless contact hole in semiconductor device - Google Patents
Method for forming borderless contact hole in semiconductor device Download PDFInfo
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- KR20040001507A KR20040001507A KR1020020036725A KR20020036725A KR20040001507A KR 20040001507 A KR20040001507 A KR 20040001507A KR 1020020036725 A KR1020020036725 A KR 1020020036725A KR 20020036725 A KR20020036725 A KR 20020036725A KR 20040001507 A KR20040001507 A KR 20040001507A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000002955 isolation Methods 0.000 claims abstract description 76
- 239000000463 material Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 239000012212 insulator Substances 0.000 claims abstract description 5
- 230000000903 blocking effect Effects 0.000 claims description 25
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 230000008646 thermal stress Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000005137 deposition process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
Description
본 발명은 반도체 소자의 보더레스 콘택홀 형성방법에 관한 것으로, 보다 상세하게는 소스/드레인 영역과 웰 영역의 단선을 예방할 수 있는 반도체 소자의 보더레스 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for forming a borderless contact hole in a semiconductor device, and more particularly, to a method for forming a borderless contact hole in a semiconductor device capable of preventing disconnection between a source / drain region and a well region.
최근의 반도체 소자를 제조하는데 있어서 고집적화와 고성능화를 위해 수많은 연구가 행해져 왔다. 이러한 일환으로 게이트 선폭의 축소, 구리배선 공정 기술 등 많은 기술 발전이 이루어져 왔다. 특히, 소스/드레인/게이트와 금속배선의 연결부위인 콘택홀의 경우는 보더레스(borderless) 콘택 기술을 이용하여 고집적화 및 고성능화를 이루고 있다.In recent years, numerous studies have been conducted for high integration and high performance in manufacturing semiconductor devices. As part of this, many technological advances have been made, such as reduction of gate line width and copper wiring process technology. In particular, in the case of a contact hole, which is a connection portion between a source / drain / gate and a metal wiring, borderless contact technology is used to achieve high integration and high performance.
종래 기술에 따른 반도체 소자의 보더레스 콘택홀 형성방법을 도 1 내지 도 3을 참조하여 설명하면 다음과 같다.A method of forming a borderless contact hole of a semiconductor device according to the related art will be described with reference to FIGS. 1 to 3 as follows.
종래 기술에 따른 반도체 소자의 보더레스 콘택홀 형성방법은, 도 1에 도시된 바와 같이, 실리콘 기판(10)에 대한 선택적 제거 및 산화물 매립으로 소자분리막(20)을 형성한다.In the method for forming a borderless contact hole of a semiconductor device according to the related art, the device isolation layer 20 is formed by selective removal of the silicon substrate 10 and oxide filling, as shown in FIG. 1.
이어서, 도 2에 도시된 바와 같이, 자기정렬 규화물층(30)(self-aligned silicide)과 질화막(40)을 상기 기판(10)상의 소정부위에 순차로 형성한다.Subsequently, as shown in FIG. 2, a self-aligned silicide layer 30 and a nitride film 40 are sequentially formed at predetermined portions on the substrate 10.
그다음, 도 3에 도시된 바와 같이, 상기 기판(10) 전면상에 PMD (polysilicon-metal-dielectric) 물질층(50)의 증착과 식각으로 보더레스 콘택홀(60)을 형성한다.Next, as shown in FIG. 3, the borderless contact hole 60 is formed by deposition and etching of the polysilicon-metal-dielectric (PMD) material layer 50 on the entire surface of the substrate 10.
그러나, 종래 기술에 따른 반도체 소자의 보더레스 콘택홀 형성방법에 있어서는 다음과 같은 문제점이 있다.However, there is a problem in the method for forming a borderless contact hole of a semiconductor device according to the prior art.
종래 기술에 있어서는, 소스/드레인 영역과 소자분리 영역의 적층한계를 넘어섰고, 특히 SRAM과 같은 설계법칙(design rule)의 여유가 매우 좁은 소자는 콘택홀과 소스/드레인 등의 접촉시 접합(junction) 부위를 침범하는 사례가 빈번히 발생되고 있다.In the prior art, the stacking limit of the source / drain region and the device isolation region is exceeded. In particular, a device with a very small margin of design rule such as SRAM is a junction in contact between the contact hole and the source / drain. ) Are frequently invaded.
이러한 현상은 콘택홀 건식각시 하지막에 대한 선택비 구현이 용이한 질화막을 주로 사용함으로 인해 발생되는 문제이며, 자기정렬 규화물(salicide) 등의 형성공정까지의 세정공정으로 인해 소자분리막이 손실되기 때문에 발생되는 문제이기도 하다.This phenomenon is a problem caused by using a nitride film that is easy to implement the selectivity for the underlying film during the contact hole dry etching, and the device isolation film is lost due to the cleaning process until the formation process of the self-aligned silicide (salicide), etc. It is also a problem.
또한, 소자분리막의 평탄화 공정시 증착두께의 미세한 차이와 연마균일도 정도에 따라서 식각해야할 산화막 두께 변화를 초래함으로 인해 식각 목표의 높이 차이가 발생하기도 한다. 따라서, 보더레스 콘택홀 식각 공정에서의 공정여유도를 좁히는 장애요인이 되며, 질화막 아래로의 플러그 침투를 유발하여 접합 누설전류의 원인이 되기도 한다.In addition, in the planarization process of the device isolation layer, the height difference of the etching target may occur due to the change in the thickness of the oxide film to be etched according to the minute difference in deposition thickness and the degree of polishing uniformity. Therefore, it becomes a barrier to narrow the process margin in the borderless contact hole etching process, and also causes the plug leakage into the nitride film and causes the junction leakage current.
이에 본 발명은 상기한 종래 기술상의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 트렌치의 측벽을 따라 식각되는 산화막의 손실을 막으므로써 소스/드레인 영역과 웰 영역의 단선을 예방하고, 산화막에 질화막이 부분적으로 추가됨으로써 소자분리 특성의 향상도 꾀할 수 있는 반도체 소자의 보더레스 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-described problems in the prior art, an object of the present invention is to prevent the loss of the oxide film etched along the sidewalls of the trench to prevent the disconnection of the source / drain region and the well region, The present invention provides a method for forming a borderless structure of a semiconductor device, in which a nitride film is partially added to the device to improve device isolation characteristics.
도 1 내지 도 3은 종래 기술에 따른 반도체 소자의 보더레스 콘택홀 형성방법을 설명하기 위한 공정별 단면도.1 to 3 is a cross-sectional view for each process for explaining a method for forming a borderless contact hole of a semiconductor device according to the prior art.
도 4 내지 도 11은 본 발명에 따른 반도체 소자의 보더레스 콘택홀 형성방법을 설명하기 위한 공정별 단면도.4 to 11 are cross-sectional views for each process for explaining a method for forming a borderless contact hole in a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100; 반도체 기판105; 트렌치100; A semiconductor substrate 105; Trench
110; 제1패드막120; 제2패드막110; First pad layer 120; 2nd pad film
130a; 제1소자분리막140a; 차단막130a; A first device isolation layer 140a; Barrier
150a; 제2소자분리막160; 소자분리막150a; Second device isolation layer 160; Device Separator
170; 자기정렬 규화물층180; 하지막170; Self-aligned silicide layer 180; Lower curtain
190; PMD 물질층200; 보더레스 콘택홀190; PMD material layer 200; Borderless Contact Hall
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 보더레스 콘택홀형성방법은, 반도체 기판상에 제1패드막과 제2패드막을 순차로 형성하는 단계; 상기 제2패드막과 제1패드막 및 기판을 선택적으로 제거하여 트렌치를 형성하는 단계; 상기 트렌치를 매립하도록 상기 기판 전면상에 제1소자분리막 물질층을 형성하는 단계; 상기 제1소자분리막 물질층의 일부 제거로 상기 트렌치를 부분 매립하는 제1소자분리막을 형성하는 단계; 상기 제2패드막을 제거한 후 상기 제1소자분리막을 포함한 상기 기판 전면상에 차단막 물질층을 형성하는 단계; 상기 차단막 물질층이 형성된 기판 전면상에 제2소자분리막 물질층을 형성하는 단계; 상기 제1패드막이 노출되도록 하는 상기 제2소자분리막 물질층과 차단막 물질층의 일부제거로 차단막과 제2소자분리막을 형성하여 상기 트렌치내에 상기 제1소자분리막과 차단막 및 제2소자분리막으로 이루어진 소자분리막을 형성하는 단계; 상기 제1패드막을 제거한 후 상기 기판상에 자기정렬 규화물층과 식각정지막을 순차로 형성하는 단계; 및 상기 식각정지막상에 PMD(폴리실리콘-금속-절연체) 물질층의 증착과 식각으로 상기 차단막에 의해 상기 소자분리막이 개방되지 않는 보더레스 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming a borderless contact hole in a semiconductor device, the method comprising: sequentially forming a first pad film and a second pad film on a semiconductor substrate; Selectively removing the second pad layer, the first pad layer, and the substrate to form a trench; Forming a first device isolation layer material layer over the entire surface of the substrate to fill the trench; Forming a first device isolation film partially filling the trench by removing a portion of the first device isolation material layer; Removing the second pad layer and forming a blocking layer material layer on an entire surface of the substrate including the first device isolation layer; Forming a second device isolation layer material layer on an entire surface of the substrate on which the blocking material layer is formed; A device comprising the first device isolation layer, the blocking layer, and the second device isolation layer in the trench by forming a blocking layer and a second device isolation layer by partially removing the second device isolation layer material layer and the blocking layer material layer to expose the first pad layer Forming a separator; Removing the first pad layer and sequentially forming a self-aligned silicide layer and an etch stop layer on the substrate; And forming a borderless contact hole in which the device isolation layer is not opened by the blocking layer by etching and etching the PMD (polysilicon-metal-insulator) material layer on the etch stop layer.
본 발명에 의하면, 보더레스 콘택홀을 매립하는 플러그가 형성되어도 트렌치 측벽부의 소자분리막이 손실되지 않는다.According to the present invention, the device isolation film of the trench sidewall portion is not lost even when a plug for filling the borderless contact hole is formed.
이하, 본 발명에 따른 반도체 소자의 보더레스 콘택홀을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a borderless contact hole of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 4 내지 도 11은 본 발명에 따른 반도체 소자의 보더레스 콘택홀 형성방법을 설명하기 위한 공정별 단면도이다.4 to 11 are cross-sectional views illustrating processes for forming a borderless contact hole of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 보더레스 콘택홀 형성방법은, 도 4에 도시된 바와 같이, 실리콘과 같은 반도체로 이루어진 기판(100)상에 제1패드막(110)과 제2패드막(120)을 순차로 형성한다. 상기 제1패드막(110)은 상기 기판(100)을 구성하는 실리콘과 상기 제2패드막(120)을 구성하는 질화막 또는 산화질화막간의 열적응력을 완화하는 역할을 담당하기 위하여 산화막을 5~20Å 두께로 증착하여 형성한다.In the method for forming a borderless contact hole of a semiconductor device according to the present invention, as illustrated in FIG. 4, the first pad film 110 and the second pad film 120 are formed on a substrate 100 made of a semiconductor such as silicon. Are formed sequentially. The first pad layer 110 may have an oxide film of 5 to 20 kV in order to relieve thermal stress between the silicon constituting the substrate 100 and the nitride film or the oxynitride layer constituting the second pad film 120. It is formed by depositing to a thickness.
이어서, 도 5에 도시된 바와 같이, 상기 제2패드막(120)과 제1패드막(110) 및 기판(100)을 건식각 등으로 선택적으로 제거한다. 그리하여, 상기 패터닝된 제2패드막(120a)과 제1패드막(110a) 및 기판(100a)에 트렌치(105)를 형성한다.Subsequently, as shown in FIG. 5, the second pad layer 120, the first pad layer 110, and the substrate 100 are selectively removed by dry etching. Thus, a trench 105 is formed in the patterned second pad layer 120a, the first pad layer 110a, and the substrate 100a.
계속하여, 상기 트렌치(105)를 매립하도록 상기 기판(100a) 전면상에 HDP 옥사이드와 같은 제1소자분리층 물질층(130)을 형성한다.Subsequently, a first device isolation layer material layer 130 such as HDP oxide is formed on the entire surface of the substrate 100a to fill the trench 105.
그다음, 도 6에 도시된 바와 같이, 상기 제1소자분리막 물질층(130)을 일부 제거하여 상기 트렌치(105)를 부분적으로 매립하는 제1소자분리막(130a)를 형성한다.Next, as shown in FIG. 6, a portion of the first device isolation layer material layer 130 is removed to form a first device isolation layer 130a partially filling the trench 105.
상기 제1소자분리막(130a)을 형성하는 단계는, 상기 제2패드막(120a)이 노출되도록 상기 제1소자분리막 물질층(130)을 화학기계적 연마(CMP)하여 평탄화한다. 그다음, 상기 평탄화된 제1소자분리막 물질층(130)을 HF가 포함된 식각용액으로 습식각하여 상기 트렌치(105)를 부분적으로 매립하는 제1소자분리막(130a)을 형성한다.The forming of the first device isolation layer 130a may include planarization by chemical mechanical polishing (CMP) of the first device isolation layer material layer 130 to expose the second pad layer 120a. Next, the planarized first device isolation layer material layer 130 is wet-etched with an etching solution containing HF to form a first device isolation layer 130a partially filling the trench 105.
또는, 상기 제1소자분리막 물질층(130)을 화학기계적 연마(CMP)하여 평탄화한 후, 상기 평탄화된 제1소자분리막 물질층(130)을 건식각하여 상기 트렌치(105)를 부분적으로 매립하는 제1소자분리막(130a)을 형성할 수 있다.Alternatively, the first device isolation material layer 130 may be planarized by chemical mechanical polishing (CMP), and then the planarized first device isolation material layer 130 may be dry-etched to partially fill the trench 105. The first device isolation layer 130a may be formed.
또는, 상기 제1소자분리막 물질층(130)을 화학기계적 연마(CMP)하지 아니하고 한단계의 습식각 공정, 즉 제1소자분리막 물질층(130)을 HF가 포함된 식각용액으로 습식각하여 상기 트렌치(105)를 부분적으로 매립하는 제1소자분리막(130a)을 형성한다.Alternatively, the trench may be wet-etched in one step without using chemical mechanical polishing (CMP), ie, wet etching the first device isolation material layer 130 with an etching solution containing HF. The first device isolation layer 130a partially filling the 105 is formed.
한편, 상기 제1소자분리막(130a) 형성시 증착공정을 적용할 수 있고, 또는 증착공정이 아닌 코팅 및 열처리 공정을 적용할 수 있다.Meanwhile, a deposition process may be applied when the first device isolation layer 130a is formed, or a coating and heat treatment process may be applied instead of the deposition process.
그다음, 도 7에 도시된 바와 같이, 상기 제2패드막(120a)을 H3PO4등이 포함된 식각용액을 사용한 습식각으로 제거한다.Next, as shown in FIG. 7, the second pad layer 120a is removed by wet etching using an etching solution including H 3 PO 4 .
이어서, 후속하는 보더레스 콘택홀 식각시 소자분리막에로의 침투를 차단하기 위한 차단막을 형성하기 위하여 먼저 상기 제1소자분리막(130a)을 포함한 상기 기판(100a) 전면상에 차단막 물질층(140)을 형성한다.Subsequently, the barrier layer material layer 140 is formed on the entire surface of the substrate 100a including the first device isolation layer 130a to form a barrier layer for blocking penetration into the device isolation layer during subsequent borderless contact hole etching. To form.
그런다음, 도 8에 도시된 바와 같이, 상기 차단막 물질층(140)이 형성된 기판(100a) 전면상에 제2소자분리막 물질층(150)을 형성한다. 상기 제2소자분리막 물질층(150)은 상기 제1소자분리막(130a)과는 동일하거나 동일계열의 물질을 증착하여 형성하는 것이 소자분리막의 물리적 특성이나 화학적 특성의 균일성을 유지하는데 바람직하다 할 것이다.Next, as shown in FIG. 8, the second device isolation layer material layer 150 is formed on the entire surface of the substrate 100a on which the blocking film material layer 140 is formed. The second device isolation layer material layer 150 may be formed by depositing the same or the same series of materials as the first device isolation layer 130a to maintain uniformity of physical or chemical properties of the device isolation layer. will be.
이어서, 도 9에 도시된 바와 같이, 상기 제1패드막(110a)이 노출되도록 상기 제2소자분리막 물질층(150)과 차단막 물질층(140)을 일부 제거하여 차단막(140a)과제2소자분리막(150a)을 형성한다.Subsequently, as shown in FIG. 9, the second device isolation layer material layer 150 and the blocking layer material layer 140 are partially removed to expose the first pad layer 110a, thereby blocking the barrier layer 140a and the second device isolation layer. 150a is formed.
상기 차단막(140a)을 비롯한 제2소자분리막(150a)을 형성하는 단계는, 상기 차단막 물질층(140)이 노출되도록 상기 제2소자분리막 물질층(150)을 화학기계적 연마하여 평탄화한다. 이어서, 상기 노출된 차단막 물질층(140)을 HF가 포함된 식각용액으로 습식각한다. 그 결과, 상기 차단막(140a)을 중심으로 상기 트렌치(105)의 하부를 부분적으로 매립하는 제1소자분리막(130a)과 상기 트렌치(105)의 상부를 부분적으로 매립하는 제2소자분리막(150a)으로 이루어진 소자분리막(160)을 완성된다.In the forming of the second device isolation layer 150a including the blocking layer 140a, the second device isolation layer material layer 150 is chemically polished and planarized so that the blocking layer material layer 140 is exposed. Subsequently, the exposed barrier layer material layer 140 is wet etched with an etching solution containing HF. As a result, the first device isolation layer 130a partially filling the lower portion of the trench 105 and the second device isolation layer 150a partially filling the upper portion of the trench 105 with respect to the blocking film 140a. The device isolation film 160 is completed.
또는, 상기 차단막 물질층(140)이 노출되도록 상기 제2소자분리막 물질층(150)을 화학기계적 연마하여 평탄화한 후, 상기 차단막 물질층(140)을 건식각하는 단계를 통하여 상기 제2소자분리막(150a)을 형성할 수 있다.Alternatively, the second device isolation layer may be planarized by chemical mechanical polishing of the second device isolation layer material layer 150 to expose the blocking layer material layer 140, and then dry-etched the block material layer 140. 150a can be formed.
한편, 상기 차단막(140a)은 질화막이나 산화질화막으로 형성한다.On the other hand, the blocking film 140a is formed of a nitride film or an oxynitride film.
이어서, 도 10에 도시된 바와 같이, 상기 제1패드막(110a)을 제거한 후 상기 기판(100a)의 액티브 영역상에 자기정렬 규화물층(170)과, 질화막 또는 산화질화막으로 식각정지막(180)을 순차로 형성한다.Next, as shown in FIG. 10, after the first pad layer 110a is removed, the etch stop layer 180 is formed of a self-aligned silicide layer 170 and a nitride film or an oxynitride layer on the active region of the substrate 100a. ) Are formed sequentially.
그다음, 도 11에 도시된 바와 같이, 상기 식각정지막(180)상에 PMD(폴리실리콘-금속-절연체) 물질층(190)을 형성한다. 계속하여, 1차로 상기 식각정지막(180)에 이를 때까지 상기 PMD(폴리실리콘-금속-절연체) 물질층(190)에 대한 선택적 식각을 진행한 다음, 2차로 상기 식각정지막(180)의 식각으로 상기 차단막(140a)에 의해 상기 소자분리막(160)이 개방되지 않는 보더레스(borderless) 콘택홀(200)을형성한다.Next, as shown in FIG. 11, a layer of PMD (polysilicon-metal-insulator) material 190 is formed on the etch stop layer 180. Subsequently, selective etching is performed on the PMD (polysilicon-metal-insulator) material layer 190 until the etch stop layer 180 is first reached, and then, secondly, the etch stop layer 180 is formed. Etching forms a borderless contact hole 200 in which the device isolation layer 160 is not opened by the blocking layer 140a.
그결과, 상기 보더레스 콘택홀(200)을 매립하는 플러그(미도시)가 형성되어도 상기 트렌치(105) 측벽부의 소자분리막(160)이 손실되지 않는다.As a result, even if a plug (not shown) filling the borderless contact hole 200 is formed, the device isolation layer 160 of the sidewall portion of the trench 105 is not lost.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 보더레스 콘택홀 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the method of forming the borderless contact hole of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는, 소자분리막의 평탄화 정도에 상관없이 콘택홀 건식각을 여유롭게 진행할 수 있으며, 얇은 질화막의 사용으로 트랜지스터의 특성 저하등도 억제시킬 수 있다. 또한, 웰과 소스/드레인을 단선시키는 문제가 없으며, 안정적인 보더레스 콘택홀 형성이 가능하다.In the present invention, regardless of the degree of planarization of the device isolation film, the contact hole dry etching can be easily carried out, and the use of a thin nitride film can also suppress the deterioration of transistor characteristics. In addition, there is no problem of disconnecting the well and the source / drain, and stable borderless contact holes can be formed.
Claims (9)
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| KR100905194B1 (en) * | 2006-07-03 | 2009-06-26 | 주식회사 하이닉스반도체 | Method for Forming Transistor of Semiconductor Device |
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| KR100905194B1 (en) * | 2006-07-03 | 2009-06-26 | 주식회사 하이닉스반도체 | Method for Forming Transistor of Semiconductor Device |
| US7651923B2 (en) | 2006-07-03 | 2010-01-26 | Hynix Semiconductor, Inc. | Method for forming transistor of semiconductor device |
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