KR20040000778A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display is provided to minimize delay deviation of gate pulses supplied to a liquid crystal panel from a driving circuit by differentiating the resistance vale deviation due to the length deviation of gate links or data links. CONSTITUTION: A plurality of gate links(L1,...,Ln) connect signal lines of a liquid crystal panel with pads for supplying signals necessary for the signal lines. An ESD(Electrostatic discharge) circuit line(62) is formed with gate electrodes of thin film transistors. The ESD circuit line crosses the gate links. A common voltage generator or power supply unit(63) applies a common electrode voltage or LCD(Liquid Crystal Display) input power to the ESD circuit line. Overlapped areas of the ESD circuit line with the gate links are different to compensate a wiring resistance value deviation due to length deviation of the gate links. An ESD circuit(61) is connected between the ESD circuit line and the common electrode voltage or LCD input power for protecting the liquid crystal panel from static electricity.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of compensating for a resistance value variation caused by a length deviation of a link portion.

Typically, a liquid crystal display device (hereinafter referred to as "LCD") is composed of a liquid crystal panel and a driving circuit portion for driving the liquid crystal panel. The lower substrate of the liquid crystal panel is provided with switch elements (that is, TFT arrays) for switching signals supplied to the liquid crystal cells, respectively. At this time, the gate terminal of the switch element is connected to the gate driver (not shown), and the source terminal is connected to the source driver (not shown), respectively. The drain terminal of the switch element is connected to the pixel electrode. The common voltage Vcom is applied to the common electrode of the upper substrate of the liquid crystal panel. In addition, a liquid crystal cell arranged in a matrix form between two substrates (ie, an upper substrate and a lower substrate) is provided.

On the other hand, under the control of the driving circuit unit, the gate driver sequentially applies the scanning signals to the respective gate lines. The source driver applies the image signal to the data line under the control of the driver circuit. At this time, when the image signal is applied to the TFT turned on by the scanning signal, the image signal is moved to the pixel electrode via the source terminal and the drain terminal. At this time, the alignment direction of the liquid crystal is controlled by the voltage difference between the ITO to which the common voltage Vcom is applied and the pixel electrode to which the image signal is applied. Hereinafter, a conventional liquid crystal display device will be described with reference to FIGS. 1 and 2.

Referring to FIG. 1, the liquid crystal display according to the related art is formed on the ITO film 20 to which the common voltage Vcom is applied from the common voltage generator 30, and the lower substrate 10. Ag dots 12 for transmitting a common voltage and electrostatic discharge (hereinafter referred to as "ESD") circuit wirings 14 and 16 formed between the Ag dots 12 and the Ag dots 12 are provided. As shown in FIG. 1, at least two ESD circuit wirings are formed in the liquid crystal panel. In this case, the Ag dot 12 is formed in a sphere shape to have conductivity, and is formed at points A, B, C, and D on the lower substrate 10, respectively. In addition, the ITO film 20 is disposed on the Ag dot 12 so that the common voltage is applied. Here, the ESD circuit 11 protects the liquid crystal panel from static electricity.

FIG. 2 is a cross-sectional view illustrating a cross section of the liquid crystal display device taken along the line AA ′ of FIG. 1. Referring to FIG. 2, in the conventional liquid crystal display, a gate electrode 31, a gate link 38, and a first ESD circuit wiring 14 are first formed on the lower substrate 10. That is, the gate link 38 is formed in the gate pad portion on the lower substrate 10, the gate electrode 31 is formed in the TFT region, and the first ESD circuit wiring 14 is formed in the data pad portion. The gate electrode 31, the gate link 38, and the first ESD circuit wiring 14 are deposited using a metal material such as aluminum (Al) or copper (Cu) by a deposition method such as sputtering. It is then formed by patterning.

The gate insulating layer 32 is formed on the gate electrode 31, the gate link 38, and the first ESD circuit wiring 14. The gate insulating layer 32 is formed by completely depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) to cover the gate link 38 and the gate electrode 31 by PECVD (Plasma Enhanced Chemical Vapor Deposition) method. Is formed.

The active layer 33 and the ohmic contact layer 34 are formed on the gate insulating layer 32 in the TFT region. The active layer 33 and the ohmic contact layer 34 are formed by stacking and patterning the first and second semiconductor layers on the gate insulating layer 32. That is, the active layer 33 is formed of amorphous silicon which is not doped with impurities, which is the first semiconductor layer. In addition, the ohmic contact layer 34 is formed of amorphous silicon doped with N-type or P-type impurities as the second semiconductor layer at a high concentration.

Source and drain electrodes 35 and 36, a second ESD circuit wiring 16, and a data link 42 are formed on the gate insulating layer 32. That is, the second ESD circuit wiring 16 is formed on the gate link 38 with the gate insulating layer 32 interposed therebetween, and the data link 42 has the first ESD with the gate insulating layer 32 interposed therebetween. It is formed on the circuit wiring 14.

The source and drain electrodes 35 and 36, the data link 42 and the second ESD circuit wiring 16 are formed by depositing and patterning the metal layer on the entire surface by the CVD method or the sputtering method. After patterning the source and drain electrodes 35 and 36, the ohmic contact layer 34 corresponding to the gate electrode 31 is also patterned to expose the active layer 33. The portion of the active layer 33 corresponding to the gate electrode 31 between the source and drain electrodes 35 and 36 becomes a channel. The source and drain electrodes 35 and 36, the data link 42, and the second ESD circuit wiring 16 are formed of chromium (Cr) or molybdenum (Mo).

The protective layer 37 is formed on the gate insulating layer 32. The protective layer 37 is formed by depositing an insulating material on the gate insulating layer 32 and then patterning the insulating material. The protective layer 37 is formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) or an organic insulating material such as acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane).

The drain contact hole 44 is formed on the protective layer 37. The pixel electrode 40 is formed by depositing and patterning a transparent conductive material on the protective layer 37 having the drain contact hole 44 formed thereon. The pixel electrode 40 is in electrical contact with the drain electrode 36 through the drain contact hole 44. The pixel electrode 40 may be any one of indium tin oxide, indium zinc oxide, and indium tin zinc oxide. It is formed as one.

3 is a plan view illustrating a gate pad portion or a data pad portion of a liquid crystal display device.

Referring to FIG. 3, first, the gate pad unit transfers a scanning signal applied from the driving IC to the gate lines of the liquid crystal panel through the gate links L1,..., Ln. To this end, the gate links L1, ..., Ln may have different inclinations depending on their positions in order to connect pads of a relatively narrow gap with pads of a gate line having a relatively wide gap. They will have different lengths, while having the same width and thickness.

As a result, the resistances applied to the gate links L1, ..., Ln have a slight difference depending on their length difference. In particular, the resistance difference between the central portion having the shorter length and the longer edge portion of the gate links L1, ..., Ln is large. As such, as the resistance difference according to the length of each of the gate links L1, ..., Ln occurs, a delay of a gate signal applied to each of the gate lines is generated, thereby causing a luminance difference such as a horizontal band. There is this.

The signal delay of each of these gate links L1, ..., Ln is determined by resistance and capacitance. That is, since each of the gate links L1, ..., Ln has the same overlapping area with the ESD circuit wiring 22, the gate links L1, ..., Ln and the ESD circuit wiring 22 are the same. While the capacitance CS1 is maintained constant, the line resistance value varies in the center and the edge part according to the wiring length deviation of each gate link L1, ..., Ln. Delays occur at L1, ..., Ln.

The common electrode voltage or the LCD input power source 23 is applied to the ESD circuit wiring 22 from a common voltage generator or power supply unit (not shown). In addition, an ESD circuit 21 for protecting the liquid crystal panel from static electricity is connected between the ESD circuit wiring 22 and the common electrode voltage or the LCD input power supply 23.

Due to the signal delay of the gate line, the voltage value ΔVp applied to the pixel may be different for each gate line as shown in Equation 1 below.

In Equation 1, when a signal delay occurs in the gate line, Vp (Vgh-Vgl) becomes small, so that the voltage value ΔVp applied to the pixel becomes small. In other words, the signal delay due to the resistance difference according to the length of each gate link (L1, ..., Ln) is the center of each gate link (L1, ..., Ln) as shown in FIG. It is worse at the edge edge than the center.

In addition, the common voltage value Vcom supplied to the pixel region from each gate link L1, ..., Ln is the center of each gate link L1, ..., Ln as shown in FIG. In this case, the positive voltage and the negative voltage are centered. As a result, the common voltage value Vcom at the edge of each gate link L1, ..., Ln is the center of each gate link L1, ..., Ln as shown in FIG. Higher. Therefore, the level of the common voltage value Vcom at the edge portion of each of the gate links L1, ..., Ln having a small voltage value ΔVp applied to the pixel must be raised to the position Vcom 'and the positive voltage It is centered on the negative voltage. That is, the common voltage value Vcom at the edge portion of each gate link L1, ..., Ln is set lower than the voltage to be actually matched so that the edge portion of each gate link L1, ..., Ln The luminance difference occurs between the center and the center.

On the other hand, the data pad unit transfers a data signal applied from the driver IC through the data link unit to the data lines of the liquid crystal panel. To this end, the data link unit has different inclinations and different lengths depending on its position in order to connect pads of a relatively narrow gap with pads of a data line having a relatively wide gap, while having the same width. And thickness.

Accordingly, data pulses uniformly supplied to the respective data links from the driving IC are attenuated or delayed. Therefore, the luminance difference occurs in the screen displayed on the liquid crystal panel due to the delay deviation between the edge portion and the center portion of each data link.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of compensating for a resistance value deviation caused by a length deviation of a link portion.

1 is a view for explaining a process of transmitting a common voltage in a conventional liquid crystal display device.

FIG. 2 is a cross-sectional view illustrating a cross section of the liquid crystal display device taken along the line AA ′ of FIG. 1.

3 is a plan view of the gate pad illustrated in FIG. 2;

4 is a waveform diagram illustrating a signal deviation of a gate pad unit illustrated in FIG. 2.

5 is a waveform diagram illustrating a pixel voltage supplied to a pixel electrode through a central gate link of the gate pad part illustrated in FIG. 2.

6 is a waveform diagram illustrating a pixel voltage supplied to a pixel electrode through an edge gate link of the gate pad portion illustrated in FIG. 2.

7 is a plan view illustrating a gate pad unit according to a first embodiment of the present invention.

8 is a plan view illustrating a gate pad part according to a second exemplary embodiment of the present invention.

9 is a plan view illustrating a gate pad unit according to a third exemplary embodiment of the present invention.

10 is a plan view illustrating a gate pad unit according to a fourth embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10: lower substrate 12: Ag dot

14, 16: ESD circuit wiring 20: ITO film

22, 39, 49, 62, 72, 82, 92: ESD circuit wiring 31: gate electrode

32: gate insulating layer 33: active layer

34: ohmic contact layer 35: source electrode

36 drain electrode 37 protective layer

38: gate link 42: data link

In order to achieve the above object, the liquid crystal display according to an exemplary embodiment of the present invention crosses the links with signal lines in the display area and links for connecting pads for supplying a signal for the signal line. And an electrostatic damage (ESD) circuit wiring having a different overlapping area with the links so as to compensate the wiring resistance value difference due to the length deviation of the links.

In the liquid crystal display, the signal wiring is a gate wiring.

In the liquid crystal display, the signal wiring is characterized in that the data wiring.

In the LCD, the links may have different line widths.

The liquid crystal display according to the embodiment of the present invention connects an electrostatic damage (ESD) circuit wiring to which a common voltage is supplied, connects signal wirings of a display area and pads for supplying a signal necessary for the signal wiring, and the electrostatic damage ( And a plurality of links crossing the ESD circuit lines and configured to have different overlapping areas with the electrostatic damage (ESD) circuit lines in order to compensate for the difference in the wiring resistance value due to the length deviation.

In the liquid crystal display, the signal wiring is a gate wiring.

In the liquid crystal display, the signal wiring is characterized in that the data wiring.

In the LCD, the links may have different line widths.

Other objects and features of the present invention in addition to the above objects will be apparent from the description of the embodiments with reference to the accompanying drawings.

A preferred embodiment of the present invention will be described with reference to FIGS. 7 to 10.

7 is a plan view illustrating a gate pad part of a liquid crystal display according to a first exemplary embodiment of the present invention. Referring to FIG. 7, the liquid crystal display according to the first exemplary embodiment of the present invention may include gate links for connecting signal wirings of a liquid crystal panel (not shown) and pads (not shown) for supplying a signal for signal wiring. Intersect L1, ..., Ln and gate links L1, ..., Ln and compensate for the difference in wiring resistance value due to the length deviation of each gate link L1, ..., Ln. An ESD circuit wiring 62 having a different overlapping area with the gate links L1, ..., Ln is provided.

The ESD circuit wiring 62 is formed together with the gate electrodes of the thin film transistor. The ESD circuit wirings 62 and the respective gate links L1, ..., Ln cross each other in an insulated state by a gate insulating layer (not shown). The common electrode voltage or the LCD input power 63 is applied to the ESD circuit wiring 62 from a common voltage generator or a power supply (not shown). In addition, an ESD circuit 61 for protecting the liquid crystal panel from static electricity is connected between the ESD circuit wiring 62 and the common electrode voltage or the LCD input power source 63.

Each gate link L1, ..., Ln connects gate lines of a liquid crystal panel (not shown) and pads (not shown) for supplying a necessary signal to the gate lines. Each of the gate links L1, ..., Ln is connected to driver ICs not shown through a pad. Each of the gate links L1, ..., Ln may have different inclinations depending on its position in order to connect pads of a relatively narrow gap with pads of a gate line having a relatively wide gap. Will have different lengths.

As a result, the resistance applied to each of the gate links L1,..., Ln has a slight difference depending on the length difference thereof. In particular, the resistance difference between the central portion having a shorter length and the longer edge portion of the gate links L1, ..., Ln is large. Therefore, gate pulses uniformly supplied to the respective gate links L1, ..., Ln from the driving IC are attenuated or delayed.

Therefore, in order to compensate for the line resistance value due to the length deviation of the gate links L1, ..., Ln, the gate links L1, ..., Ln and the ESD circuit wiring 62 and The overlap area of is set differently. That is, the line width of the ESD circuit wiring 62 gradually increases from both ends to the center portion. At this time, the signal delay of each gate link (L1, ..., Ln) has a relationship as shown in equation (2).

A: Vertical cross section of each gate link

L: length of each gate link

S: Cross area of each gate link and ESD circuit wiring

d: distance between each gate link and ESD circuit wiring

ρ: resistivity

The signal delay of the gate links L1 and Ln disposed at both ends of the gate links L1, ..., and Ln using Equation 2 is expressed by Equation 3 below.

The signal delay of the gate links Ln / 2 disposed at the center of each of the gate links L1, ..., Ln is expressed by Equation 4 using Equation 2.

In this way, the line width of the ESD circuit wiring 62 is increased or decreased according to Equation 2 described above to set different overlapping areas between the ESD circuit wiring 62 and the gate links L1, ..., Ln. Therefore, the resistance value deviation caused by the length deviation of each gate link L1, ..., Ln is equally compensated. That is, the resistance of each of the gate links L1, ..., Ln having different lengths is kept as it is, and the gate circuits L1, ..., Ln and the ESD circuit wiring 62 of The capacitance value at the overlapping surface is changed.

Accordingly, the capacitances of the ESD circuit wiring 62 and the gate links L1, ..., Ln are changed, so that the difference in resistance value according to the increase in the length of each gate link L1, ..., Ln is caused. To compensate for the signal delay between the gate links (L1, ..., Ln) is prevented. The signal delay of the gate pad unit and the conventional gate pad unit of the liquid crystal display according to the exemplary embodiment of the present invention are shown in Table 1 below.

Conventional structure Structure of the present invention Capacitance Edge = Center Edge <Center Resistance Edge> Center Edge> Center Signal delay Edge> Center Edge = Center

Accordingly, in the liquid crystal display according to the first exemplary embodiment of the present invention, the deviation of the signal delay with respect to each of the gate links L1,..., Ln is minimized, so that the gate links L1,... It is possible to supply uniformly without attenuation and delay of the gate pulse supplied to Ln).

On the other hand, in order to compensate for the delay deviation of the data signal due to the resistance value deviation caused by the length deviation of each data link in the data pad unit (not shown), as described above, the ESD circuit wiring has an overlapping area with the data links. It is formed differently. That is, the line width of the ESD circuit wiring overlapping the data links is formed to gradually increase from both ends to the center. Accordingly, by compensating for the resistance value deviation caused by the difference in length of each data link by the capacitance value between each data link and the ESD circuit wiring, the pixel of the data pulse applied to the pixel cell through the respective data links from the driver IC. The deviation of the voltage value ΔVp can be minimized.

8 is a plan view illustrating a gate pad part of a liquid crystal display according to a second exemplary embodiment of the present invention. Referring to FIG. 8, the liquid crystal display according to the second exemplary embodiment of the present invention overlaps the ESD circuit wiring 72 to which the common voltage is supplied from the common voltage source, and crosses the ESD circuit wiring 72 due to a length deviation. Gate links L1, ..., Ln are formed to have different overlapping areas with the ESD circuit wiring 72 to compensate for the resistance value deviation.

The ESD circuit wiring 72 is formed together with the gate electrodes of the thin film transistor. The ESD circuit wirings 72 and the respective gate links L1, ..., Ln are insulated by a gate insulating layer (not shown). The common electrode voltage or the LCD input power 73 is applied to the ESD circuit wiring 72 from a common voltage generator or power supply (not shown). In addition, an ESD circuit 71 for protecting the liquid crystal panel from static electricity is connected between the ESD circuit wiring 72 and the common electrode voltage or the LCD input power source 73.

Each gate link L1, ..., Ln connects gate lines of a liquid crystal panel (not shown) and pads (not shown) for supplying a necessary signal to the gate lines. Each of the gate links L1, ..., Ln is connected to driver ICs not shown through a pad. Each of the gate links L1, ..., Ln may have different inclinations depending on its position in order to connect pads of a relatively narrow gap with pads of a gate line having a relatively wide gap. Will have different lengths.

As a result, the resistance applied to each of the gate links L1,..., Ln has a slight difference depending on the length difference thereof. In particular, the resistance difference between the central portion having the shorter length and the longer edge portion of the gate links L1, ..., Ln is large. Therefore, gate pulses uniformly supplied to the respective gate links L1, ..., Ln from the driving IC are attenuated or delayed.

In order to compensate for the resistance value deviation due to the length deviation of each of the gate links L1, ..., Ln, the overlapped area between the ESD circuit wiring 72 and each of the gate links L1, ..., Ln. Is formed differently. That is, the line widths of the gate links L1 and Ln positioned at both ends of the gate links L1, ..., Ln are located at the center of the gate links L1, ..., Ln. It becomes thinner than the line width of (Ln / 2). That is, the line width of each of the gate links L1, ..., Ln overlapping the ESD circuit wiring 72 is gradually increased toward the center gate link Ln / 2 according to Equation 2 described above.

Accordingly, the capacitance of the ESD circuit wiring 72 and the gate links L1, ..., Ln is changed, so that the difference in resistance value according to the increase in the length of each gate link L1, ..., Ln is caused. To compensate for the signal delay of each of the gate links (L1, ..., Ln) is prevented.

Therefore, in the liquid crystal display according to the second exemplary embodiment of the present invention, the deviation of the signal delay due to the length deviation of each of the gate links L1, ..., Ln is minimized, and thus the gate links L1 from the driving IC are minimized. It is possible to supply uniformly without attenuation and delay of the gate pulse supplied to Ln).

On the other hand, in order to compensate for the delay deviation of the data signal due to the resistance value deviation caused by the length deviation of each data link (not shown), as described above, the overlapping area between the ESD circuit wiring and each data link is formed at both ends. It is formed to gradually increase toward the data link located in the center. Accordingly, by compensating the delay deviation of the data signal due to the resistance value deviation caused by the length deviation of each data link to the capacitance value with the ESD circuit wiring, the data pulse applied to the pixel cell through the respective data links from the driver IC. The deviation of the pixel voltage value ΔVp can be minimized.

9 is a plan view illustrating a gate pad part of a liquid crystal display according to a third exemplary embodiment of the present invention. Referring to FIG. 9, a liquid crystal display according to a third embodiment of the present invention connects signal wirings of a liquid crystal panel (not shown) and pads (not shown) for supplying a signal necessary for signal wiring, and a resistance due to a length deviation. In order to compensate the value, the gate links L1, ..., Ln having different line widths and the gate links L1, ..., Ln intersect with each other, and the respective gate links L1, ... And an ESD circuit wiring 82 having a different overlapping area with the gate links L1, ..., Ln to compensate for the difference in wiring resistance value due to the length deviation of Ln.

The ESD circuit wiring 82 is formed together with the gate electrodes of the thin film transistor. The ESD circuit wirings 82 and the respective gate links L1, ..., Ln are insulated by a gate insulating layer (not shown). The common electrode voltage or the LCD input power source 83 is applied to the ESD circuit wiring 82 from a common voltage generation unit or a power supply unit (not shown). In addition, an ESD circuit 81 for protecting the liquid crystal panel from static electricity is connected between the ESD circuit wiring 82 and the common electrode voltage or the LCD input power source 83.

Each gate link L1, ..., Ln connects signal wirings of a liquid crystal panel (not shown) and pads (not shown) for supplying a signal for signal wiring. Each gate link L1, ..., Ln is connected to driver ICs not shown. The gate links L1, ..., Ln may have different inclinations and different inclinations depending on their positions in order to connect pads of a relatively narrow gap with pads of a gate line having a relatively wide gap. Will have a different length.

As a result, the resistances applied to the gate links L1, ..., Ln have a slight difference depending on their length difference. In particular, the resistance difference between the central portion having the shorter length and the longer edge portion of the gate links L1, ..., Ln is large. Therefore, gate pulses uniformly supplied to the respective gate links L1, ..., Ln from the driving IC are attenuated or delayed.

In order to compensate for the resistance value deviation caused by the length deviation of each of the gate links L1, ..., Ln, the central gate link Ln / of the shortest length among the gate links L1, ..., Ln In 2), the line width gradually decreases toward the gate links L1 and Ln at the longest ends. That is, the line width W2 of the central gate link Ln / 2 having the shortest length among the gate links L1, ..., Ln is formed thickest, and the gate links L1 at both ends of the longest length are the thickest. The line width W1 of Ln is the thinnest. In addition, the overlapping area between the ESD circuit wiring 82 and the gate links L1, ..., Ln is formed differently. That is, the line width of the ESD circuit wiring 82 gradually increases from both ends to the center. That is, in the ESD circuit wiring 82, the line width of the center portion is formed to be the thickest, and the line width of both ends is formed to be the thinnest. At this time, the line width of each gate link (L1, ..., Ln) and the line width of the ESD circuit wiring 82 is set according to the above equation (2).

As such, according to Equation 2, the line widths of the gate links L1, ..., Ln are decreased along with the length, and the line widths of the ESD circuit wirings 82 are increased or decreased to prevent the ESD circuit wirings 82 from increasing. ) And the capacitance are varied by forming different overlapping areas between the gate links L1, ..., Ln, so that the resistance value deviation due to the length deviation of each gate link L1, ..., Ln is equal. To compensate. That is, by setting the line widths of the gate links L1, ..., Ln having different lengths differently, the resistance values are changed equally, and the gate links L1, ..., Ln and ESD The capacitance value between the circuit wirings 82 is changed.

Accordingly, the resistance values of the gate links L1, ..., Ln are changed in the same manner, and the capacitances of the ESD circuit wiring 82 and the gate links L1, ..., Ln are changed. The signal delay between the gate links L1, ..., Ln is prevented by compensating for the difference in the resistance value according to the increase in the length of each of the gate links L1, ..., Ln. Accordingly, in the liquid crystal display according to the third exemplary embodiment of the present invention, the deviation of the signal delay with respect to each of the gate links L1,..., Ln is minimized, so that the gate links L1,... It is possible to supply uniformly without attenuation and delay of the gate pulse supplied to Ln).

On the other hand, in order to compensate for the delay deviation of the data signal due to the resistance value deviation caused by the length deviation of each data link (not shown), as described above, the line width of each data link is increased or decreased with the length. In addition, the line width of the ESD circuit wiring overlapping each data ring is formed to gradually increase from both ends to the center. Accordingly, by compensating for the resistance value of each data link and the capacitance value of the ESD circuit wiring, the deviation of the pixel voltage value ΔVp of the data pulse applied to the pixel cell from the driving IC through each data link can be minimized. .

10 illustrates a gate pad portion of a liquid crystal display according to a fourth exemplary embodiment of the present invention. Referring to FIG. 10, the liquid crystal display according to the fourth exemplary embodiment of the present invention overlaps an ESD circuit line 92 supplied with a common voltage from a common voltage source, and crosses the ESD circuit line 92 due to a length deviation. In order to compensate for the resistance value deviation, gate links L1,..., Ln having different line widths and different overlapping areas with the ESD circuit wirings 92 are provided.

The ESD circuit wiring 92 is formed together with the gate electrodes of the thin film transistor. The ESD circuit wirings 92 and the respective gate links L1, ..., Ln are insulated by a gate insulating layer (not shown). The common electrode voltage or the LCD input power supply 93 is applied to the ESD circuit wiring 92 from a common voltage generator or a power supply not shown. In addition, an ESD circuit 91 for protecting the liquid crystal panel from static electricity is connected between the ESD circuit wiring 92 and the common electrode voltage or the LCD input power supply 93.

Each gate link L1, ..., Ln connects gate lines of a liquid crystal panel (not shown) and pads (not shown) for supplying a necessary signal to the gate lines. Each of the gate links L1, ..., Ln is connected to driver ICs not shown through a pad. Each of the gate links L1, ..., Ln may have different inclinations depending on its position in order to connect pads of a relatively narrow gap with pads of a gate line having a relatively wide gap. Will have different lengths.

As a result, the resistances applied to the gate links L1, ..., Ln have a slight difference depending on their length difference. In particular, the resistance difference between the central portion having the shorter length and the longer edge portion of the gate links L1, ..., Ln is large. Therefore, the gate pulses uniformly supplied from the driving ICs to the respective gate links L1, ..., Ln are attenuated or delayed.

In order to compensate for the resistance value deviation caused by the length deviation of each of the gate links L1, ..., Ln, the central gate link Ln / of the shortest length among the gate links L1, ..., Ln In 2), the line width gradually decreases toward the gate links L1 and Ln at the longest ends. That is, the line width W2 of the central gate link Ln / 2 having the shortest length among the gate links L1, ..., Ln is formed thickest, and the gate links L1 at both ends of the longest length are the thickest. The line width W1 of Ln is the thinnest. In addition, the overlapping area between the ESD circuit wiring 92 and the gate links L1, ..., Ln gradually increases from both ends to the center to be different. That is, the line widths of the respective gate links L1, ..., Ln overlapped with the ESD circuit wiring 92 are gradually increased toward the center gate link Ln / 2 according to Equation 2 described above. do.

Accordingly, the capacitances of the ESD circuit wiring 92 and the gate links L1, ..., Ln are changed, so that the difference in resistance value according to the increase in the length of each gate link L1, ..., Ln is caused. To compensate for the signal delay of each of the gate links (L1, ..., Ln) is prevented.

Accordingly, the resistance values of the gate links L1, ..., Ln are changed in the same manner, and the capacitances of the ESD circuit wiring 92 and the gate links L1, ..., Ln are changed. By compensating for the resistance value deviation due to the length deviation of each of the gate links L1, ..., Ln, the signal delay between the gate links L1, ..., Ln is prevented. Accordingly, in the liquid crystal display according to the fourth exemplary embodiment of the present invention, the deviation of the signal delay with respect to each of the gate links L1,..., Ln is minimized, so that the gate links L1,... It is possible to supply uniformly without attenuation and delay of the gate pulse supplied to Ln).

On the other hand, in order to compensate for the delay deviation of the data signal due to the resistance value deviation caused by the length deviation of each data link (not shown), as described above, the line width of each data link is increased or decreased with the length. In addition, the line width of each data ring facing the ESD circuit wiring is formed to gradually increase from both ends to the center. Accordingly, by compensating for the resistance value of each data link and the capacitance value of the ESD circuit wiring, the deviation of the pixel voltage value ΔVp of the data pulse applied to the pixel cell from the driving IC through each data link can be minimized. .

As described above, the liquid crystal display according to the exemplary embodiment of the present invention has a resistance due to the length deviation of each gate link or each data link by overlapping the area of the ESD circuit wiring with each gate link or each data link. By forming differently to compensate for the value deviation, the delay deviation of the gate pulse or the data signal supplied from the driving circuit to the liquid crystal panel can be minimized and uniformly supplied. Therefore, no screen defect such as a horizontal band occurs on the screen.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

Links for connecting signal wirings of a display area and pads for supplying a signal for the signal wiring; And an electrostatic damage (ESD) circuit wiring intersecting the links and configured to have different overlapping areas with the links so as to compensate for a wiring resistance value difference due to a length deviation of the links. The method of claim 1, And the signal line is a gate line. The method of claim 1, And the signal wiring is data wiring. The method of claim 1, And said links have different line widths. Electrostatic damage (ESD) circuit wiring supplied with a common voltage, The electrostatic damage (ESD) to connect signal wirings of a display area and pads for supplying a signal necessary for the signal wiring, intersect the electrostatic damage (ESD) circuit lines, and compensate for a difference in wiring resistance due to a length deviation; And a plurality of links having different overlapping areas with the circuit wiring. The method of claim 5, And the signal line is a gate line. The method of claim 5, And the signal wiring is data wiring. The method of claim 5, And said links have different line widths.