KR200395281Y1 - Single powered differential amplifier - Google Patents

Abstract

The input terminal composed of the input terminal IN and the base of the positive transistor Q1 of the differential amplifier stage and the resistor R1 for bias supply is connected to the other terminal of R4 and the collector of the positive transistor Q1 connected to the power supply VCC, and the collector of the negative transistor Q2 is connected. Connected to the VCC, the emitter of the positive transistor Q1 and the emitter of the negative transistor Q2 are connected, the differential amplifier stage connected to the resistor R5, the connection point of the collector of the positive transistor Q1 and R4, and the base of Q3. Connected to emitter and resistor R6, to the collector of Q3 and to the anode of D1, to the cathode of D1 and to the anode of D2, to the driver amplifier of D2 and to the resistor R7, to the collector of transistor Q3, Complementary transistor Q4 connected to the base at the connection point of the anode of diode D1 and the connection at the connection point of the resistor R7 and the cathode of diode D2 Connected to the emitter and resistor R8 of the other complementary transistors Q5 and Q4, connected to the emitter and resistor R9 of Q5, to the output terminal connected to the other terminals and output terminals OUT of R8 and R9, and to the resistor Rf1 at the output terminal OUT. Connected to the other terminal of Rf1 and Rf2, to the negative feedback terminal to which the base of negative transistor Q2 is connected, to the virtual ground point A to which RCC is connected to another terminal of R2 and to G3, and to GND Connected to the virtual ground terminal connected to capacitor C1 at both ends of R3, the OUT terminal of the output terminal, and the-terminal of the op amp IC1 and the resistor R4, and the base of Q1 at the output terminal of the capacitor C2 and IC1 connected to the terminal of IC1 and the output of IC1. The output 0 point control stage is connected to the other terminal of the resistor R1 for supplying the low bias.

Description

Single power differential amplifier {SINGLE POWERED DIFFERENTIAL AMPLIFIER}

The present invention relates to a differential amplifier that minimizes signal distortion caused by a virtual ground point and minimizes low frequency signal distortion of an input signal in a single amplifier using a single power supply. In a small or portable amplifier, a battery is used as a power source. In many cases, the power supply of the amplification circuit is composed of a single power supply method, and in order to apply a differential amplifier circuit, the power supply voltage is divided and a virtual ground is used. The virtual ground can operate unstable, and the resulting amplified output signal can be transformed. FIG. 2 is an amplifier composed of a conventional differential amplifier circuit. The input terminal IN2 and the base of the positive transistor Q21 of the differential amplifier stage An input terminal consisting of R1, a bias reference terminal consisting of C1 connected in parallel at both ends of R23, divided by R22 and R23 at half voltage of the power supply voltage, and a collector and connection point of R24 and the positive transistor Q21 connected to the power supply VCC2. The driver amplifier of the Q23 base connected to the base of Q23 connected to R26 connected to the power supply VCC2 and the complementary transistor Q24 connected to the anode of the bias diode D21 and the collector of Q23 connected to the anode and the collector and diode of the transistor Q23. Complementary transistor Q24 connected to the base at the junction of the anode of D21 and the cathode of the diode D22 and the resistor R27 and connected to the base An output terminal connected to the emitter and the resistor R28 of the other complementary transistors Q25 and Q24 to be connected and connected to the emitter and the resistor R29 of the Q25, and to the other terminal and the output terminal OUT2 of the R28 and R29, and to the resistor Rf21 at the output terminal OUT2. This is an example of a differential amplifier circuit of the prior art, which is connected to the other terminal of Rf21 and to Rf22, to the base of negative transistor Q2, and to the negative feedback terminal connected to capacitor C22 to ground GND2. When the resistance value of R22 and R23 is the same by R22 and R23 of bias reference stage, point A is 1/2 voltage of power supply voltage and DC potential of output OUT2 is 1/2 of power supply voltage. When this operation is explained in the absence of an input signal, the voltage divided by R22 and R23 at the input terminal is applied to the base of the positive transistor Q21 via R21 and the negative feedback terminal is applied. Therefore, the DC voltage of the output terminal OUT2 is supplied to the base of the negative transistor Q22 by Rf21, and the output terminal OUT2 is controlled so that the base voltage of Q21 and the base voltage of Q22 are the same at the differential amplifier stages of Q21 and Q22. When there is no input signal, C22 of the negative feedback circuit is in the same state as open, and voltage division operation by Rf22 is not performed. Therefore, the base voltage of Q22 is equal to the voltage of OUT2, and 1 / of the power supply voltage supplied to the base of Q21. Equal to 2 voltage. Referring to the operation when the input signal of the AC component is supplied to the input terminal of Fig. 2, the impedance of C21 and C22 is negligibly small when the capacitor C21 of the bias reference stage and the capacitor C22 of the feedback stage are used at a large capacity. In this case, when the input signal is supplied to the input terminal, the first amplified signal generated by the positive transistor is generated across the resistor R24 connected to the collector of Q21. The first amplified signal is input to the base of the drive transistor Q23, amplified, and a second amplified signal appears at the collector of Q23. The first amplified signal is buffered by the complementary transistors Q24 and Q25 and output to the output terminal OUT2. The output signal is divided by Rf21 and Rf22 of the feedback stage and input as a negative feedback signal to the base of the negative transistor Q22. (Description 2) The voltage amplification degree A2 of this amplifier is A2 = 1 + Rf21 / Rf22- --------------------------- Equation 1 above means DC operation, and the average DC potential of output terminal OUT2 is always A This is a direct-current control operation (controlled as output zero point control operation) that controls the same point as the bias reference voltage of the point. (Description 3) The above explanation 2 describes the negative feedback resistance Rf21 of the negative feedback circuit when an AC signal is input to the amplifier. This is an AC control operation that amplifies the input signal at the ratio of and Rf22 and outputs it to the output terminal. (Description 4) The above explanation is the operation in the full DC state and does not affect the signal with high frequency. In addition, explanation 4 is an operation when the signal frequency is high and does not affect the DC state. However, descriptions 3 and 4 can operate simultaneously when the capacitors C21 and C22 are not large enough or in low frequencies where the signal frequency is as low as several tens of Hz. The problem of this amplifier is explained as follows: First, the combined resistance of R22 and R23 at the input stage and the time constant of the capacitor C21 are Tc21, and the combined resistance of Rf21 and Rf22 at the feedback stage and the time constant of the capacitor C22 are Tc22. In this case, when the time constant of Tc21 and the time constant of Tc22 are not the same, the output signal amplified by changing at different periods due to the difference of two time constants in a differential amplifier consisting of a positive transistor and a negative transistor in a specific frequency band of the input signal (Description 5) Second, the low band signal included in the input signal is amplified by the amplification ratio according to explanation 4, but at the same time, the low frequency signal is reduced by controlling the output signal from changing in the differential amplifier stage by the operation of explanation 3. Can be. In this case, the low-frequency signal is small or inaudible in the output signal. (Description 6) Third, the output zero point control operation of the above explanation 3 and the amplification operation of the description 4 are performed in the same differential amplifier stage, so that the amplification is performed on the signal to be amplified. (Description 7)

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In the existing single-supply differential amplifier, the output signal is transformed by the time constant difference between the positive and negative transistor circuits according to the input frequency and the low frequency output signal is reduced by the output zero point control operation. Improve the prototype to faithfully amplify.

1 is an example of an amplifier configured with a differential amplifier circuit of the present invention. An input terminal composed of a base of a positive transistor Q1 of an input terminal IN and a differential amplifier stage and a resistor R1 for bias supply, and another terminal of R4 connected to a power supply VCC. A differential amplifier terminal connected to the collector of the positive transistor Q1, the collector of the negative transistor Q2 connected to the VCC, the emitter of the positive transistor Q1 and the emitter of the negative transistor Q2 connected, and connected to the resistor R5, and the positive transistor. It is connected to the connection point between the collector of Q1 and R4 and the base of Q3, and connected to the emitter of R3 and resistor R6, the collector of Q3 and the anode of D1 are connected, the cathode of D1 and the anode of D2 are connected, and the cable of D2 The driver amplifier stage connected to the sword and resistor R7, and the complementary transistor Q4 connected to the base at the connection point with the collector of transistor Q3 and the anode of diode D1; Connected to the emitter and resistor R8 of the other complementary transistors Q5 and Q4 connected to the base at the junction of the diode D2 and the resistor R7, connected to the emitter and resistor R9 of Q5, and the other terminals and output terminals OUT of R8 and R9. The output terminal connected to the output terminal OUT is connected to the resistor Rf1 and is connected to the other terminal of Rf1 and Rf2, and the negative feedback terminal to which the base of the negative transistor Q2 is connected, and the VCC and R2 are connected, and the other terminal of R2 and R3 are connected. The other terminal of the connected virtual ground points A and R3 and GND are connected, and the virtual ground terminal connected to the capacitor C1 at both ends of R3, the OUT terminal of the output terminal and the-terminal of the op amp IC1 and the resistor R4 are connected. The capacitor C2 connected to the output is composed of an output zero point control stage connected to the other terminal of the resistor R1 for supplying a bias from the output terminal of the IC1 to the base of Q1. The virtual ground terminal connects the power supply voltage VCC to the resistors R2 and R3.By dividing the circuit and connecting C1 between the virtual ground point A and GND to supply the virtual ground point A with a bias voltage of the differential amplifier stage directly, and AC stably to provide a stable grounding function like GND. The positive bias circuit that supplies the bias to Q1 is made by OPAMP IC1, and also has an output zero point control function. In addition, the negative bias circuit for supplying a bias to the negative transistor Q2 is formed by a negative feedback terminal composed of Rf1 and Rf2. The operation of the output zero point control terminal functioning as the positive bias circuit will be described. The + terminal is connected to the virtual ground point A to supply a bias to the positive transistor Q1 at the reference voltage of the op amp IC1. The negative terminal of the operational amplifier IC1 is connected to the OUT terminal of the output terminal as R4, and is connected to the output terminal of the operational amplifier IC1 and the capacitor C2 to operate as a low pass filter. This low pass filter blocks the feedback of the signal by setting the time constants of R4 and C2 so that the lowest frequency of the amplifier is cut off. That is, the signal component of the OUT terminal is cut off and only the DC component of the OUT terminal is detected and input to the-terminal of IC1. At this time, the op amp IC1 compares the voltage of the + terminal of IC1 with the voltage of the-terminal of IC1 so that the OUT terminal of the output terminal is the same as the voltage of the virtual ground point A, and from the output of IC1 to the base of the positive transistor Q1 via the resistor R1. The bias voltage is supplied to maintain a stable state. Referring to the operation of the negative feedback terminal functioning as the negative bias circuit, the DC voltage of the OUT terminal of the amplifier output terminal is controlled by the output 0 point control terminal and always the virtual ground point A. The base voltage of the negative transistor Q2 becomes the same voltage as that of the virtual ground point A. That is, the DC component is removed between the OUT terminal of the output terminal and the virtual ground point A. In this state, the signal output to the OUT terminal of the output terminal is divided by the negative feedback circuits of the resistors Rf1 and Rf2 and input to the base of the negative transistor Q2. At this time, the signal fed back by the negative feedback circuit is fed only the amplified signal component from which the DC component has been removed. The voltage amplification degree A of this amplifier is A = 1 + Rf1 / Rf2 Becomes A first feature of the present invention is characterized in that the bias supply point of the positive transistor Q1 of the differential amplifier stage and the bias supply point of the negative transistor Q2 are supplied at the same point. That is, the positive bias circuit and the negative bias circuit are supplied from the same virtual ground point A. Here, even if the capacitance of the coupling capacitor C1 connected between the virtual ground point A and the GND is used as a large one, it has some impedance at low frequencies, so that the virtual ground point is unstable. For this reason, the impedance of the capacitor C1 changes with respect to the low frequency of the input signal, thereby causing a voltage change due to the change of the signal voltage at the virtual ground point A. The change of the virtual ground point A acts in the same way on the positive bias circuit of the positive transistor Q1 and the negative bias circuit of the negative transistor Q2, so that the change of the virtual ground point A does not appear as a voltage change in the output. For example, in the composite signal of R2 and R3 and the frequency signal near the time constant of C1, the virtual ground point A changes with the period due to the time constant, and this change is the same for the base of the positive and negative transistors of the differential amplifier stage. They cancel each other out so that they do not appear in the output signal. That is, the effect of the stable ground point appears. That is, there is an improvement effect on the problem of the above description 5. The second feature of the present invention is the direct current control such that the output terminal OUT is equal to the virtual ground point A by an output zero point control circuit composed of IC1, R4, C1, and R1. , Rf1, Rf2, the negative feedback end is only a negative feedback operation for the amplified signal so that the signal amplification in the low band as described above 6 or 7 is not reduced or modified. That is, there is an improvement effect on the problems of the above descriptions 6 and 7.

When the positive bias circuit and the negative bias circuit are supplied from the same virtual ground point, even if there is a change in the virtual ground point, the differential amplifier circuit cancels each other and does not appear at the output. The negative feedback operation of the signal amplification and the output zero point control operation are separated, thereby minimizing or reducing the low frequency output signal by the output zero point control operation.

1 illustrates a bias method circuit of the present invention.

2: Example bias method circuit of the prior art.

Claims (1)

VCC and R2 are connected, and the other terminal of R2 and R3 is connected to the virtual ground A and the other terminal of R3 and GND are connected, and the capacitor C1 is connected to both ends of R3. The bias circuit for supplying the bias to the positive transistor Q1 of the differential amplifier stage is supplied by the op amp IC1 and also has the output zero point control function, and the output zero point control stage with the reference voltage input of IC1 coupled to the virtual ground point A. The bias circuit for supplying a bias to the negative transistor Q2 of the differential amplifier stage is supplied by the resistors Rf1 and Rf2 and consists of a negative feedback stage in which the other terminal of Rf2 is coupled with the virtual ground point A. The bias of the positive transistor Q1 and the negative transistor Q2 of the differential amplifier stage is supplied at the same location of the virtual ground point A, and the output zero point control operation of the output stage OUT is separated from the negative feedback stage to independently perform the output zero point control stage. Single-supply differential amplifiers.