KR200390769Y1 - Boot ROM selection apparatus - Google Patents

Abstract

The present invention relates to a board equipped with a main controller (microprocessor), and more particularly, to a boot ROM selector for allowing a main controller to boot by selecting a boot ROM during a power-on reset period on a board having a plurality of boot ROMs. .

In the above-described boot ROM selection apparatus of the present invention, a board including at least one boot ROM including an initial boot ROM for initial booting of a main controller and a memory controller for outputting an access signal to the initial boot ROM and the boot ROM, A boot ROM selecting unit which is driven by a power-on reset signal according to power supply and determines a mounting state of the initial boot ROM through a ROM bus and then outputs a boot ROM selection signal according to the mounting state; The initial boot ROM and the boot ROM are respectively configured to receive a boot ROM selection signal SEL from an output terminal of the boot ROM selection unit, and to output a boot ROM driving signal according to the boot ROM selection signal after receiving the memory access signals CS0 and CS1 of the memory controller. A bootrom drive unit connected to the bootrom; And a bootrom driver selecting unit configured to drive only one bootrom of the at least one bootrom driver.

Description

Boot ROM selection apparatus

The present invention relates to a board equipped with a main controller (microprocessor), and more particularly, to a boot ROM selector for allowing a main controller to boot by selecting a boot ROM during a power-on reset period on a board having a plurality of boot ROMs. .

1 is a schematic block diagram of a board having a main controller booted by a boot ROM in the prior art.

As shown in FIG. 1, a board having a main controller booted by a conventional boot ROM includes a main processor (Micro Processor) 10 performing booting, boot information for booting the main controller and driving the main controller, A memory controller (20) which outputs a boot ROM access signal (CS0: Chip Selection 0) or a device ROM access signal (CS1: Chip Selection 1) so as to read other driving information from the memory and controls input / output of data in the memory. And a boot ROM control unit 30 which receives a boot ROM access signal CS0 input from the memory controller 20 and selects a boot ROM for booting the main controller 10 to read boot data, and the boot ROM. A boot ROM selection signal generator 40 for outputting a boot ROM selection signal SEL for selecting a boot ROM from the controller 30, and a plurality of boot ROMs stored in the boot information and connected to the boot ROM controller 30. It is composed of a boot ROM (a first boot ROM 50 and a second boot ROM 60).

In the above configuration, the first boot 50 and the second boot 60 may be flash ROMs. In this case, the first boot 50 generally stores the initial booting information for booting. Type ROM, and the second boot ROM 60 may be a ROM (Surface Monunted Device) type ROM that stores application and boot information (boot information + application data, capacity of 1 Mbyte or more). have. Here, in the case of the SMD-type second boot 60, a special device such as using a Joint Test Acton Group (JTAG) method or a data port accessible to the second boot 60 is used to store data. Boot data and application data may be stored. In order to record data in the SMD-type second boot ROM (60) for booting without additional equipment, the first boot ROM (50) composed of DIP-type flash ROM is mounted to read and boot the basic program. Subsequently, the data necessary for the second bootrom 60 made of the SMD-type flashrom is recorded and then used.

In the above configuration, the main controller 10, the memory controller 20, the main controller 10, and the boot ROM controller 30 are connected by a system bus 80, and the memory controller 20 and the boot ROM controller 30 is connected by a control bus. The boot ROM control unit 30 and the boot ROM selection signal generator 40 are connected by a control bus for transmitting the boot ROM selection signal (SEL) 41. The first boot ROM 50 and the second boot ROM 60 are connected to the boot ROM controller 30 by a control bus and a ROM bus 70.

The memory controller 20 simultaneously outputs the boot ROM access signal CS0 and the device ROM access signal CS1 during a power-on reset period, which is a stabilization period of power, wherein the boot ROM access signal CS0 is the main controller 10. ) Is a signal that reads data from the boot ROM for booting, and the device ROM access signal CS1 is a ROM that stores boot information of another device storing data for driving other devices after booting. Speak the signal to approach. Therefore, only CS0 is involved in booting the main controller during the initial booting process.

As shown in FIG. 2, the boot ROM control unit 30 receives the boot ROM access signal CS0 and the device ROM access signal CS1 from the memory controller 20, respectively. 35 is provided, and the first mux 34 and the second mux 35 output the first boot driving signal FCS0 at the output terminal by the input of the boot ROM select signal SEL. In addition, the second mux 35 outputs the second sub-rom drive signal FCS1 at the output terminal. The first mux 34 and the second mux 35 are configured to receive the boot ROM selection signal SEL input from the input side of the inverter 36 through a control line connected by the inverter 36 in the middle thereof. It receives the boot ROM selection signal. As a result, only one first and second mux is operated by the boot ROM selection signal SEL to ensure that one boot ROM driving signal is output.

A booting process of the main control unit 10 having the above-described configuration and the main control unit 10 in the board including the plurality of boot ROMs 50 and 60 will be described below.

In general, when power is initially applied in the above-described configuration, the main control unit 10 undergoes a power on reset period for stabilizing the power, and then boots before the hardware reset is released. Read the hardware configuration information needed to configure the hardware.

As described above, when a plurality of boot ROMs, such as the first boot ROM 50 and the second boot ROM 60, are provided, the main processor 10 may perform the boot ROM selection signal generator 40 during initial booting. ) Outputs a boot ROM selection signal SEL that allows the user to read boot information of the boot ROM preset. When the boot ROM selection signal SEL is output from the boot ROM selection signal generator 40, the boot ROM control unit 30 selectively drives the first mux 34 or the second mux 35 as shown in FIG. The bootrom driving signal including the bootrom access signal is output from either the first mux 34 or the second mux 35 so that the data of the first boot 50 or the second boot 60 is read by Rombus. The main control unit 10 performs booting. That is, when the first mux 34 and the second mux 35 are operated while the SEL signal is high, when the high signal is input to the boot ROM controller 30, the first mux 34 is input. ) Is operated, and the second mux 35 is inputted with a low SEL signal by the inverter to become inoperative. On the contrary, when the low SEL signal is input to the boot ROM control unit 30, the first mux 34 is not operated and the second mux 35 is operated to generate the boot ROM driving signal FSC0 to the second boot ROM ( 60). That is, the boot ROM drive signals FCS0 and FCS1 cannot be generated at the same time, which is guaranteed by the inverter 36 as described above.

However, in the prior art as described above, the boot ROM selection signal SEL output from the boot ROM selection signal generation unit 40 for selecting the first boot ROM 50 and the second boot ROM 60 is a dip switch. Alternatively, there was a problem that a user must manually set the scheme by another separate switching device. In this case, if the user initially sets to boot to the second boot having the boot and application functions, if the boot data of the second boot 60 is lost, the boot cannot be performed. In this case, the user reboots. Set to boot to the first boot (50) having a function only to boot to the first boot (50), then write data to the second boot (60) (fusing) and then switch the option or dip switch, etc. There is a problem that must be manipulated to perform a booting method by the second boot (60) by operating.

That is, in the prior art, it is determined whether the first boot rom 50 of the DIP type and the second boot rom 60 of the SMD type are mounted together to selectively perform a different boot method according to the mounted boot rom. There is a problem that can not be provided.

Accordingly, an object of the present invention is to solve the above-described problems of the prior art, and in a board having a first boot of DIP type having only a booting function and a second boot of SMD type having a booting and application function, After the input, the main processor (Micro Processor) determines whether the first boot is installed during the power-on reset period, and automatically selects the first boot when the first boot is mounted to perform the booting procedure. It is an object of the present invention to provide a boot ROM selecting apparatus for performing a booting procedure by selecting a second boot ROM when the first boot ROM is not installed.

A boot ROM selecting apparatus of the present invention for achieving the above object, the board having at least one boot ROM including an initial boot for initial booting of the main control portion and a memory controller for outputting an access signal to the initial boot and the boot ROM. A boot ROM selection unit driven by a power-on reset signal according to power supply of the board to determine a mounting state of the initial boot ROM through a ROM bus, and outputting a boot ROM selection signal according to the mounting state; The initial boot ROM and the boot ROM are respectively configured to receive a boot ROM selection signal SEL from an output terminal of the boot ROM selection unit, and to output a boot ROM driving signal according to the boot ROM selection signal after receiving the memory access signals CS0 and CS1 of the memory controller. A bootrom drive unit connected to the bootrom; And a bootrom driver selecting unit configured to control a bootrom selection signal to drive only one bootrom of the at least one bootrom driver.

The boot ROM selecting unit may include a selection signal generation unit which is driven during the power-on reset period and selectively outputs the initial boot ROM or boot ROM driving signal according to the match information output from the ROM data comparing unit; A ROM address generation unit for outputting ROM address information on the ROM data of the initial boot ROM; A ROM lead enable signal generator for outputting a ROM lead enable signal for reading ROM information of the ROM address generator; After receiving the ROM data as the initial boot ROM identification information read from the initial boot ROM according to the ROM lead enable signal output by the ROM lead enable signal generator, the ROM data is compared with preset comparison data (comparative data). And a ROM data comparator for outputting a match signal indicating whether there is a match to the selection signal generator.

The boot ROM selecting unit may be configured to output a boot ROM driving signal during the power-on reset period.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

In the accompanying drawings for a detailed description of the present invention, the initial boot ROM is shown as the first boot (50), the other boot ROM is shown as the second boot (60), the boot ROM selection device is shown as the boot ROM control unit 100, The bootrom drive unit is illustrated by the first mux 34 and the second mux 35, and the bootrom drive unit selection unit is illustrated by the inverter 36, and the names of the other components are the same.

In addition, in the description of the accompanying drawings for explaining the present invention in detail, the configuration having the same function used the same reference numerals and names as in the prior art.

3 is a block diagram of a board including a boot ROM selection apparatus according to an embodiment of the present invention, FIG. 4 is a block diagram showing an internal configuration of a boot ROM control unit among the boot ROM selection apparatuses, and FIG. 5 is a boot ROM selection unit. It is a block block diagram which shows schematic internal structure of 110. As shown in FIG.

As shown in FIG. 3, a board according to an embodiment of the present invention includes a main processor (Micro Processor) 10 performing booting, boot information and other driving information for booting the main controller and driving the main controller. A memory controller 20 which outputs a boot ROM access signal (CS0: Chip Selection 0) or a device ROM access signal (CS1: Chip Selection 1) so as to read from the memory and controls input / output of data in the memory; After receiving the boot ROM access signal CS0 input from the memory controller 20, the mounting state of the first boot ROM for booting the main controller 10 is determined, and when the boot command is performed, the driving signal is output to the first boot ROM 50. If the first boot ROM 50 is not installed, the boot ROM controller 100 outputs a driving signal of the second boot ROM 60 and at least one boot ROM connected to the boot ROM controller 100 to store boot information. It is composed.

In the present invention, for example, the boot ROM is equipped with a first boot ROM 50 of a DIP type storing initial booting information and a second boot ROM 60 of an SMD type storing booting information and application information.

In the board according to the present invention, the main controller 10, the memory controller 20, the main controller 10 and the boot ROM controller 100 are connected by a system bus, the memory controller 20 and the boot ROM controller ( 100 is connected by a control bus. In addition, in the boot ROM control unit 100, the first boot ROM 50 and the second boot ROM 60 are connected to each other by a control bus and a ROM bus 70.

4 is a block diagram illustrating an internal configuration of the boot ROM controller 100 of FIG. 3.

As shown in FIG. 4, the boot ROM control unit 100 that is driven by the power-on reset signal and outputs the boot ROM drive signals FCS0 and FSC1 is driven by the power-on reset signal and is driven by the ROM bus 70. The boot ROM selection unit 110 outputs a boot ROM selection signal SEL according to the boot ROM mounting state after determining the mounting state, and receives the boot ROM selection signal SEL from the output terminal of the boot ROM selection unit 110. The first mux 34 and the second mux 35 connected to receive the memory access signals CS0 and CS1 of the memory controller 20 are configured in parallel, and the first mux 34 and the second mux ( 35 is separated by an inverter 36 and configured to input the boot ROM selection signal SEL to an input terminal of the inverter 36.

When the first mux 34 and the second mux 35 are set to be driven by the high boot ROM select signal SEL, the boot ROM selector 110 may operate on the first boot ROM through the Rhombus 70. When the first boot 50 is mounted, the boot state selection signal SEL of the high is outputted to drive the first mux 34 to read the mounting state of the first boot 50. And outputs a first boot driving signal FCS0 for driving. When the first boot ROM 50 is not mounted, the boot ROM selection unit 110 outputs a low boot ROM selection signal SEL. In this case, the boot ROM inverted to high by the inverter 36. The second mux 35 is driven by the selection signal SEL to output the second butrom driving signal FCS1.

5 is a schematic internal configuration diagram of the boot ROM selector 110 operating as described above. The boot ROM selector 110 performing the operation as described above includes a selection signal generator 120 and a ROM therein. An address generator 130, a ROM lead enable signal generator 140, and a ROM data comparator 150 are provided.

The selection signal generator 120 is driven during the power-on reset period and the driving signal FCS0 of the first boot 50 or the second boot 60 is generated according to the match information output from the ROM data comparator 150. , FCS1).

The ROM address generation unit 130 is also driven during the power-on reset period to initially output ROM address information corresponding to the first boot ROM 50.

The ROM lead enable signal generator 140 is also driven during a power-on reset period to output a ROM read enable signal for reading the information of the designated ROM address from the ROM address generator 130. do.

The ROM data comparison unit 150 may include ROM data as first boot ROM identification information read from the first boot ROM 50 according to the ROM lead enable signal 140 output by the ROM lead enable signal generator 140. After receiving), it compares with preset comparison data (comparison data) and outputs a match signal indicating whether there is a match.

The match signal output from the ROM data comparator 150 may be represented as a binary number such as low and high, but is not limited thereto. That is, when the case where the ROM data read from the first boot ROM 50 and the comparison data (comparative data) are the same is made high, the opposite case is set low. Here, high is a case where the first boot throttle 50 is mounted, and low is a state where the first boot throttle 50 is not mounted.

According to the match signal output from the ROM data comparison unit 150, the selection signal generator 120 outputs a boot ROM selection signal SEL, and the first mux 34 and the second mux of FIG. If 35 is set to be driven by the high SEL signal, a high boot ROM selection signal is output when the first boot ROM 50 is mounted, and vice versa, a low boot ROM selection signal ( SEL) will be output.

In the detailed description of the present invention, the process booted by the first boot 50 is called a debug mode, and the process booted by the second boot 60 is called a normal mode.

FIG. 6 is a time chart showing the operation of each component in a debug mode booting procedure, and FIG. 7 is a time chart showing the operation of each component in a booting mode of a normal mode. 8 is a flowchart illustrating a booting process of the main controller 10 in the board having the configuration of FIGS. 3 to 5 described above.

As shown in FIG. 8, the main controller 10 of the above-described board performs a booting process as power is applied. In this process, as shown in FIGS. 6 and 7, when the initial power is applied, a power on reset proceeds to a low state and a hardware reset process is performed. The memory controller 20 initially outputs a high boot ROM access signal CS0 and a low device ROM access signal CS1 (S10).

Next, after a predetermined time elapses after the power is applied, a process of determining whether the first boot 50 is installed (hereinafter referred to as a “ROM match cycle”) is performed.

That is, in the ROM matching cycle, the ROM address generation unit 130 of FIG. 5 first outputs a ROM address specifying the address of the identification information of the first boot ROM, and the ROM lead enable signal generation unit 140 The ROM lead enable signal 130 outputs a ROM lead enable signal to read ROM data corresponding to a ROM address output from the ROM address generator 130. In FIG. 6 and FIG. 7, the ROM address is expressed in hexadecimal, and the ROM lead enable signal is represented by a low signal (S20).

Next, when ROM data is input to the ROM data comparison unit 150 through a ROM bus according to a ROM read enable signal, the ROM data comparison unit 150 is stored in the storage unit in comparison data. The comparison data is read, compared with the ROM data, and a match signal indicating whether there is a match is output to the selection signal generator 120. In the description of the present invention, when the comparison data and the ROM data coincide with the first boot ROM, a high signal is output; when the comparison data does not match, the low signal is output when the first boot ROM is not installed. Assume (S30).

When a high match signal is input in step S30, the selection signal generator 120 outputs a boot ROM selection signal SEL for selecting the first boot ROM, and the first mux 34. Assuming that the second mux 35 is operated by the high boot ROM select signal SEL, the boot ROM select signal SEL becomes a high signal. When the high boot ROM selection signal SEL is output, as shown in FIG. 4, the first mux 34 is driven to output the first boot ROM driving signal FCS0, and the first boot ROM 50 is output via the Rhombus bus. The booting information is read by the main control unit 10 and booting is performed. This process is the booting process of the debug mode (S40).

On the contrary, when a low match signal is input in step S30, the selection signal generator 120 outputs a low boot ROM selection signal SEL. In this case, the high signal inverted by the inverter 36 is inverted by the inverter 36. The second mux 34 is driven by the high boot ROM selection signal to output the second boot driving signal FCS1, and the boot information is read from the second boot 60 via the ROM bus to the main controller 10. The boot is performed. This process is the booting process of the normal mode (Normal Mode) (S50).

The present invention as described above allows a boot ROM for booting the main controller on a board having a plurality of boot ROMs, thereby preventing boot errors due to manual operation.

In addition, the above-described present invention is provided in a boot ROM of a SMD type having boot information and application information and a boot ROM of a DIP type having only initial boot information, and the boot data of the SMD boot ROM is corrupted when it is set to boot by a SMD type boot ROM. In this case, the initial booting is automatically performed by the DIP type boot ROM having the initial booting information. Thus, the board mounting device can be easily managed.

In addition, the present invention described above can simplify the structure of the board by eliminating the need for an external device such as a dip switch for boot ROM selection.

1 is a schematic block diagram of a board for booting a main processor of the prior art;

FIG. 2 is a schematic block diagram of a boot ROM controller of FIG. 1;

3 is a schematic block diagram of a board for booting a main processor by bootrom selection according to an embodiment of the present invention;

4 is a block diagram illustrating a schematic internal configuration of the boot ROM controller of FIG. 3;

FIG. 5 is a block diagram illustrating a schematic internal configuration of a boot ROM selector of the boot ROM controller of FIG. 4;

6 is a time chart of a debug mode booting process.

7 is a time chart of a normal mode booting process.

8 is a flowchart illustrating a process of booting by bootrom selection according to the present invention.

* Description of Major Symbols in Drawings *

SEL (selection): Boot ROM selection signal

FCS0: First Boot ROM Drive Signal

FCS1: Second Boot ROM Drive Signal

CS0 (Chip Selection 0): Boot ROM access signal

CS1 (Chip Selection 1): Device ROM Access Signal

10: Microprocessor

20: Memory Controller

30, 100: Boot ROM controller

40, 120: boot ROM selection signal generator

50: first bootrom 60: second bootrom

70: ROM bus 80: System bus

110: ROM Selection Part

130: ROM address generation unit

140: ROM read enable signal generation unit

150: ROM data comparison

Claims (5)

A board having at least one boot ROM including an initial boot ROM for initial booting of a main controller, and a memory controller configured to output an access signal to the initial boot ROM and the boot ROM, A boot ROM selecting unit which is driven by a power-on reset signal according to power of the board to determine a mounting state of the initial boot ROM through a ROM bus and then outputs a boot ROM selection signal according to the mounting state; The initial boot ROM and the boot ROM are respectively configured to receive a boot ROM selection signal SEL from an output terminal of the boot ROM selector, and to output a boot ROM drive signal according to the boot ROM selection signal after receiving the memory access signals CS0 and CS1 of the memory controller. A bootrom drive unit connected to the bootrom; And a bootrom driver selecting unit configured to control the bootrom driving signal to drive only one bootrom of the at least one bootrom driver. The method of claim 1, wherein the boot ROM selection unit, A selection signal generation unit which is driven during the power-on reset period and selectively outputs a driving signal for the initial boot ROM or the boot ROM according to the match information output from the ROM data comparison unit; A ROM address generation unit for outputting ROM address information on the ROM data of the initial boot ROM; A ROM lead enable signal generator for outputting a ROM lead enable signal for reading ROM information of the ROM address generator; Match indicating whether the ROM data read from the initial boot ROM is received according to the ROM lead enable signal output by the ROM lead enable signal generator, and whether the ROM data is matched with preset comparison data. Boot ROM selection apparatus comprising a ROM data comparator for outputting a signal to the selection signal generator. 3. The boot ROM selector of claim 1, wherein the boot ROM selector comprises: And a bootrom driving signal is output during the power-on reset period. The method of claim 1, wherein the boot ROM drive unit, And a boot ROM selection apparatus driven by the boot ROM selection signal. The method of claim 1, wherein the boot ROM driver selection unit, A bootrom selecting device, inverting the bootrom selecting signal