KR20030095464A - Method for forming contact of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a contact of a semiconductor device is provided to be capable of reducing contact resistivity. CONSTITUTION: After forming a conductive pattern at the upper portion of a semiconductor substrate(100), the first insulating layer(140) is formed at the upper portion of the resultant structure. The second insulating layer(145) is formed at the upper portion of the first insulating layer in isotropic etching condition. At this time, the etching speed of the second insulating layer is still slower than that of the first insulating layer. Then, the first opening portion is formed by sequentially etching the second and first insulating layer for exposing the upper surface of the conductive pattern. The second opening portion is formed by carrying out an isotropic etching process at the second and first insulating layer exposed through the first opening portion. Then, the second opening portion is filled with a conductive layer(160).

Description

TECHNICAL FOR FORMING CONTACT OF SEMICONDUCTOR DEVICE

The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to a contact forming method having a low contact resistance.

In a rapidly developing information society, a semiconductor device having a high data transfer rate is required to process a large amount of information faster. In order to increase the data transfer speed of a semiconductor device, cells must be integrated at a high density on a single chip.

Accordingly, work to reduce design rules for integrating cells in semiconductor devices has been actively performed. By reducing the design rule as described above, the wirings of the semiconductor device have a three-dimensional shape and are formed in a multilayer.

As described above, a contact is required to electrically connect the interlayer wirings by forming the wiring in a multilayer. The contact is formed through the interlayer interconnections by etching the insulating layer in a narrow region to electrically connect the conductive patterns present in the different layers.

Generally, after dividing a substrate into an active region and a field region, a gate electrode made of polysilicon selectively doped on the active region and the field region is formed. After the nitride film is coated on the entire surface of the substrate on which the gate electrode is formed, the nitride film is anisotropically etched to form a spacer on the sidewall of the gate electrode. Source / drain regions are formed on both substrates of the spacer of the gate electrode by a conventional ion implantation method to form transistors. After the first insulating film is formed over the substrate including the transistor, the first insulating film is etched to expose the active region through a normal photolithography process. The etched region is filled with a conductive material to form a contact plug through a planarization process. A second insulating film is formed on the entire surface of the substrate including the contact plug. The second insulating layer is etched to form a contact hole to allow the contact plug to enter. The contact hole is filled with a conductive material to form a contact.

As described above, the size of the contact formed as described above continues to decrease as the design rules of semiconductor devices that are recently developed are developed to 0.1 micrometer or less. Therefore, the contact area between the contact and the lower contact plug is reduced due to the margin between the contact and the gate electrode. This causes the bottom critical dimension of the contact to be small, resulting in increased resistance. Due to the increased resistance, the signal current or signal voltage delivered to the contact is weakened, resulting in unclear signal detection and malfunction.

Accordingly, an object of the present invention is to provide a method for forming a contact of a semiconductor device having a low contact resistance.

1A to 1I are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to a first embodiment of the present invention.

2A to 2G are cross-sectional views illustrating a method for forming a contact for a semiconductor device according to a second exemplary embodiment of the present invention.

In order to achieve the above object, the present invention, forming a first insulating film on a semiconductor substrate on which a conductive pattern is formed, the etching rate is five times slower than the first insulating film on the first insulating film isotropic etching conditions Forming a first insulating layer by sequentially etching a predetermined region of the second insulating layer and the first insulating layer so that an upper surface of the conductive pattern is exposed; forming a first opening; and a second exposed side surface of the first opening Isotropically etching the insulating film and the first insulating film to extend a contact area with the conductive pattern to form a second opening, and filling the second opening with a conductive material.

Here, the thickness of the second insulating film is formed to be at least 10 times thicker than the thickness of the first insulating film on the conductive pattern. Therefore, even when the first insulating film is etched to increase the contact area with the conductive pattern until the etching rate of the first insulating film with respect to the second insulating film is five times, the semiconductor device may be formed due to the etching consumption of the second insulating film. It does not cause stability deterioration. However, when the etching speed of the first insulating film relative to the second insulating film is 5 times or less, the etching consumption of the second insulating film is relatively high, which may cause interference with surrounding conductive patterns.

When forming the contact hole in the above manner, by forming the bottom portion wider than the upper portion of the contact hole, it is possible to reduce the contact resistance by forming a wide contact area with the lower conductive material.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

1A to 1I are cross-sectional views of a method for forming a contact of a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1A, after dividing a substrate 100 into an active region and a field region in a conventional manner, an oxide film is formed on the entire surface of the substrate 100. Doped polysilicon is coated on the oxide film, and a nitride film is applied. A predetermined region of the nitride layer is etched and the doped polysilicon and the oxide layer are sequentially etched to form a gate electrode 110 that is selectively capped in the active region and the field region. After the nitride film is coated on the entire surface of the substrate 100 on which the gate electrode 110 is formed, the nitride film is anisotropically etched to form spacers 110a on sidewalls of the gate electrode 100. A transistor is formed by forming a source / drain region 120 on the substrate 100 located on both sides of the spacer 110a of the gate electrode 110 by a conventional ion implantation method. The first insulating layer 130 is formed on the entire surface of the substrate 100 including the transistor. A predetermined region of the first insulating layer 130 is etched by using an etch ratio of the nitride layer and the spacer 110a surrounding the first insulating layer 130 and the gate electrode 110 to form a gate electrode formed in the active region. The first opening 135 is formed to expose the upper surface of the substrate 100.

Referring to FIG. 1B, a conductive polysilicon film 138 is formed on the entire surface of the substrate 100 including the side and bottom surfaces of the first opening 135 to fill the first opening 135.

Referring to FIG. 1C, the upper surface of the first insulating layer 130 is exposed by the method of conventional chemical mechanical polishing (CMP, hereinafter referred to as "CMP"). Planarize to complete the self aligned contact (SAC, hereinafter referred to as "SAC") pad 138a.

Referring to FIG. 1D, a second insulating layer 140 is formed on the entire surface of the substrate 100 including the SAC pad 138a. Preferably, the thickness of the second insulating layer 140 is 500 Å or less.

Referring to FIG. 1E, a third insulating layer 145 is formed on the second insulating layer 140 to a thickness ten times the thickness of the second insulating layer 140. The third insulating layer 145 has a relatively low etching rate when wet etching than the second insulating layer 140. Preferably, the etching rate of the second insulating layer 140 is five times faster than the etching rate of the third insulating layer 145.

Referring to FIG. 1F, the third insulating layer 145 and the second insulating layer 140 in a predetermined area are sequentially dry etched so that the SAC pad 138a on the substrate 100 is exposed to form a second opening ( 150).

Referring to FIG. 1G, a wet etch is performed on the entire surface of the substrate 100 including the second opening 150. The third insulating layer 145 exposed to the side surface of the second opening 150 with respect to the wet etching has an etching speed that is five times slower than the second insulating layer 140. Accordingly, the second insulating layer 140 exposed on the sidewalls and the bottom surface of the lower surface of the second opening 150 may be etched more than five times faster. Due to the difference in etching speed as described above, a third opening 150a is formed in which the bottom surface of the second opening 150 is extended. Preferably, the width of the bottom of the third opening 150a is extended by the width of the SAC pad 138a.

Referring to FIG. 1H, the third opening 150a is filled by forming a conductive layer 160 on the entire surface of the substrate 100 including the third opening 150a having the bottom surface extended thereto.

Referring to FIG. 1I, a contact plug 170 is formed by planarizing the conductive layer 160 to expose the top surface of the third insulating layer 145 by a conventional CMP process.

Example 2

2A to 2H are cross-sectional views illustrating a method for forming a contact for a semiconductor device according to a second exemplary embodiment of the present invention.

Referring to FIG. 2A, after dividing a substrate 200 into an active region and a field region by a conventional method, an oxide film and a doped polysilicon are coated on the entire surface of the substrate 200. A predetermined region of the doped polysilicon is etched and the oxide layer is sequentially etched to form the gate electrode 210. After the nitride film is coated on the entire surface of the substrate 200 on which the gate electrode 210 is formed, the nitride film is anisotropically etched to form spacers 210a on sidewalls of the gate electrode 200. Source / drain regions 220 are formed on the substrate 200 located on both sides of the spacer 210a of the gate electrode 210 by a conventional ion implantation method to form a transistor.

Referring to FIG. 2B, a first insulating layer 240 is formed on the entire surface of the substrate 200 including the transistor. Preferably, the first thickness 240a of the first insulating layer 240 disposed on the top surface of the gate electrode 210 of the transistor is 500 Å or less.

Referring to FIG. 2C, a second insulating layer 245 is formed on the first insulating layer 240. In this case, the second thickness 245a of the second insulating layer 240 formed on the gate electrode 210 is formed to be 10 times the first thickness 240a. The second insulating layer 245 has a relatively low etching rate when wet etching the first insulating layer 240. Preferably, the etching rate of the first insulating layer 240 is five times faster than the etching rate of the second insulating layer 245.

Referring to FIG. 2D, the second insulating film 245 and the first insulating film 240 in a predetermined region are sequentially dry etched so that the gate electrode 210 on the substrate 200 is exposed, and thus the first opening ( 250).

Referring to FIG. 2E, a wet etch is performed on the entire surface of the substrate 200 including the first opening 250. The second insulating layer 245 exposed to the side surface of the first opening 250 with respect to the wet etching has an etching speed that is five times slower than that of the first insulating layer 240. Accordingly, the first insulating layer 240 exposed to the sidewalls and the bottom surface of the lower surface of the first opening 250 is etched relatively five times faster. Due to the difference in etching speed as described above, the second opening 250a is formed in which the bottom surface of the first opening 250 is extended. Preferably, the width of the bottom surface of the second opening 250a is extended by the width of the gate electrode 210.

Referring to FIG. 2F, the conductive layer 260 is formed on the entire surface of the substrate 200 including the second opening 250a having the bottom surface extended to fill the second opening 250a.

Referring to FIG. 2G, the conductive film 260 is planarized to expose the top surface of the second insulating film 245 by a conventional CMP process to form a contact plug 270.

As described above, according to the present invention, an insulating layer is formed on the conductive layer by forming a first film having a high etching rate and a second film having a relatively low etching rate under the same wet etching conditions. Accordingly, when the insulating layer is etched to form the opening, when the wet etching is performed, the first insulating film may be selectively etched to expand the bottom surface of the opening. Accordingly, the openings formed between the layers in the semiconductor device having a very narrow critical dimension may be narrowly formed, and the contact resistance may be reduced by extending the area in contact with the conductive layer. Therefore, due to the reduction in the critical dimension, it is possible to prevent the operation speed of the semiconductor device from lowering, thereby improving the performance of the semiconductor device.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (4)

Iii) forming a first insulating film on the semiconductor substrate on which the conductive pattern is formed; Ii) forming a second insulating film on the first insulating film at an etching speed of at least five times lower than that of the first insulating film under isotropic etching conditions; Iii) sequentially etching the second insulating film and the first insulating film so as to expose an upper surface of the conductive pattern to form a first opening; I) isotropically etching the second insulating film and the first insulating film exposed to the side surface of the first opening to form a second opening having an extended contact area with the conductive pattern; And Iii) filling the second opening with a conductive material. The method of claim 1, wherein a thickness of the second insulating layer is at least 10 times thicker than a thickness of the first insulating layer on the conductive pattern. The method of claim 1, wherein the first opening is formed by dry etching in step iii). The method of claim 1, wherein the step (i) expands the bottom surface area of the second opening to be equal to the area of the upper surface of the conductive pattern.