KR20030094568A - Circuit and method of compensating voltage drop of internal power voltage for cell array in semiconductor memory device - Google Patents

Abstract

PURPOSE: A circuit for compensating the voltage drop of an inner power voltage for a cell array in a semiconductor memory device and a method for compensating the voltage drop are provided to satisfy the requirement for the low power voltage and the requirement for the high power voltage. CONSTITUTION: A circuit for compensating the voltage drop of an inner power voltage for a cell array in a semiconductor memory device includes a pull-up driver and a pulse width control circuit(420). The pull-up driver pulling up the inner power voltage level for the cell array to an external power voltage level in response to the pulse width. And, the pulse width control circuit(420) controls the pulse width of the pulse signal in response to the level detection signal. The level detection signal is capable of shifting the logic state in response to the sense control signal to control the sensing of the data stored at the memory cell and the external power voltage.

Description

Circuit and method of compensating voltage drop of internal power voltage for cell array in semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to an internal power supply voltage drop compensation circuit for a cell array and an internal power supply voltage drop compensation method for a cell array.

In the current semiconductor memory device, in order to compensate for the instantaneous drop of the internal power supply voltage for the cell array that occurs early in the sensing of the memory cell data, the internal power supply for the cell array for a predetermined time is applied to the internal power supply voltage for the cell array that is dropped during the initial sensing. There is a circuit for applying an external power supply voltage higher than the power supply voltage.

1 is a diagram showing a first example of a conventional internal power supply voltage VINTA drop compensation circuit 10 for a cell array. Referring to FIG. 1, an internal power supply voltage drop compensation circuit 10 for a cell array includes a delay circuit PWM1, a logic gate 11, and a driver MPO.

The delay circuit PWD1 is configured by a chain of a plurality of inverters to delay the sensing control signal PS used in the conventional memory device for a predetermined time. The logic gate 11 may include the sensing control signal PS and the delay circuit ( The output signal of PWD1) is received and negatively multiplied to output an autopulse signal VINTAEB having a predetermined pulse width to the gate of the driver MPO.

The driver MPO is connected between the external power supply voltage VEXT and the internal power supply voltage VINTA for the cell array, and converts the internal power supply voltage VINTA for the cell array to the external power supply voltage VEXT in response to the auto pulse signal VINTAEB. Pull-up). The external power supply voltage VEXT is higher than the internal power supply voltage VINTA for the cell array.

2 is a diagram showing a second example of the conventional internal power supply voltage VINTA drop compensation circuit 20 for a cell array. Referring to FIG. 2, the internal power supply voltage drop compensation circuit 20 for the cell array includes a delay circuit PWM2, a logic gate 21, and a driver MPO.

The difference from the internal power supply voltage drop compensation circuit 10 for the cell array shown in FIG. 1 is that the delay circuit PWM2 has a larger delay amount than the delay circuit PWM1 of FIG. 1.

Referring to the operation of the circuits of FIGS. 1 and 2, the point is to determine how much the pulse width of the auto pulse signal VINTAEB is made. If the width of the pulse is too small, the dip of the internal power supply voltage VINTA for the cell array may not be sufficiently compensated, and thus the cell restore time may not be obtained as desired.

However, if the pulse width is too large, the internal power supply voltage VINTA for the cell array is overdriving and the current consumption increases, so how to optimize the operation of the circuit of the auto pulse signal VINTAEB It is a way to guarantee.

Recent demands on low power supply voltage operation for memory devices have increased the need for significantly increasing the autopulse width of this circuit. Such a request for low power supply voltage results in a reduction in the absolute value of the internal power supply voltage (VINTA) for the cell array, so that a memory device operating at the low power supply voltage is relatively low when sensing the same number of cells. Not only will there be a dip in the internal power supply voltage (VINTA) for the large cell array, but also the gap between the external power supply voltage and the internal power supply voltage (VINTA) for the cell array is reduced, resulting in a dip in the internal power supply voltage (VINTA) for the cell array. To compensate for this, it is necessary to apply an auto pulse signal VINTAEB having a larger pulse width to the driving transistor MPO.

FIG. 3 is data showing an internal power supply voltage VINTA for a cell array when the external power supply voltage VEXT is changed from a low voltage to a high voltage with respect to the circuit of FIG. 1. Referring to the data of FIG. 3, the internal power supply voltage VINTA is overdriven by the pulse width of the excessive auto pulse signal VINTAEB from 2.5 V when the external power supply voltage VEXT is 2.5 V. You can see that (VINTA) is overshooting. As such, the excessively large internal power supply voltage VINTA for the cell array causes a problem of increasing power consumption by increasing current consumption during active / restore.

In general, memory devices having low power supply voltage operation characteristics are also required to operate in a general power supply voltage region and a high power supply voltage region. In the memory device operating in such a wide area, the circuit proposed above should be large enough to compensate for the dip of the internal power supply voltage (VINTA) for the cell array at low power supply voltage, and internally for the cell array at high power voltage. It is necessary to have a pulse width small enough to prevent overshooting of the power supply voltage VINTA.

That is, the conventional internal power supply voltage drop compensation circuits 10 and 20 shown in FIGS. 1 and 2 may not generate auto pulse signals VINTAEB corresponding to changes in the external power supply voltage VEXT. .

Accordingly, a technical object of the present invention is to provide a circuit for compensating for a drop in the internal power supply voltage for a cell array that satisfies the demand at the low power supply voltage and the demand at the high power supply voltage that conflict with the width of the auto pulse. have.

Another technical problem to be solved by the present invention is to provide a method for compensating for the drop in the internal power supply voltage for a cell array, which satisfies the demand at the low power supply voltage and the demand at the high power supply voltage which conflict with the width of the auto pulse. There is.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a view showing a first example of a conventional internal power supply voltage drop compensation circuit for a cell array.

2 is a diagram illustrating a second example of a conventional internal power supply voltage drop compensation circuit for a cell array.

3 is data showing an internal power supply voltage for a cell array when the external power supply voltage is changed from a low voltage to a high voltage with respect to the circuit of FIG. 1.

4 is a block diagram of an internal power supply voltage drop compensation circuit for a cell array according to the present invention.

5 is an embodiment of a level detection signal generation circuit.

6 is an embodiment showing a pulse width control circuit according to the present invention.

7 is data showing a change in pulse width according to a change in an external power supply voltage level according to the present invention.

8 is a graph showing simulation results when the pulse width is reduced at a high power voltage.

9 is a graph illustrating a change in cell restore time according to a pulse width at a low power supply voltage.

10 is a flowchart illustrating a method for compensating an internal power supply voltage for a cell array according to the present invention.

One aspect of the present invention for achieving the above technical problem relates to a circuit for compensating for a drop in the internal power supply voltage for the cell array. A circuit for compensating for a drop in an internal power supply voltage for a cell array according to the present invention includes a driver for pulling up the internal power supply voltage level for a cell array to an external power supply voltage level in response to a pulse signal; And a pulse width control circuit for controlling the pulse width of the pulse signal in response to a sensing control signal for controlling sensing of data stored in a memory cell and a level detection signal for transitioning a logic state in response to a change in the external power supply voltage. It is characterized by including.

Preferably, the external power supply voltage level is higher than the internal power supply voltage level for the cell array.

Also preferably, when the level of the external power supply voltage is lower than the level of a predetermined reference voltage, the logic state transitions to a first logic state, and the logic when the level of the external power supply voltage is higher than the level of the reference voltage. The state is characterized by a transition to a second logical state.

Further, preferably, the pulse width of the pulse signal when the level of the external power supply voltage is lower than the reference voltage is wider than the pulse width of the pulse signal when the external power supply voltage is higher than the reference voltage.

Another aspect of the present invention for achieving the above technical problem relates to a circuit for compensating for an internal power supply voltage drop for a cell array. A circuit for compensating for an internal power supply voltage drop for a cell array according to the present invention includes: a sourcing circuit for charging the cell array voltage to an external power supply voltage in response to a pulse signal having a predetermined pulse width; And a pulse width control circuit for controlling the pulse width in response to a level detection signal, wherein the level detection signal transitions a logic state in response to a change in the external power supply voltage.

Preferably, when the external power supply voltage is lower than a predetermined reference voltage, the logic state transitions to a first logic state, and when the external power supply voltage is higher than a predetermined reference voltage, the logic state is a second logic state. It is characterized by the transition to.

Also preferably, in response to the level detection signal, the pulse width control circuit increases the delay when the level detection signal is in the first logic state and decreases the delay when the level detection signal is in the second logic state. It features.

Another aspect of the present invention for solving the above technical problem relates to a circuit for compensating for a drop in an internal power supply voltage for a cell array. A circuit for compensating for an internal power supply voltage drop for a cell array according to the present invention includes a driver for pulling up the level of the internal power supply voltage for a cell array to an external power supply voltage level in response to an autopulse signal having a predetermined pulse width; A voltage detection circuit for comparing a reference voltage with a first voltage obtained by dividing the external power supply voltage in response to a high power voltage test enable signal and outputting a comparison result; And a pulse width control circuit for controlling the pulse width of the auto pulse signal in response to the sensing control signal for controlling the sensing of data stored in the memory cell and the comparison result.

Preferably, the pulse width control circuit outputs a signal having a narrow pulse width when the level of the first voltage is higher than the level of the reference voltage and is wide when the level of the first voltage is lower than the level of the reference voltage. A signal having a pulse width is output.

Another aspect of the present invention for solving the above technical problem relates to a method for compensating for a drop in the internal power supply voltage for a cell array. A method for compensating for a drop in an internal power supply voltage for a cell array according to the present invention includes the steps of: receiving a predetermined external power supply voltage, comparing a first reference voltage divided by the external power supply voltage with a predetermined reference voltage, and outputting a comparison result; Generating a pulse signal in response to the comparison result and a sensing control signal for controlling sensing of data stored in a memory cell; And pulling-up an internal power supply voltage for a cell array to the external power supply voltage in response to the pulse signal, wherein generating the pulse signal comprises: the level of the first voltage being greater than the level of the reference voltage; When the signal is high, a signal having a narrow pulse width is output. When the level of the first voltage is lower than the level of the reference voltage, a signal having a wide pulse width is output.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

4 is a block diagram of an internal power supply voltage drop compensation circuit for a cell array according to an exemplary embodiment of the present invention. Referring to FIG. 4, an internal power supply voltage drop compensation circuit 400 for a cell array includes a level detection circuit 410, a pulse width control circuit 420, and a driver 430.

The level detection circuit 410 detects a predetermined level of the external power supply voltage VEXT in response to the high power voltage test enable signal HITE and the reference voltage VREF and outputs the detection result PEVCDET to the pulse width control circuit. Output at 420.

The pulse width control circuit 420 generates an auto pulse signal VINTAEB having a predetermined pulse width in response to the predetermined sensing control signal PS and the level detection signal PEVCDET, and outputs the generated auto pulse signal VINTAEB to the driver 430. The driver 430 pulls up the cell array internal power supply voltage VINTA to the external power supply voltage VEXT in response to the auto pulse signal VINTAEB.

5 is an embodiment of a circuit for generating the level detection circuit 410 of FIG. Referring to FIG. 5, the level detection circuit 410 includes a differential amplifier 510, a voltage distribution circuit 520, a pull-down circuit 56, and two inverters 57 and 58. The differential amplifier 510 includes a plurality of transistors 50 to 55.

The PMOS transistor 50 is connected between the power supply voltage VDD and the node N56 and the high power voltage test enable signal HITE is input to the gate of the PMOS transistor 50. The PMOS transistor 51 is connected between the node N56 and the node N57 and the gate of the PMOS transistor 51 is connected to the node N57. The PMOS transistor 54 is connected between the node N56 and the node N58 and the gate of the PMOS transistor 54 is connected to the node N57.

The PMOS transistor 52 is connected between the node N57 and the node N59, the reference voltage VREF is input to the gate of the PMOS transistor 52, and the PMOS transistor 55 is the node N58 and the node N59. ), And the division voltage Vdiv is input to the gate of the PMOS transistor 55. The NMOS transistor 53 is connected between the node N59 and the ground power supply VSS, and the reference voltage VREF is input to the gate of the NMOS transistor 53.

The voltage distribution circuit 520 has two diode-coupled PMOS transistors and two diode-coupled NMOS transistors, the PMOS transistors being connected between the external power supply voltage VEXT and the node N60, the NMOS transistors being the node. It is connected between N60 and the ground power supply VSS. The voltage Vdiv of the node N60 is determined by adjusting the ratio of the channel length to width of each PMOS transistor and the ratio of the channel length to width of each NMOS transistor. That is, the voltage Vdiv of the node N60 is a voltage obtained by dividing the external power supply voltage VEXT to a predetermined level.

The pull-down circuit 56 is an NMOS transistor, which is connected between the node N58 and the ground power supply VSS, and the high power voltage test enable signal HITE is input to the gate of the NMOS transistor 56. The inverter 57 is connected between the node N58 and the input terminal of the inverter 58, and the inverter 58 inverts the output signal of the inverter 57 to output the level detection signal PEVCDET.

The operation of the level detection circuit 410 will be described with reference to FIG. 5. When the external power supply voltage VEXT is a high power supply voltage, the high power supply test enable signal HITE is activated (e.g., logic "high"). Therefore, since the transistor 56 is turned on in response to the activated high power voltage test enable signal HITE, the level of the node N58 is pulled down to the ground power supply VSS level. Thus, the level detection signal PEVCDET is deactivated (e.g., logic "low").

However, when the external power supply voltage VEXT is a low power supply voltage, the high power voltage test enable signal HITE is inactivated. Accordingly, since the transistor 56 is turned off in response to the deactivated high power voltage test enable signal HITE, the voltage of the node N58 is compared with the level of the reference voltage VREF and the level of the distribution voltage Vdiv. It is determined by the result.

Assuming that the reference voltage VREF is equal to the internal power supply voltage VINTA for the cell array, the differential amplifier 510 outputs a result of amplifying a difference between the reference voltage VREF and the distribution voltage Vdiv. When the reference voltage VREF is higher than the division voltage Vdiv, the voltage of the node N58 becomes "high", so the level detection signal PEVCDET is activated. However, when the reference voltage VREF is lower than the division voltage Vdiv, the voltage of the node N58 is " low ", so that the level detection signal PEVCDET is inactivated.

6 is an embodiment showing a pulse width control circuit 420 according to the present invention. 6 illustrates the pulse width control circuit 420 and the driver 430 together. Referring to FIG. 6, the pulse width control circuit 420 includes a delay circuit PWM3 and a logic gate 66.

The logic gate 66 generates an autopulse signal VINTAEB by performing a negative AND on the NAND of the delayed sensing control signal PS that delays the sensing control signal PS and the sensing control signal PS by a predetermined time.

The delay circuit PWM3 outputs the delayed sensing control signal DPS in response to the sensing control signal PS. The delay circuit PWM3 is composed of an inverter 60, an inverter 61, an inverter 62, a transmission gate T1, an inverter 63, and an inverter 64 that input the sensing control signal PS. A path PA1 and a second path PA2 constituted by an inverter 60, a transmission gate T2, an inverter 63, and an inverter 64 as inputs of the sensing control signal PS. The first path PA1 has a larger delay amount than the second path PA2.

The transmission gates T0 and T1 respectively use the level detection signal PEVCDET and the level detection signal PEVCDET inverted by the inverter 65 as inputs of the gate, and the transmission gate T0 is the level detection signal PEVCDET. Is connected to be turned on when is a logic 'high', and the transmission gate T1 is connected to be turned on when the level detection signal PEVCDET is a logic 'low'.

An operation of an embodiment of the present invention will be described with reference to FIGS. 4 to 6. When the external power supply voltage VEXT is a low power supply voltage, the level detection signal PEVCDET becomes logic 'high' in response to the level detection circuit 410, and the transmission gate T0 in response to the level detection signal PEVCDET. Is turned on and the transmission gate T1 is turned off.

In this case, the delay circuit PWM3 delays the sensing control signal PS through the first path PA1. Therefore, the delayed sensing control signal DPS having a large amount of delay is output in response to the sensing control signal PS.

The logic gate 66 outputs an auto pulse signal VINTAEB having a large pulse width in response to the sensing control signal PS and the delayed sensing control signal DPS. In response to the auto pulse signal VINTAEB having a large pulse width, the driver 430 properly compensates for the internal power supply voltage VINTA for the cell array.

On the other hand, when the external power supply voltage VEXT is a high power supply voltage, the level detection signal PEVCDET becomes logic 'low' in response to the level detection circuit 410, and the transmission gate (eg, in response to the level detection signal PEVCDET). T1 is turned on and the transmission gate T0 is turned off. In this case, the delay circuit PWM3 becomes the second path PA2. Therefore, in response to the sensing control signal PS, a delayed sensing control signal DPS having a small delay amount is generated.

The logic gate 66 outputs an auto pulse signal VINTAEB having a small pulse width in response to the sensing control signal PS and the delayed sensing control signal DPS. In response to the auto pulse signal VINTAEB having a small pulse width, the driver 430 properly compensates for the internal power supply voltage VINTA for the cell array.

That is, according to FIGS. 4 to 6, the pulse width of the auto pulse signal VINTAEB is adjusted by the pulse width control circuit 420 in response to the level of the external power supply voltage VEXT, thereby the internal power supply voltage VINTA for the cell array. ) To compensate accordingly.

7 is data showing a change in pulse width according to a change in an external power supply voltage level according to the present invention. This data simulates the pulse width change of the auto pulse signal VINTAEB after fixing the reference voltage VREF at 1.5V and then changing the external power supply voltage VEXT from 1.5V to 4.0V in 0.1V increments. The result is.

In FIG. 7, it can be seen that the pulse width suddenly changes near 2.2 V of the external power supply voltage VEXT, which is a result of detecting the level of the external power supply voltage VEXT. The separation origin (VEXT = 2.2V) of the region of the high power supply voltage and the low power supply voltage claimed in the drawing is arbitrarily designated for convenience of description and does not act as a limiting factor of the present invention.

8 is a graph showing simulation results when the pulse width is reduced at a high power voltage. As shown in FIG. 8, the present invention does not exhibit overshooting of the cell array power supply voltage VINTA at a high power supply voltage (VEXT = 2.5V or more), and a change in the level of the cell array power supply voltage VINTA even at a high power supply voltage. Can hardly be seen and converges to the original level.

9 is a graph illustrating a change in cell restore time according to a pulse width at a low power supply voltage. The result of comparing the operation | movement in the case of using FIG. 1 and FIG. 5 which were the existing circuits at the low power supply voltage 1.8V is shown. Referring to FIG. 9, the delay time from the sensing control signal PS to the time when the sensing of the cell is 95% completed is 31.89 ns when the existing circuit of FIG. 1 is used, and 25.78 ns when a new circuit is added. It can be seen that the cell restore time of the new circuit is increased by about 6ns compared to the existing circuit.

10 is a flowchart illustrating a method of compensating an internal power supply voltage VINTA for a cell array according to the present invention. This will be described with reference to FIGS. 10 and 4 to 6. The predetermined external power supply voltage VEXT is received and the voltage obtained by distributing the external power supply voltage VEXT is compared with the predetermined reference voltage VREF (step 100). The step is performed in the level detection circuit 410. In addition, a pulse signal having a pulse width different from that of the external power supply voltage VEXT is generated (step 110). The step is performed in the pulse width control circuit 420. In operation 130, the cell array internal power supply voltage VINTA is pulled up to an external power supply voltage VEXT in response to the pulse signal. The step is performed by the driver 430 which pulls up the auto pulse signal VINTAEB to the external power supply voltage VEXT.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the circuit for compensating for the drop of the power supply voltage for the cell array and the method for compensating the width of the auto pulse signal used for compensating the power supply voltage for the cell array are sufficiently large at a low power supply voltage. It is effective to prevent the phenomenon that the cell restore time is insufficient at the low power supply voltage.

In addition, the circuit for compensating for the drop of the power supply voltage for the cell array and the method for compensating according to the present invention, by reducing the pulse width of the auto pulse signal at a high power voltage to prevent overshooting of the power supply voltage for the cell array, the external power supply voltage Correspondingly, there is an effect of properly compensating for the drop in the internal power supply voltage for the cell array.

Claims (13)

A driver for pulling up the internal power supply voltage level for the cell array to an external power supply voltage level in response to a pulse signal; And, And a pulse width control circuit for controlling the pulse width of the pulse signal in response to a sensing control signal for controlling sensing of data stored in a memory cell and a level detection signal for transitioning a logic state in response to a change in the external power supply voltage. An internal power supply voltage drop compensation circuit for a cell array of a semiconductor memory device, characterized in that the. The method of claim 1, wherein the external power supply voltage level is And an internal power supply voltage drop compensation circuit for the cell array of the semiconductor memory device, wherein the internal power supply voltage level is higher than the internal power supply voltage level for the cell array. The method of claim 1, The logic state transitions to a first logic state when the level of the external power supply voltage is lower than a level of a predetermined reference voltage, and the logic state is second logic when the level of the external power supply voltage is higher than the level of the reference voltage. An internal power supply voltage drop compensation circuit for a cell array of a semiconductor memory device, characterized in that transition to a state. The method of claim 3, wherein the first logical state and the second logical state And the first logic state is logic 'high', and the second logic state is logic 'low'. The method of claim 1, The pulse width of the pulse signal when the level of the external power supply voltage is lower than the reference voltage is wider than the pulse width of the pulse signal when the external power supply voltage is higher than the reference voltage. Internal power supply voltage drop compensation circuit. An internal power supply voltage drop compensation circuit for a cell array that compensates for a cell array voltage drop of a semiconductor memory device generated when sensing data stored in a memory cell array. A sourcing circuit for charging the cell array voltage to an external power supply voltage in response to a pulse signal having a predetermined pulse width; And, A pulse width control circuit for controlling the pulse width in response to a level detection signal, And the level detection signal transitions a logic state in response to a change in the external power supply voltage. The method of claim 6, When the external power supply voltage is lower than the predetermined reference voltage, the logic state transitions to the first logic state, and when the external power supply voltage is higher than the predetermined reference voltage, the logic state transitions to the second logic state. An internal power supply voltage drop compensation circuit for a cell array of a semiconductor memory device. 8. The method of claim 7, wherein the first logical state and the second logical state And the first logic state is logic 'high', and the second logic state is logic 'low'. The method of claim 6, wherein the pulse width control circuit And in response to the level detection signal, increase the delay when the level detection signal is in the first logic state and decrease the delay when the level detection signal is in the second logic state. Internal power supply voltage drop compensation circuit. 10. The method of claim 9, wherein the first logical state and the second logical state And the first logic state is logic 'high', and the second logic state is logic 'low'. A driver for pulling up the level of the internal power supply voltage for the cell array to an external power supply voltage level in response to the autopulse signal having a predetermined pulse width; A voltage detection circuit for comparing a reference voltage with a first voltage obtained by dividing the external power supply voltage in response to a high power voltage test enable signal and outputting a comparison result; And, And a sensing control signal for controlling the sensing of data stored in the memory cell and a pulse width control circuit for controlling the pulse width of the auto pulse signal in response to the comparison result. Voltage drop compensation circuit. The method of claim 11, wherein the pulse width control circuit Output a signal having a narrow pulse width when the level of the first voltage is higher than the level of the reference voltage; and output a signal having a wide pulse width when the level of the first voltage is lower than the level of the reference voltage. An internal power supply voltage drop compensation circuit for a cell array of a semiconductor memory device. Accepting a predetermined external power supply voltage, comparing the first voltage with which the external power supply voltage is distributed, and a predetermined reference voltage and outputting a comparison result; Generating a pulse signal in response to the comparison result and a sensing control signal for controlling sensing of data stored in a memory cell; And, And pulling up the internal power supply voltage for the cell array to the external power supply voltage in response to the pulse signal, The generating of the pulse signal may include outputting a signal having a narrow pulse width when the level of the first voltage is higher than the level of the reference voltage and wide pulse width when the level of the first voltage is lower than the level of the reference voltage. An internal power supply voltage drop compensation method for a cell array of a semiconductor memory device, comprising: outputting a signal having a signal;