KR20030094480A - Apparatus of semiconductor device including storage node for capacitor and manufacturing method therefor - Google Patents

Abstract

PURPOSE: A semiconductor device having a storage node of a capacitor and a method for manufacturing the same are provided to be capable of effectively increasing the capacitance of the capacitor. CONSTITUTION: A semiconductor device is provided with a semiconductor substrate(100) defined with a plurality of unit cells, a conductive contact(450) formed at the upper portion of the semiconductor substrate in one unit cell region, and at least two cylinder stack type storage nodes(500) of a capacitor, connected with the conductive contact, electrically. At this time, the conductive contact is electrically connected with the predetermined portion of the semiconductor substrate. Preferably, one cylinder stack type storage node has the same surface area as the other cylinder stack type storage node.

Description

A semiconductor device including a storage electrode of a capacitor and a method of manufacturing the same {Apparatus of semiconductor device including storage node for capacitor and manufacturing method therefor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a semiconductor device including a storage node of capacitor capable of realizing an increase in capacitance and a method of manufacturing the same.

As semiconductor memory devices, such as DRAM (DRAM) devices, are increasingly integrated, pattern miniaturization or design rules are rapidly decreasing. Reduction of design rules has caused difficulties in stably securing various characteristics of semiconductor devices, for example, transistors or cell capacitors. In particular, as the design rule is reduced, various methods for securing the capacitance of the capacitor have been proposed.

The type of capacitor currently being tried to secure the capacitance of the capacitor is a simple stack type, a stack type using HSG (HemiSpherical Grain), a cylinder stack type, or a cylinder type using HSG. For example. In the early simple stack type, a weak capacitance has been proposed, and in the case of the stack type using HSG, a bridge failure occurs frequently, which makes it difficult to apply to mass production. In the case of the cylinder stack type, interest in the adoption thereof is gradually increasing.

1 is a cross-sectional view schematically illustrating a storage electrode of a capacitor of a conventional cylinder stack type.

2 is a plan view schematically illustrating a shape in which a storage electrode of a conventional cylinder stack type capacitor is disposed in a unit cell.

1 and 2, one storage electrode 50 for one capacitor is introduced in the form of a cylinder stack on one unit cell on the semiconductor substrate 10. The storage electrode 50 is electrically connected to the active region 11 of the semiconductor substrate 10 through the conductive contact 45 and the contact pad 41 prepared through the lower insulating layers 31 and 35. Are electrically connected to a transistor including a gate 20 formed of two kinds of conductive layers 21 and 25. In this case, a process margin of forming the contact pad 41 may be more widely secured by a capping layer 27 introduced above the gate 20 and a spacer 29 introduced on the sidewall. Can be.

Referring again to FIG. 2, storage electrodes 50 of a conventional cylinder stack type capacitor are introduced one by one into a unit cell. However, in order to secure the capacitance required for the reliable operation of the semiconductor device, a problem arises in that the height of the storage electrode 50 must be greatly increased. However, increasing the height of the storage electrode 50 deepens the structural weakness of the cylinder stacked storage electrode, and is also limited by the patterning process for the storage electrode 50.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device including a storage electrode of a capacitor capable of effectively increasing the capacitance of the capacitor, and a method of manufacturing the same.

FIG. 1 is a cross-sectional view schematically illustrating a storage node for capacitor of a capacitor in the form of a conventional cylinder stack.

FIG. 2 is a plan view schematically illustrating a shape in which a storage electrode of a conventional cylinder stack type capacitor is disposed in a unit cell.

3 is a plan view schematically illustrating a shape in which a storage electrode of a capacitor in a cylinder stack form according to an exemplary embodiment of the present invention is disposed in a unit cell.

4 is a cross-sectional view schematically illustrating a semiconductor device including a storage electrode of a capacitor in the form of a cylinder stack according to an embodiment of the present invention.

5 and 6 are diagrams schematically illustrating an effect of increasing capacitance by a semiconductor device including a storage electrode of a capacitor in a cylinder stack form according to an embodiment of the present invention.

7 and 15 are schematic views illustrating a method of manufacturing a semiconductor device including a storage electrode of a capacitor in the form of a cylinder stack according to an embodiment of the present invention.

One aspect of the present invention for achieving the above technical problem, provides a semiconductor device comprising a storage electrode of the capacitor. The semiconductor device includes at least two cylinders for conductive contacts formed to be electrically connected to the semiconductor substrate portion in one unit cell on a semiconductor substrate, and capacitors electrically connected to the conductive contacts. It comprises storage nodes in the form of a stacker.

Here, the storage electrodes may occupy areas equal to each other.

Another aspect of the present invention for achieving the above technical problem, provides a semiconductor device manufacturing method comprising a storage electrode of a capacitor. The manufacturing method includes forming an insulating layer on a semiconductor substrate, and forming a conductive contact formed through the insulating layer to be electrically connected to the semiconductor substrate portion in one unit cell. And forming storage nodes in the form of at least two cylinder stacks for capacitors to be electrically connected to the conductive contacts.

The forming of the conductive contact may include forming the insulating layer as a multilayer having a wet etching rate higher than that of a lower layer, and patterning the insulating layer to form a contact hole. Wet etching the contact hole to expand the upper inlet portion of the contact hole by relatively rapid wet etching of the top layer of the multilayer, and forming a conductive contact to fill the contact hole. can do.

In this case, the forming of the storage electrode may include introducing a mold layer and a photoresist pattern having patterns in a bar shape orthogonal to each other to expose a portion where the storage electrode is to be formed on the mold layer. And forming the mold layer by patterning the mold layer using the photoresist pattern, and forming the storage electrodes to be shaped by the mold.

In this case, the forming of the photoresist pattern may include forming and exposing a first photoresist pattern including repeated bar patterns, and forming a photoresist layer covering the first photoresist pattern. Bar patterns orthogonal to may be repeatedly exposed and developed to form a second photoresist pattern.

According to the present invention, it is possible to provide a storage electrode structure of a capacitor and a method of manufacturing the capacitor that can effectively increase the capacitance of the capacitor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, the layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. May be interposed.

According to an embodiment of the present invention, a storage cylinder in the form of two cylinder stacks is introduced on the same conductive contact so that two capacitors are connected to one unit cell. In other words, in a storage device such as DRAM, two storage electrodes are introduced at a position where a storage electrode of one capacitor is introduced in a unit cell implemented by one transistor and one capacitor, thereby increasing capacitance by about 25%. You can. In this way, the capacitance can be increased to improve the electrical properties or to lower the cylinder stack height to make it structurally stable and reduce constraints on subsequent processes.

This invention will be described in more detail with reference to specific examples.

3 is a plan view schematically illustrating a shape in which a storage electrode of a capacitor in a cylinder stack form according to an exemplary embodiment of the present invention is disposed in a unit cell.

4 is a cross-sectional view schematically illustrating a semiconductor device including a storage electrode of a capacitor in the form of a cylinder stack according to an embodiment of the present invention.

3 and 4, repeating unit cells are provided on the semiconductor substrate 100, and one unit cell is provided with two cylinder stack-type storage electrodes 500. As the two-cylinder stack-type storage electrodes 500 are introduced as described above, two capacitors are connected in parallel to one unit cell to replace the existing one capacitor. The two storage electrodes 500 introduced in the exemplary embodiment of the present invention are formed on an area substantially equal to the area occupied by the existing storage electrode 50 (FIG. 2). Meanwhile, in order to support the two storage electrodes 500, the conductive contact 450 may be extended in a direction in which a bit line (not shown) extends.

As shown in FIG. 4, the storage electrode 500 is an active region of the semiconductor substrate 100 through the conductive contact 450 and the contact pad 410 prepared through the lower insulating layers 310 and 350. The gate 200, which is electrically connected to the 110, includes two kinds of conductive layers 210 and 250, for example, a conductive poly-silicon layer 210, a metal silicide layer 250, and the like. It is electrically connected to a transistor (transistor) formed to include. In this case, the process margin of forming the contact pad 410 may be more widely secured by the capping layer 270 introduced to the upper side of the gate 200 and the spacer 290 introduced to the sidewall.

As such, by introducing two storage electrodes 500 on an area occupied by one storage electrode (50 in FIG. 2), the capacitance of a capacitor to be formed including the storage electrodes 500 may be greatly increased. have.

FIG. 5 is a plan view schematically illustrating a case in which one storage electrode 50 is introduced into a unit cell, and FIG. 6 illustrates two storage electrodes 50 introduced into a unit cell according to an embodiment of the present invention. It is a top view which is schematically shown in order to demonstrate the case.

Referring to FIGS. 5 and 6, in a general DRAM device, if the length of one short axis of one unit cell is a, the length of another axis may be approximately 2a. When the storage electrode of the capacitor is configured in the unit cell, the storage electrode 50 is configured as shown in FIG. 5. The total circumferential length of the storage electrode 50 in the form of a rectangular cylinder is approximately 6a 'assuming that the length of the short axis is a' and the length of the long axis is 2a '. Similarly, when the two storage electrodes 500 are introduced according to the exemplary embodiment of the present invention as shown in FIG. 6, when the storage electrodes 500 are formed in a similar shape to each other, that is, a square shape is most preferred. Since effective and stable, the total circumferential length of these two storage electrodes 500 is 8a '.

Since the cylinder stack type capacitor generally uses both the inner surface and the outer surface of the storage electrode 500, assuming that the thickness of the cylinder is d except for consideration because the height is constant, the conventional storage electrode 50 The maximum circumferential length that can be used for the capacitor is 12a'-8d, and the maximum circumferential length that can be used for the capacitor in the two storage electrodes 500 in the embodiment of the present invention is 16a'-16d.

For example, when applied to an actual capacitor with a 'of 300 nm and d of 50 nm, the maximum circumferential length that can be used for the capacitor in the conventional storage electrode 50 is 3200 nm, but according to an embodiment of the present invention. The maximum circumferential length that can be used for the capacitors in the two storage electrodes 500 amounts to 4000 nm. Thus, only an increase gain in the length around the storage electrode 500 amounts to 25%. In the actual process, a certain distance must be introduced between the storage electrodes 500 in the form of cylinders, and in the actual process, the corners of the square are rounded, so that the total perimeter of the actual two storage electrodes 500 is smaller. As this will increase, this circumference will reach up to 25% as described above. Increasing the overall circumferential length of these two storage electrodes 500 eventually contributes to an increase in the capacitance of the capacitors employing these two storage electrodes 500.

As described above, a method for introducing two storage electrodes 500 into one unit cell will be described in detail with reference to FIGS. 7 to 15.

7 to 13 are schematic views illustrating a method of manufacturing a semiconductor device including a storage electrode of a capacitor in the form of a cylinder stack according to an embodiment of the present invention.

Referring to FIG. 7, a step of forming the second insulating layer 351 and the bit line 435 on the first insulating layer 310 is schematically illustrated. Specifically, the gate 200 and the like are formed by the transistor process on the active region 110 set by the device isolation 150 of the semiconductor substrate 100. The gate 200 may be formed of a conductive polysilicon layer 210 and a metal silicide layer 250 such as a tungsten silicide layer. The capping insulating layer 270 may be introduced on the gate 200, and the spacer 290 may be introduced on the sidewall of the gate 200. Although not shown, an impurity layer (not shown) for drain and source regions is introduced to a portion adjacent to the gate 200 of the active region 110 of the semiconductor substrate 100.

After the transistors including the gate 200 are formed one by one in the unit cell, the first insulating layer 310 covering the gate 200 is formed of silicon oxide or the like. Thereafter, the conductive contact pads 410 electrically connected to the active region 110, preferably the source region, of the semiconductor substrate 100 adjacent to the gate 200 are formed to penetrate the first insulating layer 310. do. This conductive contact pad 410 is introduced to electrically connect the capacitor to the source region. In addition, a second conductive contact pad 430 penetrating the first insulating layer 310 may be introduced. The second conductive contact pads 430 are introduced to electrically connect the bit line 435 and the drain region of the transistor. The conductive contact pads 410 may be formed by forming a contact hole by a self-aligned etching process using the spacer 290 and the capping insulating layer 270 of the gate 200.

After forming the second insulating layer 351 covering the conductive contact pad 410 or the second conductive contact pad 430 with silicon oxide or the like, a bit line 435 is formed on the second insulating layer 351. . The bit line 435 is electrically connected to the second conductive contact pads 430 through the second insulating layer 351 to be electrically connected to the transistor.

Referring to FIG. 8, a third insulating layer 353 covering the bit line 435 is formed of silicon oxide or the like as an interlayer insulating layer. After planarizing the third insulating layer 353 by chemical mechanical polishing (CMP) or etch back, the third insulating layer 353 may be formed to introduce a wider conductive contact on the third insulating layer 353. The fourth insulating layer 355 is introduced as an insulating material having an etching rate higher than that of the third insulating layer 353. Like the third insulating layer 353, the fourth insulating layer 355 may be formed of an insulating material different from silicon oxide, but may also be formed of silicon oxide. When the fourth insulating layer 355 is made of silicon oxide, the densification degree, that is, the density is lower than that of the third insulating layer 353 may help to indicate a relatively fast wet etch rate.

Referring to FIG. 9, a contact hole 451 is formed to expose an upper surface of the conductive contact pad 410. Specifically, the contact hole 451 exposing the upper surface of the conductive contact pad 410 by patterning the fourth insulating layer 355, the third insulating layer 353, and the second insulating layer 351 by a photolithography process. ). In this case, the etching process may use dry anisotropic etching.

Referring to FIG. 10, the upper inlet portion of the contact hole 451 is widened through wet etching. Since the fourth insulating layer 355 is preferably formed of an insulating material having a higher wet etching rate than that of the third insulating layer 353, for example, silicon oxide, when the contact hole 451 is wet-etched, the contact hole 451 may be formed. The portion of the fourth insulating layer 355 constituting the sidewall of the inlet portion is etched at a relatively high speed compared to the third insulating layer 353 below. As a result, a contact hole 451 'having a relatively large upper inlet portion is formed.

Referring to FIG. 11, the contact hole 451 ′ is filled to form a conductive contact 450 electrically connected to the conductive contact pad 410. The conductive contact 450 is formed by forming a conductive layer filling the contact hole 451 ', for example, a conductive polysilicon layer, and then flattening the conductive layer with an etch back or a CMP to limit the conductive contact 450 into the contact hole 451'. do. At this time, since the upper inlet of the contact hole 451 ′ is introduced wider than the lower portion, the conductive contact 450 also has an upper portion of the upper portion extending in the direction in which the bit line 435 extends from the lower portion. As shown in FIG. 3, the conductive contact 450 having the extended upper portion is to support and electrically connect the two storage electrodes 500 together.

Meanwhile, although the conductive contact 450 is formed by introducing a contact hole 451 ′ having a relatively large upper inlet with reference to FIGS. 9 to 11, two storage electrodes 500 according to the present invention are described. Extended conductive contacts may be formed in other ways. For example, the contact hole for the conductive contact may be introduced in a form in which the bit line extends in the extending direction, and consequently, the conductive contact may be introduced in the form in which the bit line extends in the extending direction. In addition, when forming a contact hole for a conductive contact by adding a spacer and a capping layer (not shown) to the bit line, a wider contact hole can be introduced by introducing a self aligned etch (SAC). . Accordingly, the upper surface of the conductive contact can be expanded.

Referring to FIG. 12, two storage electrodes 500 are electrically connected to the conductive contacts 450. The process of forming each storage electrode 500 is formed according to a known process of forming a storage electrode in the form of a cylinder stack, but as shown in FIG. 3, one capacitor is introduced so that two capacitors are introduced into one unit cell. Two storage electrodes 500 are connected to the contact 450.

Specifically, a mold layer covering the fourth insulating layer 355 and the conductive contact 450 is formed. The mold layer is introduced for the mold 700 for imparting a three dimensional cylinder shape to the storage electrode 500. The mold layer is removed by wet etching after the storage electrode 500 is formed. When the mold layer is preferably formed of a silicon oxide layer, an etch stop layer may be further introduced into the silicon nitride (Si ₃ N ₄ ) at the bottom of the mold layer so as to terminate the etch in the etching process of patterning a subsequent mold layer. Can work.

Thereafter, a photoresist layer for a photolithography process is formed on the mold layer. A photoresist is performed on the photoresist layer to form a photoresist pattern (not shown). The photoresist pattern may be formed to expose the mold layer portion where the actual storage electrode 500 is to be formed. Since the two storage electrodes 500 are formed to be substantially aligned with the left and right upper sides of the conductive contact 450, a photoresist pattern is formed accordingly.

Thereafter, the mold layer is patterned using the photoresist pattern as an etching mask to form the mold 700. In this case, a hard mask (not shown) patterned by the photoresist pattern may be further introduced and used together as the etching mask. In this case, the hard mask may be made of polysilicon or the like. Thereafter, a conductive storage electrode layer having a shape is deposited along the mold 700, and then planarized with an etch back or a CMP to be separated into each storage electrode 500.

Referring to FIG. 13, two storage electrodes 500 are implemented in one unit cell by selectively removing the mold 700. By the above-described process, two storage electrodes 500 electrically connected to one conductive contact 450 are formed in the form of a cylinder stack. In this case, the storage electrode 500 may be formed of conductive polysilicon.

Subsequently, in order to configure a capacitor employing the storage electrode 500, a dielectric layer (not shown) and a plate electrode (not shown) may be formed on the storage electrode 500 to complete the capacitor. Accordingly, two capacitors connected to one conductive contact 450 may be provided, so that two capacitors are provided in one unit cell in the DRAM device.

Meanwhile, since two storage electrodes 500 are provided in one conductive contact 450, a higher capacitance may be realized by minimizing a gap between the storage electrodes 500. In order to minimize the gap between the storage electrodes 500, it is important to increase the resolution of the photoresist pattern used in the process of patterning the mold layer into a mold. To this end, an embodiment of the present invention proposes to implement a photoresist pattern at a higher resolution by the following process.

14 and 15 are views schematically illustrating a method of forming a photoresist pattern employed in a method of manufacturing a semiconductor device including a storage electrode of a capacitor in a cylinder stack form according to an embodiment of the present invention. .

14 and 15, the photoresist pattern 600 for the storage electrode 500 may be formed through two photo development processes. First, as illustrated in FIG. 14, the first photoresist pattern 610 having a vertical bar shape, which is repeated by using a straight bar mask having a vertical bar shape, is formed by exposing and developing a photoresist layer. Subsequently, after the photoresist layer is applied again, the second photoresist pattern 650 having a horizontal bar shape is repeated to the first photoresist pattern 610 by exposure and development by using a horizontal bar-shaped pattern mask. Form orthogonally. In this manner, in order to form a mold for the storage electrode 500, the photoresist pattern 650 may be formed as an etching mask in the process of selectively etching the mold layer. The photoresist pattern 650 is composed of bar-shaped patterns that are orthogonal to expose the mold layer portion of the portion where the storage electrode 500 is to be formed.

By forming the photoresist pattern 600 in the form of a bar as described above, the resolution in the photographing process of forming the photoresist pattern 600 can be relatively increased. Accordingly, the resolution of the photoresist pattern 600 may be relatively high, and thus, the gap between the storage electrodes 500 may be minimized. Accordingly, the capacitance of the capacitor can be maximized.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

According to the present invention described above, by increasing the capacitance per unit cell by introducing two cylinder stack-type storage electrodes in place of the conventional one-cylinder stack-type storage electrodes. An increase in capacitance of approximately 10% to 25% can be achieved for the same capacitor footprint. In this way, the increase in capacitance can be realized, and the height of the cylinder stack of the entire storage electrode can be lowered. Accordingly, the structural stability of the storage electrode can be improved, thereby reducing the burden on subsequent processes.

Claims (6)

A conductive contact formed on the semiconductor substrate so as to be electrically connected to the semiconductor substrate portion in one unit cell; And And storage nodes in the form of at least two cylinder stacks for capacitors formed to be electrically connected to the conductive contacts. The method of claim 1, And the storage electrodes each occupy an area equal to each other. Forming an insulating layer on the semiconductor substrate; Forming a conductive contact formed through the insulating layer to be electrically connected to a portion of the semiconductor substrate in one unit cell; And Forming storage nodes in the form of at least two cylinder stacks for capacitors to be electrically connected to the conductive contacts. 4. The method of claim 3, wherein forming the conductive contact Forming the insulating layer into a multilayer in which the uppermost layer has a higher wet etch rate than the lower layer; Patterning the insulating layer to form a contact hole; Wet etching the contact hole to expand the upper inlet portion of the contact hole by relatively rapid wet etching of the top layer of the multilayer; And Forming a conductive contact filling the contact hole. The method of claim 3, wherein forming the storage electrode Introducing a mold layer; Forming a photoresist pattern having bar-shaped patterns orthogonal to each other so as to expose a portion where the storage electrode is to be formed on the mold layer; Patterning the mold layer using the photoresist pattern to form a mold; And Forming the storage electrodes that are shaped by the mold. The method of claim 5, wherein the forming of the photoresist pattern is performed. Exposing and developing a first photoresist pattern consisting of repeated bar patterns; And And forming a second photoresist pattern by repeatedly exposing and developing a photoresist layer covering the first photoresist pattern and bar patterns orthogonal to the bar patterns.