KR20030092329A - High efficient solar cell and fabrication method thereof - Google Patents
High efficient solar cell and fabrication method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 80
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 80
- 239000010703 silicon Substances 0.000 claims abstract description 80
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 239000000155 melt Substances 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 239000000243 solution Substances 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 239000007791 liquid phase Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000010587 phase diagram Methods 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000006104 solid solution Substances 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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Abstract
Description
본 발명은 고효율 태양전지 및 그 제조방법에 관한 것으로, 더욱 상세하게는 용액성장법을 이용하여 전면 전극을 형성하는 방법에 관한 것이다.The present invention relates to a high efficiency solar cell and a method for manufacturing the same, and more particularly, to a method of forming a front electrode using a solution growth method.
일반적으로 태양전지는, 외부에서 들어온 빛에 의해 태양전지의 반도체 내부에서 전자와 정공의 쌍이 생성되고, 이러한 전자와 정공의 쌍에서 pn 접합에서 발생한 전기장에 의해 전자는 n형 반도체로 이동하고 정공은 p형 반도체로 이동함으로써 전력을 생산한다.In general, a solar cell has a pair of electrons and holes generated inside the semiconductor of the solar cell by light from outside, and electrons move to an n-type semiconductor by an electric field generated at a pn junction in the pair of electrons and holes. Moving to p-type semiconductors produces power.
종래 태양전지의 효율을 높이기 위해 고안된 고효율 태양전지 구조의 하나인 함몰전극구조의 태양전지(BCSC : buried contact solar cell)에서는 태양전지의 전면에 홈을 형성하고 홈의 내부를 도전성 물질로 충진시킴으로써 전면의 금속전극을함몰된 형태로 형성한다.In buried contact solar cell (BCSC), which is one of the high efficiency solar cell structure designed to improve the efficiency of conventional solar cell, the groove is formed on the front of the solar cell and the inside of the groove is filled with a conductive material. To form a metal electrode of the recessed shape.
이와 같이 전면의 금속전극을 실리콘 기판의 내부에 함몰구조로 형성하면, 실리콘 산화막 상에 전극을 형성하는 경우에 비해 낮은 접촉저항을 얻을 수 있으며, 전극이 기판 상면에서 차지하는 면적만큼 태양광을 흡수하지 못함으로 인해 발생하는 손실인 쉐이딩 손실(shading loss)을 2~3% 줄일 수 있다. 따라서 함몰전극구조의 태양전지는 태양전지의 고효율화와 저가격화에 적합한 것으로 알려져 있다.In this way, if the metal electrode on the front surface is formed in the silicon substrate, the contact resistance is lower than that of the electrode on the silicon oxide film, and the electrode does not absorb sunlight as much as the area occupied by the upper surface of the substrate. Shading loss, which is caused by failure, can be reduced by 2-3%. Therefore, the solar cell of the recessed electrode structure is known to be suitable for high efficiency and low price of the solar cell.
함몰전극구조의 태양전지에 관한 종래 기술로는 미국특허 4,748,130호 및 4,726,850호가 있으며, 이들 특허에서는, 먼저 p형 실리콘 기판의 전면에 홈을 형성하고, 홈을 포함한 p형 실리콘 기판의 전면 상에 인(P)을 도핑하여 n층을 형성한 다음, p형 실리콘 기판의 후면에 Al층을 형성하여 후면전극을 형성하고, 홈의 내벽에 고농도로 인을 도핑하여 고농도 불순물 영역을 형성한 후, 도금 또는 진공증착 등의 방법으로 홈의 내부를 은(Ag)으로 충진시켜 전면전극을 함몰 구조로 형성한다.Conventional techniques related to solar cells with recessed electrode structures include US Pat. Nos. 4,748,130 and 4,726,850. In these patents, grooves are first formed in the front surface of a p-type silicon substrate, and the phosphors are formed on the front surface of the p-type silicon substrate including the grooves. After doping (P) to form an n layer, an Al layer is formed on the back surface of the p-type silicon substrate to form a back electrode, and a high concentration impurity region is formed by doping phosphorus at a high concentration on the inner wall of the groove, followed by plating. Alternatively, the inside of the groove is filled with silver (Ag) by vacuum deposition or the like to form the front electrode in a recessed structure.
상기한 제조공정에서 전면전극과 실리콘 기판 사이에 옴성 접촉(ohmic contact)을 형성하기 위해 고농도로 인을 도핑하여 고농도 불순물 영역을 형성하는데, 이 때 고농도로 인을 도핑하기 위해 800℃ 이상의 고온으로 열처리하는 과정을 거친다.In the above manufacturing process, a high concentration of impurity regions are formed by doping phosphorus at a high concentration to form an ohmic contact between the front electrode and the silicon substrate. In this case, heat treatment is performed at a high temperature of 800 ° C. or higher to dope phosphorus at a high concentration. Go through the process.
그러나, 고온으로 열처리할 때에 로(furnace)로부터 불순물의 유입이 촉진될 수 있으며, 특히 다결정 실리콘 기판을 이용할 경우 과도한 열부하로 태양전지의 성능이 저하되는 문제점이 있었다.However, the inflow of impurities from the furnace (furnace) may be promoted when the heat treatment at a high temperature, especially when using a polycrystalline silicon substrate has a problem that the performance of the solar cell is degraded due to excessive heat load.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 불순물이 없고 열부하로 인한 성능저하가 방지되어 효율이 향상된 고효율 태양전지를 저렴한 공정 비용으로 제조하는 데 있다.The present invention is to solve the problems as described above, the object is to produce a high efficiency solar cell with low process cost improved efficiency by preventing impurities and performance degradation due to heat load.
도 1은 본 발명의 일 실시예에 따른 고효율 태양전지 구조가 도시된 사시도이다.1 is a perspective view showing a high efficiency solar cell structure according to an embodiment of the present invention.
도 2는 금속과 실리콘의 상태도(phase diagram)이다.2 is a phase diagram of metal and silicon.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 금속의 온도에 따른 실리콘의 고용도 차이를 이용한 용액성장법으로 실리콘 기판의 전면에 금속이 도핑된 실리콘층과 실리콘이 소량 함유된 금속층을 형성하고, 그 위에 전면전극을 형성하는 것을 특징으로 한다.In order to achieve the object as described above, in the present invention, a silicon layer doped with a metal and a metal layer containing a small amount of silicon are formed on the entire surface of the silicon substrate by a solution growth method using a difference in the solid solution of silicon according to the temperature of the metal. And forming a front electrode thereon.
이하, 본 발명에 따른 고효율 태양전지의 구성에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a configuration of a high efficiency solar cell according to the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 일 실시예에 따른 고효율 태양전지 구조를 도시한 사시도로서, 함몰전극구조 태양전지가 도시되어 있다.1 is a perspective view illustrating a structure of a high efficiency solar cell according to an embodiment of the present invention, in which a recessed electrode structure solar cell is illustrated.
도 1에 도시된 바와 같이, 제1도전형, 예를 들면 p형의 실리콘 기판(11) 상에는 이와 반대 도전형을 가지는 제2도전형, 예를 들면 n형의 반도체층(이하 n층이라 칭함)(12)이 형성되어 있고, p형의 실리콘 기판(11)과 n층(12) 사이의 계면에는 pn 접합이 형성되어 있어 태양전지의 필수 구성 요소인 pn 구조가 도시되어 있다.As shown in FIG. 1, a second conductive type, for example, an n-type semiconductor layer (hereinafter referred to as n-layer) having a conductivity type opposite to that of the first conductive type, for example, a p-type silicon substrate 11, is described below. 12 is formed, and a pn junction is formed at the interface between the p-type silicon substrate 11 and the n-layer 12 to show a pn structure which is an essential component of the solar cell.
n층(2)의 전면 및 p형의 실리콘 기판(11) 후면 상에는 각각 SiO2층(13a, 13b)이 형성되어 있다.SiO 2 layers 13a and 13b are formed on the front surface of the n-layer 2 and the back surface of the p-type silicon substrate 11, respectively.
n층(2)의 전면에 형성된 SiO2층(13a)의 표면으로부터 다수개의 홈(14)이 실리콘 기판(11)이 노출되는 소정깊이로 형성되어 있으며, 홈(14)의 내부에는 n형 불순물이 고농도로 도핑된 n+실리콘층(15)이 1~5 ㎛ 두께로 형성되어 있고, n+실리콘층(15) 상에는 실리콘이 소량 포함된 실리콘 함유 금속층(16)이 형성되어 홈(14)의 내부를 충진하고 있다.A plurality of grooves 14 are formed to a predetermined depth from which the silicon substrate 11 is exposed from the surface of the SiO 2 layer 13a formed on the front surface of the n-layer 2, and the n-type impurities are formed inside the grooves 14. The highly doped n + silicon layer 15 is formed to a thickness of 1 to 5 μm, and a silicon-containing metal layer 16 containing a small amount of silicon is formed on the n + silicon layer 15 to form a groove 14. It is filling the inside.
이 때, n+실리콘층(15)과 실리콘 함유 금속층(16)은 금속의 온도에 따른 실리콘의 고용도 차이를 이용한 용액성장법으로 형성된 것으로서, 용액성장법은 기본적으로 열 평형상태에서 이루어지기 때문에 실리콘 기판에 열적 불안정성을 가져오지 않으며, 또한 용액성장법으로 형성된 n+실리콘층(15)과 실리콘 함유 금속층(16)에는 결함이 전혀 없다.At this time, the n + silicon layer 15 and the silicon-containing metal layer 16 is formed by the solution growth method using the difference in the solid solution of silicon according to the temperature of the metal, since the solution growth method is basically made in the thermal equilibrium state There is no thermal instability in the silicon substrate, and there are no defects in the n + silicon layer 15 and the silicon-containing metal layer 16 formed by the solution growth method.
실리콘 함유 금속층(16) 상에는 전면전극(17)이 형성되어 있다.The front electrode 17 is formed on the silicon containing metal layer 16.
p형 실리콘 기판(11)의 후면에서는 SiO2층(13b)이 부분적으로 식각된 후면전극패턴(18)이 형성되어 있고, 후면전극패턴(18) 하부의 p형 실리콘 기판(11)에는 국부적으로 p형 불순물이 고농도로 도핑된 p+영역(19)이 형성되어 있으며, 후면전극패턴(18)을 포함한 후면 SiO2층(13b)의 상부 전면에는 후면전극(20)이 형성되어 있다.On the back surface of the p-type silicon substrate 11, a back electrode pattern 18 is formed in which the SiO 2 layer 13b is partially etched. The p-type silicon substrate 11 under the back electrode pattern 18 is locally formed. A p + region 19 doped with a high concentration of p-type impurities is formed, and a rear electrode 20 is formed on an upper front surface of the rear SiO 2 layer 13b including the rear electrode pattern 18.
그러면, 상기한 바와 같은 본 발명의 일 실시예에 따른 고효율 태양전지를제조하는 방법에 대해 상세히 설명한다.Then, a method of manufacturing a high efficiency solar cell according to an embodiment of the present invention as described above will be described in detail.
먼저, p형의 실리콘 기판(11)의 전면에 인(P)을 도핑하여 n층(12)을 형성하고, 반사방지 효과를 위해 n층(12) 전면 및 실리콘 기판(11)의 후면에 SiO2층(13a, 13b)을 형성한다.First, an n-layer 12 is formed by doping phosphorus (P) on the front surface of the p-type silicon substrate 11, and SiO is disposed on the front surface of the n-layer 12 and the back surface of the silicon substrate 11 for the antireflection effect. Two layers 13a and 13b are formed.
다음, 화학적 에칭, 기계적인 스크라이빙, 또는 레이저 등을 이용하여 n층(12)의 표면으로부터 실리콘 기판(11)이 노출되는 소정깊이로 다수개의 홈(14)을 형성한다.Next, a plurality of grooves 14 are formed to a predetermined depth through which the silicon substrate 11 is exposed from the surface of the n layer 12 using chemical etching, mechanical scribing, laser, or the like.
다음, 상기한 홈(14)이 형성된 실리콘 기판 구조물을 실리콘이 포화된 금속 용융액 내에 침지한 다음, 금속과 실리콘의 상태도에서 해당 조성의 액상선 이하의 온도로 하강하여 용액성장법으로 홈(14) 내에 금속이 고농도로 도핑된 n+실리콘층(15) 및 실리콘이 소량 포함된 실리콘 함유 금속층(16)을 형성한다.Next, the silicon substrate structure in which the grooves 14 are formed is immersed in a metal molten metal saturated with silicon, and then the grooves 14 are formed by the solution growth method by lowering the temperature below the liquidus line of the corresponding composition in the state diagram of the metal and silicon. An n + silicon layer 15 heavily doped with metal and a silicon-containing metal layer 16 containing a small amount of silicon are formed therein.
이 때, 금속과 실리콘의 용융액에 사용된 금속으로는 Sb , Bi , As 등이 있다. 또한, 금속과 실리콘의 용융액에서 실리콘이 포화되어 있는 것이 바람직하고, 용융액의 온도를 하강할 때에는 냉각속도를 2 ℃/min 이하로 하강하는 것이 바람직하다.At this time, metals used in the melt of the metal and silicon include Sb, Bi, As and the like. In addition, it is preferable that the silicon is saturated in the melt of the metal and silicon, and when the temperature of the melt is lowered, the cooling rate is preferably lowered to 2 ° C / min or less.
도 2는 금속(M)과 실리콘의 상태도(phase diagram)로서, 여기에는 액상영역(L), 액상과 실리콘 고상의 공존영역(L+Si), 액상과 금속 고상의 공존영역(L+M), 그리고 고상영역(S)가 도시되어 있다. 이에 도시된 바와 같이, 실리콘이 포화된 조성의 금속 용융액(A)의 온도를 ΔT 만큼 하강하면(B) 실리콘이ΔX 만큼 과포화된 상태가 되고, 이 과포화된 실리콘은 액상 에피택시(epitaxy) 성장을 통해 고상으로 석출된다. 이 때 성장된 실리콘층은 1019/cm3이상의 금속을 함유하며, 이와 같이 하는데 금속이 1019/cm3이상 함유된 실리콘층은 n+층의 역할을 충분히 수행하는 것이다.FIG. 2 is a phase diagram of the metal (M) and silicon, which includes a liquid phase region (L), a coexistence region (L + Si) of a liquid phase and a silicon solid phase, and a coexistence region (L + M) of a liquid phase and a metal solid phase. ), And the solid state region S is shown. As shown in the drawing, when the temperature of the metal melt (A) having a saturated composition of silicon is lowered by ΔT (B), the silicon becomes supersaturated by ΔX, and the supersaturated silicon causes liquid epitaxy growth. Precipitates to solid through. In this case, the grown silicon layer contains 10 19 / cm 3 or more of metal, and the silicon layer containing 10 19 / cm 3 or more of the metal sufficiently performs the role of n + layer.
또한, 상기한 바와 같이 용액 성장법에서는 열적 평형을 유지하기 위한 방향으로 반응이 진행되어 실리콘층이 성장하기 때문에, n+실리콘층(15)은 홈을 통해 노출된 실리콘 기판(11)에서만 에피택시 성장하며, SiO2층(13a)에서는 성장하지 않는다.In addition, as described above, in the solution growth method, since the reaction proceeds in a direction for maintaining thermal equilibrium and the silicon layer grows, the n + silicon layer 15 is epitaxy only in the silicon substrate 11 exposed through the groove. It grows and does not grow in the SiO 2 layer 13a.
이와 같이 n+실리콘층(15)이 성장하다가 온도가 공융점(eutectic point, 도 3에서 E로 표시) 이하로 하강하면 실리콘과 금속이 α:β의 조성인 고상이 석출되는데, 이는 실리콘 함유 금속층(16)에 해당된다.As such, when the n + silicon layer 15 grows and the temperature falls below the eutectic point (denoted by E in FIG. 3), a solid phase having a composition of α: β of silicon and metal precipitates, which is a silicon-containing metal layer. This corresponds to (16).
이러한 실리콘 함유 금속층(16) 내에 존재하는 실리콘의 양은 상태도로부터 예측되는 이론적인 조성과 유사하나 금속 내에서의 실리콘의 용해도 차이에 의해 약간의 변화폭이 있다. 따라서, 실리콘 함유 금속층(16) 내의 실리콘 함량은 0.01~3 at% 이다.The amount of silicon present in the silicon-containing metal layer 16 is similar to the theoretical composition predicted from the state diagram, but there is a slight variation due to the difference in solubility of silicon in the metal. Therefore, the silicon content in the silicon containing metal layer 16 is 0.01 to 3 at%.
일예로, 금속이 Bi 인 경우 실리콘 함유 금속층(16)에는 실리콘이 0.2 at% 정도로 포함되고, 금속이 As 인 경우에는 실리콘이 1 at% 정도로 포함된다.For example, when the metal is Bi, the silicon-containing metal layer 16 contains about 0.2 at% of silicon, and when the metal is As, about 1 at% of silicon is included.
다음, 실리콘 함유 금속층(16) 상에 도금법, 진공증착법, 또는 스크린 프린팅(screen printing) 방법 등을 이용하여 Ag, Cu 등과 같은 물질로 이루어진 전면전극(17)을 형성한다.Next, the front electrode 17 made of a material such as Ag, Cu or the like is formed on the silicon-containing metal layer 16 by using a plating method, a vacuum deposition method, or a screen printing method.
다음, 실리콘 기판(11)의 후면에 형성된 SiO2층(13b)을 부분적으로 식각하여 후면전극패턴(18)을 형성하고, 후면전극패턴(18)을 통해 p형 불순물을 도핑하여 실리콘 기판(11) 내에 국부적으로 p+영역(19)을 형성한 다음, 후면전극패턴(18)을 포함한 SiO2층(13b)의 상부 전면에 후면전극(20)을 형성함으로써, 태양전지 제조를 완료한다.Next, the SiO 2 layer 13b formed on the back surface of the silicon substrate 11 is partially etched to form the back electrode pattern 18, and the silicon substrate 11 is doped with p-type impurities through the back electrode pattern 18. Next, a p + region 19 is formed locally, and then a back electrode 20 is formed on the upper front surface of the SiO 2 layer 13b including the back electrode pattern 18, thereby completing solar cell manufacturing.
상기한 바와 같이, 본 발명에서는 용융성장법을 이용하여 n+실리콘층을 형성할 때 불순물 유입이 없어서 무결함층으로 형성하기 때문에, 종래 n+영역을 형성하기 위해 고온으로 열처리할 때 발생하였던 불순물 유입 문제가 해결되는 효과가 있으며, 또한, 열부하가 없으므로 태양전지의 변환효율이 향상되는 효과가 있다.As described above, in the present invention, since the impurity is not formed when the n + silicon layer is formed by the melt growth method, and thus is formed as a defect-free layer, the impurity generated when heat treatment at a high temperature in order to form the n + region is performed. There is an effect that the inflow problem is solved, and also there is no heat load has the effect of improving the conversion efficiency of the solar cell.
또한, 종래 고온 열처리에 비해 공정시간이 단축되므로 에너지 비용이 절감되는 효과가 있다.In addition, since the process time is shortened compared to the conventional high temperature heat treatment, the energy cost is reduced.
그리고, 본 발명에 따라 용융성장법으로 형성한 n+실리콘층 및 실리콘 함유 금속층 상에 전면전극을 형성할 때에, 도금법, 스크린 프린팅과 같은 저가의 공정을 적용하기에 용이하므로, 결과적으로 저가격의 태양전지의 제조를 실현하는 효과가 있다.In addition, when forming the front electrode on the n + silicon layer and the silicon-containing metal layer formed by the melt growth method according to the present invention, it is easy to apply low-cost processes such as plating and screen printing, resulting in a low-cost aspect There is an effect of realizing the manufacture of a battery.
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