KR20030091663A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a ferroelectric capacitor, and has an object to provide a capacitor having a lower electrode capable of satisfactorily connecting metal wirings. On the first insulating film 11 formed on the upper side of the semiconductor substrate 1, the adhesion layer 12a formed of the titanium oxide of grain larger than the height formed on the first insulating film 11, and the adhesion layer 12a. A capacitor lower electrode 13a including a formed precious metal, a capacitor dielectric film 14a made of a ferroelectric material formed on the capacitor lower electrode 13a, and a capacitor upper electrode 15a formed on the capacitor dielectric film 14a. .

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a ferroelectric capacitor and a method for manufacturing the same.

Flash memory and ferroelectric memory (FeRAM) are known as nonvolatile memories that can store information even when the power supply is turned off.

The flash memory has a floating gate embedded in a gate insulating film of an insulated gate type field effect transistor (IGFET), and stores information by accumulating charge representing the storage information on the floating gate. For writing and erasing information, it is necessary to flow a tunnel current through the gate insulating film, and a relatively high voltage is required.

FeRAM has a ferroelectric capacitor which stores information using the hysteresis characteristics of the ferroelectric. The ferroelectric film formed between the upper electrode and the lower electrode in the ferroelectric capacitor generates polarization according to the voltage applied between the upper electrode and the lower electrode, and has a spontaneous polarization that maintains the polarization even when the applied voltage is removed.

Inverting the polarity of the applied voltage also inverts the polarity of the spontaneous polarization. By detecting the polarity and magnitude of the spontaneous polarization, information can be read. FeRAM operates at a lower voltage than a flash memory, and has the advantage that high-speed writing is possible due to power saving.

As the capacitor used for the FeRAM memory cell, a planar type structure having a wiring contact region on the upper surface is used.

The planar ferroelectric capacitor is formed by, for example, a process as shown in Figs. 1A and 1B.

First, as shown in FIG. 1A, the metal oxide film 103, the first metal film 104, the ferroelectric film 105, and the first oxide film are formed on the interlayer insulating film 102 covering the silicon substrate 101. 2 metal film 106 is formed. Subsequently, as shown in FIG. 1B, the second metal film 106 is patterned to form the capacitor upper electrode 106a, and the ferroelectric film 105 is patterned to form the capacitor dielectric film 105a. Is done. In addition, by patterning the first metal film 104 and the metal oxide film 103, the first metal film 104 is used as the capacitor lower electrode 104a.

In Japanese Unexamined Patent Publication No. 10-22463, a titanium oxide film is formed as the metal oxide film 103, and a metal film such as platinum, platinum alloy, iridium, and iridium oxide is formed as the first metal film 104. As the method of forming a titanium oxide film by the process in that document, the oxygen introduction electron beam vapor deposition method, the oxygen introduction RF sputtering method, and the oxygen introduction DC sputtering method are mentioned as an example. Further, as a method of forming a titanium oxide film in a plurality of processes, a method of forming a titanium film by a DC sputtering method, an RF sputtering method, or an electron beam deposition method, and then partially oxidizing a part of the titanium film in an oxygen atmosphere by partial oxidation is described. .

However, in order to increase the spontaneous polarization of the ferroelectric film 105 constituting the capacitor dielectric film 105a, for example, the PZT film, it is necessary to increase the surface orientation strength of the platinum film constituting the lower electrode 104a. . In order to increase the <222> plane orientation strength of the platinum film, it is necessary to increase the <200> plane orientation strength of the plane orientation of the titanium oxide film.

In order to increase the orientation strength of the <200> plane of the titanium oxide film, it is preferable to form a titanium oxide film by oxidizing the titanium film in an oxygen atmosphere after forming the titanium film on the insulating film.

However, when only the oxygen gas is introduced into the oxidizing atmosphere to oxidize the titanium film to form the titanium oxide film, the surface of the titanium oxide film becomes rough, and thus the surface of the platinum film on the titanium oxide film may be rough.

If the surface roughness of the platinum film constituting the lower electrode becomes large, there is a fear that a defect may occur in the connection between the capacitor lower electrode and the lead wire. For example, in the structure in which the wiring made of aluminum is connected to the lower electrode via the titanium barrier metal film, when the roughness of the surface of the capacitor lower electrode becomes large, the aluminum wiring and the platinum film react with each other to easily cause connection failure.

An object of the present invention is to provide a semiconductor device having a capacitor having a lower electrode capable of satisfactorily connecting wiring and a manufacturing method thereof.

1 (a) and (b) are cross-sectional views showing a conventional capacitor forming process.

2A and 2B are cross-sectional views (part 1) showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

3 (a) to 3 (c) are cross-sectional views (part 2) showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

4 (a) to 4 (c) are cross-sectional views (part 3) showing the manufacturing process of the semiconductor device according to the embodiment of the present invention.

5A and 5B are sectional views (No. 5) showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 6 shows the dependence of the <200> plane orientation integral intensity and the <200> plane orientation half-value width of the XRD pattern on the formation conditions of the titanium oxide film constituting the adhesion layer of the capacitor lower electrode of the semiconductor device according to the embodiment of the present invention. Figure shown.

FIG. 7 shows a titanium oxide film formed by oxidizing a titanium film with an oxygen flow rate of 1%. FIG.

8 shows a titanium oxide film formed by oxidizing a titanium film at an oxygen flow rate of 100%.

Fig. 9 is a view showing the integrating orientation strength of the XRD pattern of the platinum film formed on the titanium oxide film formed by oxidizing the titanium film with different oxygen flow ratios.

Fig. 10 is a graph showing the relationship between the film forming temperature of Pt constituting the capacitor lower electrode and the defective rate of FeRAM.

11 is a plan view showing a monitor capacitor having the same structure as the capacitor of the semiconductor device according to the embodiment of the present invention.

12 (a) and 12 (b) are plan views showing the presence or absence of deterioration of the lower electrode contact region depending on the conditions for forming the platinum lower electrode constituting the monitor capacitor shown in FIG.

Fig. 13 is a sectional view showing a connection portion between a capacitor lower electrode made of platinum and aluminum wiring formed at a substrate temperature of 550 ° C.

Fig. 14 is a sectional view showing a connection portion between a capacitor lower electrode made of platinum and an aluminum wiring formed at a substrate temperature of 100 ° C.

<Explanation of symbols for the main parts of the drawings>

1: silicon substrate

2: device isolation insulating film

3a: p well

3b: n well

4: gate insulating film

5a to 5c: gate electrode

6: sidewall insulating film

7a, 7b: n-type impurity diffusion region

8a, 8b: p-type impurity diffusion region

11: interlayer insulation film

12: Ti film

12a: TiO _x film

13: first conductive film

13a: capacitor lower electrode

The above object is a first insulating film formed on the upper surface of the semiconductor substrate, an adhesive layer formed on the first insulating film of a titanium oxide having a larger width than the height, a capacitor lower electrode comprising a noble metal formed on the adhesion layer and And a capacitor dielectric film made of a ferroelectric material formed on the capacitor lower electrode, and a capacitor upper electrode formed on the capacitor dielectric film.

The above object is to oxidize and oxidize the titanium film in a step of forming a first insulating film above the semiconductor substrate, a step of forming a titanium film on the first insulating film, and an atmosphere introduced with an oxygen gas flow rate of 50% or less. Forming a titanium film, forming a first conductive film made of a noble metal on the titanium oxide film, forming a ferroelectric film on the first conductive film, forming a second conductive film on the ferroelectric film, Forming an upper electrode of the capacitor by patterning the second conductive film; forming a dielectric film of the capacitor by patterning the dielectric film; and forming a lower electrode of the capacitor by patterning the first conductive film. It is solved by the manufacturing method of a semiconductor device characterized by the above-mentioned.

According to the present invention, there is provided an adhesion layer made of grained titanium oxide having a width larger than the height between the lower electrode made of the noble metal constituting the capacitor and the insulating film below it. Such grain size titanium oxide film is formed by oxidizing while heating a titanium film in the atmosphere introduce | transduced with the oxygen gas flow rate ratio below 50%, Preferably it is 10% or less.

Compared with the titanium oxide film formed by oxidizing a titanium film on the conditions of 100% of an oxygen flow ratio, this titanium oxide film has a small aspect ratio, and has high <200> plane orientation strength, and is excellent in flatness.

As the flatness of the surface of the adhesion layer is improved, the flatness of the lower electrode formed thereon is also improved, and the contact with the wiring connected to the lower electrode is also good. In addition, the higher the <200> plane orientation strength of the adhesion layer, the higher the <222> plane orientation strength of the lower electrode metal film formed thereon, for example, the platinum film. When the orientation strength of the <222> plane of the lower electrode is increased, the film quality of the ferroelectric film formed thereon is also improved.

In the case where the lower electrode of the capacitor is composed of a platinum film, the platinum film is formed by the sputtering method at a temperature of 100 ° C or lower. Accordingly, when the aluminum wiring is connected to the capacitor lower electrode via the conductive base film, for example, the titanium nitride film, almost no reaction product of aluminum and platinum is formed in the contact portion.

EMBODIMENT OF THE INVENTION Below, the Example of this invention is described based on drawing.

2 to 5 are cross-sectional views illustrating a process of forming a semiconductor memory device according to an embodiment of the present invention.

First, the steps up to forming the cross-sectional structure shown in FIG. 2A will be described.

In Fig. 2A, the element isolation insulating film 2 is formed on the surface of the p-type silicon (semiconductor) substrate 1 by the LOCOS (Local Oxidation of Silicon) method. As the element isolation insulating film 2, a shallow trench isolation (STI) structure may be employed.

After the element isolation insulating film 2 is formed, p-type impurities and n-type impurities are selected and introduced into predetermined active regions (transistor formation regions) in the memory cell region A and the peripheral circuit region B of the silicon substrate 1. The p well 3a is formed in the active region of the memory cell region A, and the n well 3b is formed in the active region of the peripheral circuit region B.

In addition, a part of p well 3a is abbreviate | omitted in FIGS. In addition, since the CMOS is formed in the peripheral circuit region B, p wells (not shown) are also formed.

Thereafter, the surface of the silicon substrate 1 is thermally oxidized to form a silicon oxide film used as the gate insulating film 4 on the surfaces of the p wells 3a and n wells 3b.

Subsequently, a polycrystalline or amorphous silicon film and a tungsten silicide film are sequentially formed on the device isolation insulating film 2 and the gate insulating film 4. Then, the silicon film and the tungsten silicide film are patterned by a photolithography method to form the gate electrodes 5a and 5b on the p well 3a and the gate electrodes 5c on the n well 3b. do. In addition, one gate electrode 5b on the p well 3a is partially omitted.

In the memory cell region A, two gate electrodes 5a and 5b are formed on the p well 3a at substantially parallel intervals, and these gate electrodes 5a and 5b extend over the device isolation insulating film 2 to form a word. It becomes a line.

Subsequently, an n-type impurity is ion-implanted in both sides of the gate electrodes 5a and 5b in the p well 3a of the memory cell region A to be the source / drain of the n-channel MOS transistors T ₁ and T ₂ . 2 n-type impurity diffusion regions 7a and 7b and a third n-type impurity diffusion region (not shown) are formed. The second n-type impurity diffusion region 7b located at the center of the p well 3a is electrically connected to a bit line described later, and the first n-type impurity diffusion region 7a located at both sides of the p well 3a. And the third n-type impurity diffusion region (not shown) are electrically connected to a capacitor described later.

Subsequently, first and second p-type impurity diffusions are ion-implanted into both sides of the gate electrode 5c in the n well 3b of the peripheral circuit region B to become a p-channel MOS transistor T ₃ source / drain. The regions 8a and 8b are formed.

After that, an insulating film is formed over the silicon substrate 1, the element isolation insulating film 2, and the gate electrodes 5a, 5b, 5c. By etching back the insulating film, the sidewall insulating film 6 remains on both sides of the gate electrodes 5a to 5c. As the insulating film, for example, silicon oxide (SiO ₂ ) formed by the CVD method is used.

Further, the first and second n-type impurity diffusion regions 7a and 7b and the third n-type impurity diffusion region are formed by using the gate electrodes 5a and 5b and the sidewall insulating film 6 on the p well 3a as a mask. The n-type impurity diffusion region is made into the LDD structure by ion implantation of n-type impurity into the. Further, p-type impurity diffusion regions 8a and 8b are ion-implanted into the p-type impurity diffusion regions 8a and 8b using the gate electrode 5c and the sidewall insulating film 6 on the n well 3b as masks. 8b) is an LDD structure.

In addition, the above-mentioned separation of the n-type impurity and the p-type impurity is performed using a resist pattern (not shown).

Accordingly, formation of the first nMOS transistor T ₁ having the first and second n-type impurity diffusion regions 7a and 7b and the gate electrode 5a, and the second n-type impurity diffusion region 7b and the third n Formation of the second nMOS transistor T ₂ having the type impurity diffusion region and the gate electrode 5b ends, and the pMOS transistor having the first and second p-type impurity diffusion regions 8a and 8b and the gate electrode 5c. Formation of T ₃ ends.

Thereafter, a cover film 10 covering the nMOS transistors T ₁ , T _2, and pMOS transistor T ₃ is formed on the silicon substrate 1 by plasma CVD. As the cover film 10, for example, a silicon oxynitride (SiON) film is formed.

Subsequently, by a plasma CVD method using TEOS gas, a silicon oxide (SiO ₂ ) film is grown to a thickness of about 1.0 μm, and the silicon oxide film is used as the first interlayer insulating film 11.

Subsequently, as the densification treatment of the first interlayer insulating film 11, the first interlayer insulating film 11 is heat treated at a temperature of 650 ° C. for 30 minutes in a nitrogen atmosphere at normal pressure. Thereafter, the upper surface of the first interlayer insulating film 11 is polished and planarized by a chemical mechanical polishing (CMP) method.

Next, as shown in FIG. 2B, the titanium (Ti) film 12 is formed to a thickness of about 50 nm or less, for example, about 20 nm by sputtering on the first interlayer insulating film 11. . In the formation process of the Ti film 12, the silicon substrate 1 is controlled at a temperature of room temperature to 150 deg. Room temperature is 20 degreeC, for example.

Subsequently, the silicon substrate 1 is carried into the heating furnace. Then, the heating by the argon (Ar) gas into the (not shown) with the introduction in terms of 1980cc / min., 20cc / min oxygen (O ₂₎ gas. It is introduced under the condition of.

As shown in Fig. 3A, the RTA is subjected to a substrate temperature of 400 to 1000 ° C, for example, 700 ° C, an oxidation time of 10 to 120 seconds, for example, 20 seconds in an oxygen-containing atmosphere in a heating furnace. By Rapid Thermal Annealing, the entirety of the Ti film 12 is oxidized to form a titanium oxide (TiO _x ) film 12a. In addition, the inside of a heating furnace is normal pressure.

The titanium oxide film 12a formed under such conditions has a higher <200> plane orientation strength and a titanium oxide film constituting the titanium oxide film 12a compared with the titanium oxide film formed by introducing only oxygen into a heating furnace. The aspect ratio of the grains is also reduced, and the surface roughness is also reduced. The aspect ratio is the ratio of the height to the grain width. Details of the titanium oxide film will be described later.

The titanium oxide film 12a is an adhesion layer between the platinum film and the first interlayer insulating film 11 to be described later, or the base layer of the platinum film to be described later. As for an adhesion layer, several nm-50 nm are needed from the function.

Next, the process until forming the structure shown to Fig.3 (b) is demonstrated.

First, a platinum (Pt) film is formed as the first conductive film 13 on the titanium oxide film 12a. The Pt film is formed by the sputtering method while setting the substrate temperature to, for example, 100 ° C. or lower and 50 ° C. or higher. In this case, the thickness of the Pt film is set to about 100 to 300 nm, for example, about 150 nm. The <222> plane orientation intensity | strength of this Pt film | membrane became high depending on the <200> plane orientation intensity | strength of the titanium oxide film 12a, and surface roughness also became small. Details of the Pt film will be described later.

Thereafter, a lead zirconate titanate (PZT; Pb (Zr _1-x Ti _x ) O ₃ ) film having a thickness of 100 to 300 nm is formed as the ferroelectric film 14 on the first conductive film 13 by the RF sputtering method. The composition of Pb, Zr and Ti constituting the PZT film is, for example, in the range of Pb / (Zr + Ti) = 1.10 to 1.15.

The ferroelectric layer 14 may be formed by a metal organic deposition (MOD) method, an organic metal CVD (MOCVD) method, a sol gel method, or the like. As the material of the ferroelectric layer 14, in addition to PZT, other PZT materials such as PLCSZT and PLZT, SrBi ₂ Ta ₂ O ₉ (SBT, Y1), SrBi ₂ (Ta, Nb) ₂ O ₉ (SBTN, YZ) You may employ | adopt Bi layer structure compounds, such as), and another metal oxide ferroelectric.

Subsequently, RTA (Rapid Thermal Annealing) is performed under a condition of about 585 ° C. for about 90 seconds in an oxygen atmosphere as a crystallization treatment of the PZT film constituting the ferroelectric film 14.

Subsequently, an iridium oxide (IrOx) film is formed on the ferroelectric film 14 as the second conductive film 15 by a two-step reactive sputtering method. As a first step, an IrOx film is formed to a thickness of 25 to 100 nm. In this case, the gas introduced into the sputtering atmosphere contains argon gas at 100 cc / min. Oxygen (O ₂ ) gas to 30 to 60 cc / min. Shall be. Subsequently, RTA is performed on the IrO _x film under a condition of about 20 at a temperature of about 725 ° C. in an oxygen atmosphere. In addition, as a second step, an IrO _x film is further formed to a thickness of 100 to 225 nm. In this case, argon gas and oxygen gas introduced into a sputtering atmosphere are made into the same flow volume.

Next, the process until forming the composition shown in FIG.3 (c) is demonstrated.

First, a plurality of capacitor upper electrodes 15a are formed above the element isolation insulating film 2 in the memory cell region A by patterning the second conductive film 15. Subsequently, the ferroelectric film 14 is patterned to form the capacitor dielectric film 14a.

Thereafter, an alumina film is formed on the capacitor upper electrode 15a, the capacitor dielectric film 14a, and the first conductive film 13 as a capacitor protective insulating film 16 by sputtering to a thickness of about 20 to 50 nm. In addition to the alumina film, a PZT, a silicon nitride film, a silicon nitride oxide film, or the like may be used as the capacitor protective insulating film 16.

Subsequently, as shown in Fig. 4A, the capacitor protective insulating film 16, the first conductive film 13, and the titanium oxide film 12a are patterned using a resist mask (not shown). A stripe shape extends in the extending direction of the word line (gate electrode) below the capacitor upper electrode 15a. As a result, the capacitor lower electrode 13a formed of the first conductive film 13 is formed. The titanium oxide film 12a may also be considered to be part of the capacitor lower electrode 13a.

One capacitor Q is constituted by one capacitor upper electrode 15a, a capacitor dielectric film 14a and a capacitor lower electrode 13a below it.

Subsequently, as shown in FIG. 4B, the silicon oxide film is formed on the capacitor protective insulating film 16, the first interlayer insulating film 11, and the capacitor Q as the second interlayer insulating film 17 to a thickness of about 1 μm. Form. This silicon oxide film is formed by CVD using TEOS. Subsequently, the upper surface of the second interlayer insulating film 17 is planarized by the CMP method. In this example, the remaining film thickness of the second interlayer insulating film 17 after CMP is about 300 nm on the capacitor of the memory cell region A. FIG.

Next, the process until forming the structure shown to Fig.4 (c) is demonstrated.

First, by patterning the second interlayer insulating film 17, the first interlayer insulating film 11, and the cover film 10, the first and second contacts are respectively formed on the first and second n-type impurity diffusion regions 7a and 7b, respectively. While forming the holes 17a and 17b, the third and fourth contact holes 17c and 17d are formed on the first and second p-type impurity diffusion regions 8a and 8b, respectively.

The first contact hole 17a is formed over the n-type impurity diffusion region 7a formed near both sides of the p well 3a in the memory cell region A. In addition, the second contact hole 17b is formed on the second n-type impurity diffusion region 7b interposed between the two gate electrodes 5a and 5b at the center of the p well 3a.

Subsequently, a Ti film having a thickness of 20 nm and a TiN film having a thickness of 50 nm are sequentially formed by sputtering in the first to fourth contact holes 17 a to 17 d and on the second interlayer insulating film 17. A W film is formed on the TiN film by the CVD method. The W film is formed to a thickness that completely fills the first to fourth contact holes 17a to 17d.

Further, the Ti film, the TiN film and the W film are polished by the CMP method and removed from the upper surface of the second interlayer insulating film 17. Accordingly, the Ti film, the TiN film, and the W film left in the first to fourth contact holes 17a to 17d are used as the first to fourth conductive plugs 18a to 18d, respectively.

Thereafter, a silicon nitride film is formed as the antioxidant film 19 on the first to fourth conductive plugs 18a to 18d and the second interlayer insulating film 17.

Subsequently, as shown in FIG. 5A, the anti-oxidation film 19 and the second interlayer insulating film 17 are patterned, respectively, on the capacitor upper electrode 15a and the contact region of the capacitor lower electrode 13a, respectively. Fifth and sixth contact holes 19a and 19b are formed.

Subsequently, the crystallinity of the ferroelectric film 14 constituting the capacitor dielectric film 14a is restored by annealing at about 500 to 600 ° C. for 60 minutes in an oxygen atmosphere. In this case, the oxidation of tungsten constituting the first to fourth conductive plugs 18a to 18d is prevented by the antioxidant film 19. Thereafter, the antioxidant film 19 is removed by the etch back.

Next, a metal film is formed on the second interlayer insulating film 17 and on the first to fourth conductive plugs 18a to 18d. As the metal film, for example, a titanium nitride (TiN) film having a thickness of 150 nm, an aluminum film having a thickness of 500 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 100 nm are formed on the second interlayer insulating film 17. Form in order.

Subsequently, the metal film is patterned by the photolithography method to form the first to fourth aluminum wirings 20a to 20d and the conductive pads 20e as shown in Fig. 5B.

The first aluminum wiring 20a in the memory cell region A extends from the first conductive plug 18a into the fifth contact hole 19a to electrically connect the capacitor upper electrode 15a and the first conductive plug 18a. Connect. As a result, the capacitor upper electrode 15a is electrically connected to the first n-type impurity diffusion region 7a through the first aluminum wiring 20a and the first conductive plug 18a. In addition, the second aluminum wiring 20b in the memory cell region A is connected to the capacitor lower electrode 13a through the sixth contact hole 19b.

The third and fourth aluminum wirings 20c and 20d are electrically connected to the p-type impurity diffusion regions 8a and 8b through the third and fourth conductive plugs 18c and 18d of the peripheral circuit region B, respectively.

The conductive pad 20e in the memory cell region A is formed in an island shape on the second conductive plug 18b and electrically connected to a bit line (not shown) formed thereon. The conductive pad 20e and the second conductive plug 18b are formed to electrically connect the bit line and the second n-type impurity diffusion region 7b.

After the first to fourth wirings 20a to 20d and the conductive plugs 20e are formed, a third interlayer insulating film is further formed, a conductive plug is formed, and a bit line or the like is formed on the third interlayer insulating film. The details are omitted.

However, it has been clarified by experiment that the <200> plane orientation strength of the titanium oxide film 12a serving as the basis of the capacitor lower electrode 13a is different depending on the oxidation conditions of the Ti film 12.

First, a plurality of samples in which a titanium film was formed to a thickness of 20 nm was prepared on an insulating film made of silicon oxide formed on a silicon substrate, and the titanium film of these samples was oxidized under various conditions in a furnace at atmospheric pressure to form a titanium oxide film.

The first oxidation condition was a substrate temperature of 700 ° C., an oxygen (O ₂ ) gas flow rate of 20 cc / min., And an argon gas flow rate of 1980 cc / min. The oxidation time is 20 seconds. The second oxidation condition is a substrate temperature of 700 ° C., an oxygen (O ₂ ) gas flow rate of 1000 cc / min., And an argon gas flow rate of 1000 cc / min. The oxidation time is 20 seconds. The third oxidation condition is a substrate temperature of 700 ° C., an oxygen (O ₂ ) gas flow rate of 2000 cc / min., And an argon gas flow rate of 0 cc / min. The oxidation time is 20 seconds.

That is, in the first to third oxidation conditions, the total flow rate of the mixed gas of oxygen and argon was made constant, the oxygen flow rate ratio (oxygen concentration) in the mixed gas was changed, and the other oxidation conditions were made the same.

The oxygen flow rate ratio in the oxygen-argon mixed gas is 1% under the first oxidation condition, the oxygen flow rate ratio in the oxygen-argon mixed gas is 50% under the second oxidation condition, and the oxygen flow rate ratio is 100% under the third oxidation condition.

Then, the <200> orientation strength of the titanium oxide (TiO _x ) film formed under the first to third oxidation conditions was examined by XRD (X-ray diffractometer) method, and the result as shown in FIG. 6 was obtained.

6 shows the oxygen concentration or the oxygen flow rate in the oxidation process of the Ti film, and the vertical axis shows the half width of the XRD pattern of the <200> of the titanium oxide film and the integral strength of the XRD pattern of the <200> of the titanium oxide film. Doing.

According to FIG. 6, the difference in the oxygen concentration in the oxidation process does not show a large difference in the half-value width of <200>, and the <200> plane appears on each titanium oxide film formed under the first to third oxidation conditions. It can be seen that. However, according to FIG. 6, it became clear that the integration intensity | strength differs and the orientation intensity | strength of a <200> plane differs by the difference of oxygen concentration. That is, the lower the oxygen concentration, the stronger the <200> plane orientation. In addition, the integral strength of the titanium oxide film formed as the oxygen flow rate ratio 50% was twice or more the integral strength of the titanium oxide film formed as the oxygen flow rate ratio 100%. Therefore, the oxygen flow rate ratio in the oxidizing atmosphere of the titanium film is 50% or less, preferably 1% or less. If it is an oxygen flow rate ratio of 1% or less, it may be a trace amount and may be larger than 0%.

7 shows the state of the grain G of the titanium oxide film formed under the oxidation condition having an oxygen flow rate ratio of 1%. In addition, the state of the grain G of the titanium oxide film formed on the oxidation conditions of 100% of oxygen flow ratio is shown as FIG.

7 and 8, when comparing the relationship between the bottom width a and the height b of the grain G of the titanium oxide film, the size of the grains (particles) G of the titanium oxide formed under oxidation conditions of 1% oxygen flow rate ratio is a> b. The grain G of titanium oxide formed on the oxidation conditions of 100% of oxygen flow ratio becomes a <b. That is, the grain G of the titanium oxide film formed under the oxidation condition having an oxygen flow rate ratio of 1% is relatively large in size compared with the grain G of the titanium oxide film formed under the oxidation condition having an oxygen flow rate ratio 100%. In addition, the surface of the titanium oxide film formed under the oxidation condition having an oxygen flow rate ratio of 100% is rougher than the surface of the titanium oxide film formed under the oxidation condition having an oxygen flow rate ratio 1%. As the surface of the titanium oxide film becomes flat, the flatness of the metal film thereon also improves.

7 and 8 are shown based on photographs taken with a scanning electron microscope (SEM), respectively.

Subsequently, a platinum film was formed on the titanium oxide film formed by oxidizing the titanium film under oxidation conditions of 1% oxygen flow rate. Further, a platinum film was formed on the titanium oxide film formed by oxidizing the titanium film under oxidation conditions of 100% oxygen flow rate. And the <222> plane orientation intensity | strength of each platinum film was investigated by XRD method, and the result as shown in FIG. 9 was obtained. In other words, the integral intensity of the XRD pattern of the platinum film on the titanium oxide film formed under the oxidation condition of 1% oxygen flow rate ratio was 910000 cps. On the other hand, the integral intensity of the XRD pattern of the platinum film on the titanium oxide film formed under the oxidation condition of 100% oxygen flow rate ratio was 340000 cps. The <222> plane is also represented by the (111) plane.

Therefore, according to Figs. 6 and 9, it can be seen that the <222> plane orientation strength of the platinum film increases depending on the <200> plane orientation strength of the titanium oxide film thereunder.

Subsequently, experiments were made on how the growth temperature of the platinum film constituting the capacitor lower electrode influences the defective rate of FeRAM, and the results as shown in FIG. 10 were obtained.

The defective rate is that after writing data to a plurality of capacitors in the FeRAM, the FeRAM is heated under the condition of 150 ° C for 4 hours, and then the data of the plurality of capacitors in the FeRAM is read under an environment of, for example, 85 ° C, and the inside of the FeRAM The ratio of the data reading failure which the some capacitors generate | occur | produces is shown. The dielectric film of the capacitor is made of PZT, and the upper electrode is made of iridium oxide.

Accordingly, the first to third FeRAMs having a plurality of capacitors composed of the lower electrodes of platinum formed at 100 ° C are compared with the fourth to sixth FeRAMs having a plurality of capacitors composed of the lower electrodes of platinum formed at 550 ° C. As a result, it was found that the defective rate was significantly lowered.

Therefore, it was found that by forming the platinum film serving as the capacitor lower electrode at a low temperature, FeRAM having a low defective rate and a good yield can be formed. As for the growth temperature of a platinum film, 50 to 50 degreeC is preferable at 100 degrees C or less.

One of the factors that reduce the device failure rate by forming the platinum film at low temperature is a reaction of the lower electrode and the aluminum wiring.

FIG. 11 is a plan view of the monitor capacitor viewed from above, and the upper electrode 32 is formed on the lower electrode 31 made of platinum formed on the interlayer insulating film 30 via a PZT film (not shown). The lower electrode 31 has a contact region protruding in the horizontal direction from the upper electrode 32. In addition, the lower electrode 31 and the upper electrode 32 are covered with an insulating film (not shown). The first aluminum wiring 33 is connected to the upper electrode 32 via the first contact hole 34, and the first aluminum wiring 33 is electrically connected to the first monitor pad 35. In addition, the second aluminum wiring 37 is connected to the contact region of the lower electrode 31 through the second contact hole 36, and the second aluminum wiring 37 is electrically connected to the second monitor pad 38. Connected. The first and second aluminum wirings 33 and 37 have a three-layer structure in which an aluminum film is sandwiched from above and below a titanium nitride film. The titanium oxide film (not shown) is formed between the lower electrode 31 and the interlayer insulating film 30.

A capacitor having a lower electrode 31 composed of platinum formed at a film formation temperature (substrate temperature) 550 ° C. by sputtering is referred to as Q ₁ . Further, a capacitor having a lower electrode 31 composed of a platinum formed on the film forming temperature is 100 ℃ by sputtering to Q _2.

Then, the capacitor Q ₁ was heated at 370 ° C. for 0.5 hour and then observed from above with a microscope. As shown in FIG. 12A, the contact between the lower electrode 31 and the second aluminum wiring 37 was observed. The area is discolored. In contrast, when the capacitor Q ₂ was heated at 370 ° C. for 0.5 hour and observed from above under a microscope, as shown in FIG. 12B, the lower electrode 31 and the second aluminum wiring 37 were formed. ) Showed no change from the initial state.

In the capacitor Q ₁ in which the lower electrode 31 is formed of platinum formed at 550 ° C., the aluminum film reacts with the lower electrode 31 through the titanium nitride film constituting the lower layer of the aluminum wiring 37 so that the color of the contact region is reduced. It seems to have changed.

Therefore, after heating the capacitor having the lower electrode of platinum formed at the film forming temperature of 550 ° C. at about 370 ° C., the cross section of the contact portion between the lower electrode and the aluminum wiring was examined, as shown in FIG. 13.

In FIG. 13, the lower electrode 41 of the capacitor is formed on the first insulating film 40 made of silicon oxide, and the second insulating film 42 made of silicon oxide is formed on the lower electrode 41 and the first insulating film 40. The contact hole 43 is formed on the contact region of the lower electrode 41 of the second insulating film 42. A titanium oxide film 44 formed by oxidizing the titanium film in a mixed gas atmosphere of argon and oxygen is formed between the lower electrode 41 and the first insulating film 40. Further, in the contact hole 43 and on the second insulating film 42, an aluminum wiring 46 having a structure in which an aluminum film 46a is interposed between the titanium nitride films (conductive base films: 46b and 46c) is formed. The aluminum wiring 46 is connected to the lower electrode 41 via the contact hole 43. In the bottom portion of the contact hole 43, the film thickness of the lower titanium nitride film 46b constituting the aluminum wiring 46 is about 150 nm.

At the bottom of such a contact hole 43, the aluminum film 46a reacted with the lower electrode 41 through the titanium nitride film 46b to form a reaction product 47 of aluminum and platinum. When the volume of the reaction product 47 increases, there is a fear that the second insulating film 42 floats around the contact region of the lower electrode 41 and the lower electrode 41 and the aluminum wiring 46 may become poor in contact.

On the other hand, the cross section of the contact part of the lower electrode 41a and the aluminum wiring 46 after heating the capacitor which has the lower electrode 41a of platinum formed at film-forming temperature (substrate temperature) 100 degreeC at 370 degreeC was investigated. The bar is as shown in FIG. In Fig. 14, no reaction product is formed between the aluminum wiring 46 and the lower electrode 41a. In addition, in FIG. 14, the same code | symbol as FIG. 13 has shown the same element.

By the way, the platinum film is formed by lowering the film formation temperature, so that the hydrogen catalyst effect of the platinum film is reduced. Therefore, the ferroelectric capacitor having a lower electrode made of platinum formed at a low film forming temperature, for example, 100 ° C. or less, is suppressed from deterioration due to the reducing action, and the defective rate of the device is reduced.

In the above embodiment, the capacitor lower electrode 13a is made of platinum, but may be made of iridium. The orientation strength of the <222> plane of this iridium also depends on the orientation strength of the <200> plane of the titanium oxide 12a similarly to platinum. In addition, although argon was introduce | transduced in the atmosphere which oxidizes a titanium film in the said Example, you may introduce nitrogen, helium, neon, and any other inert gas.

(Supplementary Note 1) A first insulating film formed above the semiconductor substrate;

An adhesion layer formed on the first insulating film, the adhesion layer comprising grained titanium oxide having a width greater than that of the height;

A capacitor lower electrode including a noble metal formed on the adhesion layer;

A capacitor dielectric film made of a ferroelectric material formed on the capacitor lower electrode;

A capacitor upper electrode formed on the capacitor dielectric layer

It has a semiconductor device characterized by the above-mentioned.

(Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the adhesion layer has a thickness of 50 nm or less.

(Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein the first insulating film is a silicon oxide film.

(Supplementary Note 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the precious metal is either platinum or iridium.

(Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the ferroelectric material is any one of a PZT-based, SBT, and Bi-based layered compound.

(Supplementary Note 6) a second insulating film covering the capacitor upper electrode, the capacitor dielectric film, and the capacitor lower electrode;

A contact hole formed on the capacitor lower electrode in the second insulating layer;

Aluminum-containing wiring formed on the second insulating film and connected to the capacitor lower electrode through the contact hole.

The semiconductor device according to any one of Supplementary Notes 1 to 5, further comprising:

(Supplementary Note 7) an impurity diffusion region formed in the surface layer of the semiconductor substrate;

A conductive plug formed in the second insulating film under the aluminum wiring and in the hole to electrically connect the aluminum wiring and the impurity diffusion region;

The semiconductor device according to Appendix 6, further comprising:

(Supplementary Note 8) forming a first insulating film above the semiconductor substrate;

Forming a titanium film on the first insulating film;

Oxidizing the titanium film to form a titanium oxide film in an atmosphere introduced at an oxygen gas flow rate of 50% or less;

Forming a first conductive film made of a noble metal on the titanium oxide film;

Forming a ferroelectric film on the first conductive film;

Forming a second conductive film on the ferroelectric film;

Forming an upper electrode of the capacitor by patterning the second conductive film;

Forming a dielectric film of the capacitor by patterning the ferroelectric film;

Forming a lower electrode of the capacitor by patterning the first conductive layer

Method for manufacturing a semiconductor device comprising a.

(Supplementary Note 9) The method for manufacturing a semiconductor device according to Supplementary Note 8, wherein the oxygen gas flow rate ratio is introduced into the atmosphere at 1% or less.

(Supplementary Note 10) The method for manufacturing a semiconductor device according to Supplementary Note 8 or 9, wherein an inert gas is introduced into the atmosphere in addition to the oxygen.

(Supplementary Note 11) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 8 to 10, wherein the formation of the noble metal constituting the first conductive film forms a platinum film at a temperature of 100 ° C or lower.

(Supplementary Note 12) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 8 to 11, wherein the formation of the first insulating film is a step of forming a silicon oxide film using TEOS.

(Supplementary Note 13) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 8 to 12, wherein the ferroelectric film is composed of any one of PZT-based, SBT, and Bi-based layered compounds.

(Supplementary Note 14) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 8 to 13, wherein the titanium oxide film is patterned to form the same planar shape as the lower electrode.

(Supplementary Note 15) forming a second insulating film on the first insulating film and on the capacitor;

Patterning the second insulating film to form a hole in a region protruding from the upper electrode in the lower electrode;

Forming an aluminum-containing wiring on the second insulating film that is connected to the lower electrode through the hole;

The method of manufacturing a semiconductor device according to any one of Supplementary Notes 8 to 14, further comprising.

(Supplementary Note 16) The method of manufacturing the semiconductor device according to Supplementary note 15, further comprising the step of forming a capacitor protective film covering the capacitor before forming the second insulating film.

As described above, according to the present invention, an adhesion layer made of titanium oxide having a grain size larger than the height is formed between the lower electrode made of the noble metal constituting the capacitor and the insulating film. The orientation strength can be increased, the flatness can be improved, and the flatness of the lower electrode formed on the adhesion layer can also be improved, so that the contact between the lower electrode and the wiring can be improved.

In addition, the higher the <200> plane orientation strength of the adhesion layer, the higher the <222> plane orientation strength of the lower electrode metal film formed thereon, so that the film quality of the ferroelectric film formed on the lower electrode can be improved.

In the case where the capacitor lower electrode is composed of a platinum film, when the platinum film is formed by the sputtering method at a temperature of 100 ° C. or lower, the aluminum film formed on the capacitor lower electrode via the conductive base film has good contact with the capacitor lower electrode. Become.

Claims (7)

A first insulating film formed above the semiconductor substrate, An adhesion layer formed on the first insulating film and composed of grained titanium oxide having a width greater than that of height; A capacitor lower electrode including a noble metal formed on the adhesion layer; A capacitor dielectric film made of a ferroelectric material formed on the capacitor lower electrode; A capacitor upper electrode formed on the capacitor dielectric layer A semiconductor device comprising a. The method of claim 1, The film thickness of the adhesion layer is 50 nm or less. The method according to claim 1 or 2, A second insulating film covering the capacitor upper electrode, the capacitor dielectric layer, and the capacitor lower electrode; A contact hole formed on the capacitor lower electrode in the second insulating layer; Aluminum-containing wiring formed on the second insulating film and connected to the capacitor lower electrode through the contact hole. A semiconductor device comprising a. Forming a first insulating film above the semiconductor substrate; Forming a titanium film on the first insulating film; Oxidizing the titanium film to form a titanium oxide film in an atmosphere introduced at an oxygen gas flow rate of 50% or less; Forming a first conductive film made of a noble metal on the titanium oxide film; Forming a ferroelectric film on the first conductive film; Forming a second conductive film on the ferroelectric film; Forming an upper electrode of the capacitor by patterning the second conductive film; Forming a dielectric film of the capacitor by patterning the dielectric film; Forming a lower electrode of the capacitor by patterning the first conductive layer Method for manufacturing a semiconductor device comprising a. The method of claim 4, wherein The oxygen gas flow rate ratio is introduced to the atmosphere at 1% or less, the manufacturing method of a semiconductor device. The method according to claim 4 or 5, An inert gas other than the oxygen is introduced into the atmosphere, wherein the semiconductor device is produced. The method according to any one of claims 4 to 6, The formation of the noble metal constituting the first conductive film forms a platinum film at a temperature of 100 ° C. or less.