KR20030088763A - CMOS transistor using channel junctions and logic circuit using the same - Google Patents

Abstract

PURPOSE: A CMOS transistor is provided to be capable of reducing the size of circuits and improving operation speed by using a channel junction instead of a floating node. CONSTITUTION: A semiconductor substrate(10) includes the first and second region(20,30). A P-well(40) is formed at the first region(20) of the substrate. The first junction region(50) is formed in the P-well(40) for fetching the first electrode(110). The second junction region(60) is formed in the second region(30) for fetching the second electrode(120). The first gate oxide layer(70) and the first gate electrode(80) are stacked on the first region(20) to partially overlap the first junction region. The second gate oxide layer(90) and the second gate electrode(100) are stacked on the second region(30) to partially overlap the second junction region. The first channel is formed at a lower of the first gate electrode(80) and the second channel is formed at a lower of the second gate electrode(100), thereby forming a PN junction.

Description

CMOS transistor using channel junctions and logic circuit using the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to CMOS transistors using channel junctions, and more particularly to CMOS transistors having dual gates as one transistor.

The high operating speed for dual gates is achieved by implementing low capacitance. This is made possible by allowing two transistors to share a well structure called a floating node. The CMOS dual gate uses a P-type gate as the gate of the PMOS transistor to enable a short channel effect, I-V characteristics, and a surface channel to easily adjust the threshold voltage. The dual gate is complicated in its process, and the two transistors basically use a large area of the circuit, and the circuit line width is further reduced, causing many problems.

CMOS transistors consist of one PMOS transistor and one NMOS transistor. Two CMOS transistors can be connected in series to form a NAND gate (four transistors used). In addition, two CMOS transistors can be connected in parallel to form a NOR gate (four transistors used). These NOR or NAND gates can be combined to form more complex logic circuits. These CMOS transistors have low power dissipation, higher noise immunity, ratioless logic and higher speed, despite the complexity of the manufacturing process and the large area requirements. It is dominant because of its operation.

However, as mentioned above, CMOS transistors do not overcome the disadvantages of complicated manufacturing process and large circuit area.

Therefore, in the present invention, a channel junction capable of high-speed operation while reducing circuit area by implementing dual gate in one transistor by replacing a floating node between two transistors with a gate voltage induced PN junction in a conventional dual gate is disclosed. The purpose is to provide a CMOS transistor used.

Another object of the present invention is to provide a CMOS transistor which can make the configuration of a logic circuit simpler, more economical, and more stable.

1A is a cross-sectional view illustrating the structure of a CMOS transistor according to the present invention.

1B is a cross-sectional view for explaining a capacitor characteristic of a CMOS transistor according to the present invention;

1C is a symbol of a CMOS transistor in accordance with the present invention.

Figure 2a is a NAND logic circuit diagram using the CMOS transistor of the present invention.

2B is a symbol of FIG. 2A;

3A is a NOR logic circuit diagram using CMOS transistors of the present invention.

3B is a symbol of FIG. 3B.

<Description of reference numerals for main parts of the drawings>

10: N-type semiconductor substrate 20: first region (NMOS region: 20)

30: second region (PMOS region: 30) 40: P well

50: n + junction region 50 60: p + region 60

70: first insulating film 70, 80: first gate electrode

90: second insulating film 100: second gate electrode

110: first electrode 120: second electrode

Sea MOS transistor according to the present invention for achieving the above object is

A semiconductor substrate having first and second regions;

A well region formed in a first region of the semiconductor substrate;

A first junction region formed in the well and having a first electrode drawn therethrough;

A second junction region formed in the second region of the semiconductor substrate and from which the second electrode is drawn out;

A first gate oxide layer and a first gate electrode stacked on the semiconductor substrate in the first region where the well is formed so as to overlap a portion of the first junction region;

A second channel oxide layer and a second gate electrode stacked on the semiconductor substrate in the second region so as to overlap a portion of the second junction region, and a first channel is formed in the semiconductor substrate below the first gate electrode. A second channel is formed in the semiconductor substrate below the second gate electrode, whereby a PN junction is formed by the first and second channels.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1A is a cross-sectional view of a CMOS transistor according to a first embodiment of the present invention, and FIG. 1B is a symbol thereof.

Referring to FIG. 1A, an N-type semiconductor substrate 10 is provided. The N-type semiconductor substrate 10 is divided into a first region (NMOS region: 20) and a second region (PMOS region: 30). P wells 40 are formed in the first region 20. An n + junction region 50 is formed in the P well 40, and a p + region 60 is formed in the semiconductor substrate 10 of the second region 30. A first insulating layer 70 such as a gate oxide overlapping a portion of the n + junction region 50 is formed on the P well 40, and a first gate electrode 80 is formed on the first insulating layer 70. . A second insulating film 90 such as a gate oxide overlapping a portion of the p + junction region 60 is formed on the semiconductor substrate 10 of the second region 30, and a second gate is formed on the second insulating film 90. The electrode 100 is formed. The first electrode 110 is drawn from the n + junction region 50 and the second electrode 120 is drawn out from the p + junction region 60, respectively.

In this transistor configuration, as shown in FIG. 1A, a gate line is separated to form a half structure of an NMOS transistor at one gate, and a half structure of a PMOS transistor is formed at another gate and a single transistor is formed by combining them. .

In the manufacture of such a transistor, a manufacturing process applied to an NMOS transistor and a PMOS transistor currently used, and a process applied to a dual gate process may be equally applied. Further, such a transistor may be formed in accordance with the purpose by combining a normal MOS transistor, a depletion MOS transistor, a native MOS transistor, a triple well MOS transistor, or the like. FIG. 1A shows a state in which a normal NMOS transistor and a native PMOS transistor are combined as an example.

The basic operating principle of the transistor having the structure of FIG. 1A will be described.

The basic principle of the NMOS transistor is that when a voltage higher than the threshold voltage is applied to the gate, an N-type channel is induced in the P-well (or P-type substrate) portion below the gate oxide, and when the proper bias is applied to the source and drain, the induced N Transistors with current flowing through the channel become active. On the other hand, the PMOS transistor operates by applying a voltage lower than the threshold voltage to the gate to induce a P-type channel under the gate oxide layer.

Likewise, the transistor shown in FIG. 1 operates by simultaneously applying the operating conditions of the NMOS and PMOS transistors. A high voltage Vg1 higher than the threshold voltage is applied to the first gate electrode 80 on the NMOS side to form an N-type channel Ln, while a voltage Vg2 lower than the threshold voltage is applied to the second gate on the PMOS side. To form a P channel (Lp). The N-type channel and the P-string channel are in contact with each other to form a PN junction. When forward bias is applied to these PN junctions, the transistors are activated. That is, when a low voltage is applied to the first electrode 110 (Vn) and a high voltage is applied to the second electrode 120 (Vp), current flows from the PMOS side to the NMOS side, thereby operating the transistor. When the low voltage is represented by L and the high voltage is represented by H, the operation of the transistor proposed in the present invention is shown in Table 1 below.

Vg1 (NMOS) Vg2 (PMOS) transistor L L OFF L H OFF H L ON H H OFF

1B is a cross-sectional view illustrating a capacitance of a transistor according to the present invention.

The capacitance of the transistor according to the present invention is reduced compared to a dual gate device or a CMOS transistor for the following reasons.

1. A conventional dual gate device or CMOS transistor basically uses two transistors. However, since the present invention makes these two transistors one, it can be seen that the floating area is reduced by half, so that the floating capacitance is reduced accordingly.

2. As can be seen in FIG. 1B, the transistor of the present invention is divided into two floating regions, and the two capacitances are connected in series with respect to the applied signal, thereby reducing the total capacitance.

3. Capacitors formed between PN junctions have a very small channel width when using surface channels, so the capacitance is considered to be very small compared to the gate-oxide-side floating capacitors, and the overall circuit operation is insignificant.

4. If two transistors are used, all four bias wells are needed, whereas only one transistor CMOS requires two.

2A shows a NAND logic circuit using the transistor of the present invention, and FIG. 2B shows its symbol.

In FIG. 2A, a depletion PMOS transistor is used as an active load. This is to maintain the advantages of the CMOS logic circuit by allowing the high voltage to be output through the PMOS and the low voltage through the MOS transistor proposed in the present invention, as in CMOS logic circuits. When the signal to be compared is X and Y, the composition of output signal is as follows.

Vout = X + / Y = / (/ XY) → NAND (/ X, Y)

Only when (X, Y) = (0,1) the transistor is turned on, so only in this case the output goes low and the rest are high signals. The reason why the output signal goes low when (X, Y) = (0,1) is the following two reasons.

1. The current of the PMOS transistor, which is an active load, is due to electromagnetism. Since the transistor proposed in the present invention is a PN junction, the current is caused by electrons. Since the electron mobility is twice that of the field, more current will flow in the NPMOS transistor than in the PMOS transistor. In other words, the internal resistance of the NPMOS transistor is smaller than that of the PMOS transistor.

2. Since the load ratio of the active load PMOS transistor can be adjusted, a larger resistance is applied to the PMOS transistor side, so that the desired output can be made low voltage.

3A shows a NOR logic circuit using the transistor of the present invention, and FIG. 3B shows its symbol.

As in the NAND logic circuit of FIG. 2A, the high signal is output through the PMOS transistor and the low signal is output through the NMOS transistor or the transistor of the present invention, thereby maintaining the characteristics of the CMOS transistor logic circuit. The configuration of the output signal is as follows.

Vout = / (X + Y) → NOR (X, Y)

By using the conventional CMOS inverter circuit (or other inverter circuit) and the above-described NAND and NOR logic circuits, all logic circuit structures can be realized.

According to the present invention, the N-type and P-type channels formed when the NMOS and the PMOS are operated are formed in one transistor and operated through a PN junction to perform the same operation as the conventional CMOS or dual gate devices. By implementing the conventional CMOS, which consists of NMOS and PMOS, in one transistor, the circuit area is greatly reduced while maintaining the advantages of CMOS. In addition, the operating speed of the circuit is improved by reducing capacitance compared to CMOS or dual gate devices.

Moreover, the simple configuration of NOR or NAND logic circuits significantly reduces circuit area and contributes significantly to debugging.

Claims (7)

Semiconductor substrate having first and second regions A well region formed in a first region of the semiconductor substrate; A first junction region formed in the well and having a first electrode drawn therethrough; A second junction region formed in the second region of the semiconductor substrate and from which the second electrode is drawn out; A first gate oxide layer and a first gate electrode stacked on the semiconductor substrate in the first region where the well is formed so as to overlap a portion of the first junction region; A second channel oxide layer and a second gate electrode stacked on the semiconductor substrate in the second region so as to overlap a portion of the second junction region, and a first channel is formed in the semiconductor substrate below the first gate electrode. And a second channel is formed in the semiconductor substrate under the second gate electrode so that the PN junction is formed by the first and second channels. The method of claim 1, And the semiconductor substrate and the well are P-type, wherein the first junction region is N-type while the second junction region is P-type. The method of claim 1, And the semiconductor substrate is N-type, the well is P-type, the first junction region is N-type, and the second junction region is P-type. The method of claim 1, And the voltage supplied to the first electrode is lower than the voltage supplied to the second electrode. A CMOS transistor having the structure of claim 1 and having a first electrode grounded; A negative logic multiplication signal comprising a load connected between a second electrode of the CMOS transistor and a power supply to perform a negative logic multiplication on the negative signal of the first signal input to the first gate of the CMOS transistor and the second signal input to the second gate. Outputting through the second electrode. The method of claim 5, And said load comprises a depletion type PMOS transistor. A CMOS transistor having the structure of claim 1 and having a first electrode grounded; An NMOS transistor connected in parallel to the first and second electrodes of the CMOS transistor; A first signal connected between a second electrode of the CMOS transistor and a power supply and having a gate electrode connected to a gate terminal of the NMOS transistor, the first signal being input to the first gate electrode of the CMOS transistor and the PMOS transistor; And a negative logic sum of the second signal input to the second gate electrode of the CMOS transistor.