KR20030083446A - Method of making dual damascene for semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a dual damascene structure of a semiconductor device is provided to be capable of minimizing the thickness of a photoresist and the generation of metallic polymer. CONSTITUTION: A diffusion barrier layer(104), a low-permittivity interlayer dielectric(106"), a metal hard mask are sequentially formed on a substrate(100) having a lower metal line(102). The metal hard mask is selectively etched using the first photoresist pattern. A tungsten hard mask is then deposited to expose the metal hard mask pattern. Then, a metal interconnection region is patterned. An oxide hard mask(116) is formed to expose the tungsten hard mask pattern. After removing the tungsten hard mask pattern, a via hole is formed by patterning the exposed interlayer dielectric(106"). After removing the metal hard mask pattern, a trench is formed by selectively etching the interlayer dielectric(106").

Description

Dual damascene etching method of semiconductor device {METHOD OF MAKING DUAL DAMASCENE FOR SEMICONDUCTOR DEVICE}

The present invention relates to a method for forming dual damascene etching of a semiconductor device. In particular, the thickness of the photo-resist film is greatly reduced compared to the conventional process method to facilitate fine patterning and to accurately adjust critical damascene. A dual damascene etching method of a semiconductor device that can be.

In general, metal wiring is formed in two ways.

The first method is a method of forming a photoresist pattern on a metal film, and then directly etching the metal film by a plasma etching process using the photoresist pattern as an etching barrier to form a metal wiring in a desired form. However, this method has a problem that it is very difficult to secure the electrical characteristics in the trend that the critical dimension of the metal wiring is reduced.

The second method is a method using a damascene process. First, a portion of the first interlayer insulating layer is etched and removed to form a contact hole, and then a metal film is embedded in the contact hole to form a metal plug. After forming a second interlayer insulating film on the resultant, the second interlayer insulating film is etched to expose the metal plug, and a spacing pattern having a line shape is formed. Then, the spacing pattern is formed. A metal film is embedded in the metal film to form a metal wiring in contact with the metal plug. This method is able to obtain relatively superior electrical characteristics than the former method, and at the same time, the use of the method is gradually expanded because of less process cost.

1A to 1D are cross-sectional views illustrating a method for forming dual damascene etching of a semiconductor device according to the related art.

First, as illustrated in FIG. 1A, a diffusion barrier 14 and a low-k dielectric material are formed on a semiconductor substrate 10 on which a lower metal wiring (Sub-Metal) 12 is formed in a damascene manner. After the deposition of one interlayer insulating layer (IMD-1) 16 and the stopping layer 18, a predetermined via hole is formed only in the stopping layer 18 ′.

Next, as shown in FIGS. 1B to 1C, after the low dielectric constant (Low-k) second interlayer insulating film (IMD-2) 20 is deposited thereon, the photoresist film 22 is sufficiently thick coated. Let's do it. After etching the patterned area 24a corresponding to the upper-metal-wiring of the coated photoresist layer 22 by etching, the dual damascene composed of via holes 24b and upper metal wirings is etched. The pattern 24c can be obtained.

This process method has the advantage of easy patterning of the photoresist layer and easy adjustment of trench depth and profile. However, in most cases, since the dielectric constant of the material used as the stopping layer 18 is high, the dielectric constant and capacitance of the entire interlayer insulating film (IMD) become large, resulting in low dielectric constant (Low). k) The advantage of using the material as an interlayer insulating film (IMD) is eliminated. In addition, since the entire interlayer insulating film must be etched only with the photoresist patterned with respect to the upper metal wiring, the etching selectivity of the interlayer insulating film (IMD) material to the photosensitive film must be considerably large, or the photoresist having a very high thickness must be patterned. This problem makes it difficult to implement a fine pattern, and also becomes a factor of inaccurate critical dimension of the pattern.

2A to 2D are cross-sectional views illustrating another dual damascene etching method of a semiconductor device according to the related art for solving such a problem.

First, as shown in FIGS. 2A to 2B, the diffusion barrier layer 34 and the low-k first interlayer insulating layer 34 are formed on the semiconductor substrate 30 on which the lower metal wires 32 are formed in a damascene manner. IMD 36) is deposited. The photoresist film 38 is sufficiently thickly coated thereon and the via holes 40a are patterned, followed by plasma dry etching to form the via holes 40b.

Next, as shown in FIGS. 2C to 2D, after the photoresist layer 42 is coated on the first interlayer insulating layer 36 ′, the region corresponding to the upper metal wiring is patterned 44a in a negative manner, followed by etching. Proceeding, a dual damascene pattern 44b consisting of via holes and upper metal wirings can be obtained.

This method is relatively simple and does not cause a problem of increasing the dielectric constant of the entire interlayer insulating film (IMD) due to the stopping layer. However, since the via hole needs to be deeply etched, the patterned photoresist may have a sufficiently high thickness or a sufficiently high etch selectivity of the interlayer dielectric (IMD) material to the photoresist in the etching process. In addition, the photoresist remaining inside the via hole formed in the trench mask patterning process may not be removed well, and a micro-trench phenomenon generated in the trench etching process may also make the process difficult.

3A to 3D are cross-sectional views illustrating another method for forming dual damascene etching of a semiconductor device according to the related art to solve such a problem.

First, as shown in FIGS. 3A to 3B, the diffusion barrier layer 54 and the low dielectric constant (Low-k) first interlayer on the semiconductor substrate 50 on which the lower metal wiring 52 is formed by the dual damascene method. An insulating film 56, a stopping layer 58, and a low dielectric constant (Low-k) second interlayer insulating film 60 are deposited. The photoresist film 62 is applied thereon, and the upper metal wiring region is negatively patterned 63a, followed by plasma dry etching to form the trench 63b.

Next, as shown in FIGS. 3C to 3D, after the photoresist 64 is applied again, the via holes are intaglio patterned 63c and then etched, thereby performing dual damascene with the via holes and the upper metal wiring. The pattern 63d can be obtained. This approach has the advantage that the trench and via hole depth and profile can be easily adjusted.

However, when the via mask is patterned, it is difficult to accurately control the size of the via hole, and the dielectric constant of the entire interlayer insulating layer due to the stopping layer is increased.

Accordingly, the present invention has been made to solve the above problems, and the present invention is to deposit a diffusion barrier, low dielectric constant (Low-k) interlayer insulating film (IMD) on the pre-formed lower-metal wiring in a damascene manner, and then an oxide film thereon. After making a composite hard mask composed of a hard mask (Oxide-Hard-Mask) and a double metal hard mask (Metal-Hard-Mask), by selectively etching using two different types of plasma, the internal connection metal ( An object of the present invention is to provide a dual damascene etching method of a semiconductor device capable of forming interconect metals).

In addition, an object of the present invention is to provide a dual damascene etching method of a semiconductor device that can easily implement a fine patterning compared to the conventional process method by minimizing the thickness of the photosensitive film.

Another object of the present invention is to provide a dual damascene etching method of a semiconductor device capable of minimizing the generation of a metallic polymer.

1A to 1D are cross-sectional views illustrating a method for forming dual damascene etching of a semiconductor device according to the related art.

2A to 2D are cross-sectional views illustrating another dual damascene etching method of a semiconductor device according to the related art.

3A to 3D are cross-sectional views illustrating another dual damascene etching method of a semiconductor device according to the related art.

4A to 4J are cross-sectional views illustrating a method for forming dual damascene etching of a semiconductor device according to the present invention.

(Explanation of symbols for the main parts of the drawing)

100 semiconductor substrate 102 lower metal wiring

104: diffusion barrier 106: low dielectric constant interlayer insulating film

108: metal hard mask 110: photosensitive film

112: tungsten hard mask 114: photosensitive film

116: oxide hard mask

Dual damascene etching method of the semiconductor device according to the present invention for achieving the above object,

Sequentially forming a diffusion barrier film, a low dielectric constant interlayer insulating film, and a metal hard mask on the semiconductor substrate on which the lower metal wiring is formed by a damascene process;

Applying a first photoresist film on the metal hard mask and patterning the first photoresist film in a region where a via hole is to be formed;

First etching only the metal hard mask by the patterned first photoresist;

Depositing a thin layer of tungsten hard mask on the resultant and then planarizing it by a chemical mechanical polishing process to expose the metal hard mask to the outside;

Patterning the upper metal wiring region after applying a thin layer of the second photosensitive film on the resultant,

Second etching only the metal hard mask of the remaining portion except for the upper metal wiring region;

After depositing a thin film of an oxide hard mask on the resultant, planarization using a chemical mechanical polishing process to expose the metal hard mask to the outside;

Exposing only the tungsten hard mask to the outside by exposing the interlayer dielectric layer in a region corresponding to the via hole region to the outside;

Etching the interlayer dielectric layer to form a via hole;

Etching and removing only the metal hard mask by a fifth etch;

And etching the interlayer insulating layer to form a via hole and an upper metal wiring trench simultaneously.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

4A to 4J are cross-sectional views illustrating a method for forming dual damascene etching of a semiconductor device according to the present invention.

First, referring to FIG. 4A, a diffusion barrier layer 104, a low dielectric constant (Low-k) interlayer dielectric layer (IMD) 106, are formed on a semiconductor substrate 100 on which a lower metal line (Sub-Metal-Line) 102 is formed. A metal hard mask 108 is deposited. At this time, the metal hard mask 108 is selected as a material (eg, Ti, TiN, Ta, TaN, etc.) that is well etched by the plasma activated Cl ₂ + BCl ₃ + N ₂ gas.

The photosensitive film 110 is applied thereon, but the photosensitive film 110 is applied to a thickness such that only the metal hard mask 108 deposited on the top layer can be sufficiently etched.

When the application of the photoresist film 110 is completed, the photoresist film is patterned 111a in the via hole region. In this way, when the thickness of the photoresist film is applied low, fine patterning is easy and the critical dimension of the pattern is accurately realized. When patterning the photoresist, the wafer is in a flat state with no bending, which also facilitates fine patterning and adjustment of critical dimensions.

Next, referring to FIG. 4B, only the metal hard mask 108 deposited on the top layer is etched using a plasma activated with Cl ₂ + BCl ₃ + N ₂ gas. At this time, the metal hard mask 108 existing in the upper metal wiring region remains in the form of a thin metal wiring because it is protected by a pre-patterned photoresist film 108 '.

Next, referring to FIG. 4C, after a thin deposition of the tungsten (W) hard mask 112 on the structure of FIG. 4B, the chemical-mechanical-polling is performed so that the metal hard mask 108 ′ is exposed to the outside. CMP) planarization.

Next, referring to FIG. 4D, the photoresist film 114 is thinly coated and then the top metal line region is patterned 114 ′. In this case, the photoresist layer 114 is applied to a thickness low enough to etch only the metal hard mask 108 ′ deposited on the top layer. Patterning of the trenches is also easy because fine patterning occurs with no surface curvature.

Next, referring to FIG. 4E, only the metal hard mask 108 ″ of the remaining portion except for the top metal line region is etched using the plasma activated with Cl ₂ + BCl ₃ + N ₂ gas.

Next, referring to FIG. 4F, the oxide hard mask 116 is thinly deposited on the structure of FIG. 4E, and then planarized using a chemical-mechanical-planarization (CMP) method, which is formed in FIGS. 4B and 4E. The metal hard mask 108 ″ is exposed to the outside.

Next, referring to FIG. 4G, the bias power is lowered using a plasma activated with SF ₆ + Ar gas to increase the selectivity with the upper metal hard mask 108 ″ to perform etching, thereby tungsten metal hard mask 112. Only the low dielectric constant (Low-k) interlayer dielectric material in the region corresponding to the via hole region is exposed to the outside.

Next, referring to FIG. 4H, a low dielectric constant (Low-k) using a plasma activated with C _a F _b + C _x H _y F _z + Ar (a, b, x, y, z: integer) and the like ) The interlayer insulating film 106 'material is etched. At this time, the oxide film is controlled by appropriately adjusting the gas combination and plasma activation parameters of C _a F _b + C _x H _y F _z + Ar (a, b, x, y, z: integer). The plasma atmosphere is formed so that the selectivity of the low dielectric constant interlayer insulating film 106 'with respect to the hard mask and the selectivity of the low dielectric constant interlayer insulating film with respect to the metal hard mask 108 "are sufficiently large.

Next, referring to FIG. 4I, etching is performed using a plasma activated with Cl ₂ + BCl ₃ + N ₂ gas to remove the remaining metal hard mask 108 ″. At this time, the plasma activation parameter is removed. In this case, the bias power supply, which is responsible for accelerating the activated plasma components (radicals) down, is set as low as possible, such that when the bias power is applied low, Cl ₂ + BCl ₃ + N ₂ under most conditions. Since the plasma that activates the gas has a very low etching ratio to the oxidizing material, the oxide hard mask 116 and the low dielectric constant interlayer insulating film 106 'material are hardly etched.

Next, referring to FIG. 4I, a low dielectric constant (Low −) using plasma in which C _a F _b + C _x H _y F _z + Ar (a, b, x, y, z: integer) is activated again. k) By etching the interlayer insulating film 106 " material, a dual damascene pattern 118c in which a via hole and an upper metal wiring trench are simultaneously formed can be formed.

As described above, the method for forming a dual damascene etch of a semiconductor device according to the present invention is a double layer for a low-k interlayer dielectric film (IMD) material during a semiconductor device manufacturing process. It can be applied to form a multi-layer metallization (Multi Layer Meallization) by the damascene etching method. In particular, by adopting the process method proposed in the present invention, since the thickness of the patterned photosensitive film can be significantly lowered compared to the existing process method, it is possible to easily implement a fine pattern.

In addition, by employing the process method proposed in the present invention, since the thickness of the photoresist film patterned based on the conventional process method can be greatly reduced, there is an advantage in that the size of the via hole or the trench, particularly the critical dimension, can be precisely adjusted.

In addition, by adopting the process method proposed in the present invention, since all patterning of the photoresist is performed on a perfect flat plate, it is possible to facilitate fine pattern implementation and adjustment of critical dimensions.

By adopting the process method proposed in the present invention, there is no need to use a high dielectric constant stopping layer. Therefore, since the dielectric constant of the entire interlayer insulating film is lowered, the performance degradation of the semiconductor chip due to the RC delay can be prevented.

According to the process method proposed in the present invention, since the low dielectric constant interlayer insulating film is etched in the absence of the photosensitive film, the metal polymer is relatively small. Therefore, it is easier to remove the metal polymer after the etching is completed than the conventional process method.

According to the process method proposed in the present invention, when the metal line is patterned, it is patterned in an embossed form, resulting in an intaglio metal line. In other words, it means that the damascene pattern can be implemented using a general reticle rather than a reticle for damascene. In the case of Logic Foundary and COT business, some optional processes may be required due to the needs of the customer. The damascene and non damascene processes can be implemented with the same reticle. Therefore, the same reticle manufacturing cost can be saved.

In addition, according to the process method proposed in the present invention, since less polymer is generated, it is advantageous for cleaning, and thus the effect on yield due to inter connect fail is small.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (10)

Sequentially forming a diffusion barrier film, a low dielectric constant interlayer insulating film, and a metal hard mask on the semiconductor substrate on which the lower metal wiring is formed by a damascene process; Applying a first photoresist film on the metal hard mask and patterning the first photoresist film in a region where a via hole is to be formed; First etching only the metal hard mask by the patterned first photoresist; Depositing a thin layer of tungsten hard mask on the resultant and then planarizing it by a chemical mechanical polishing process to expose the metal hard mask to the outside; Patterning the upper metal wiring region after applying a thin layer of the second photosensitive film on the resultant, Second etching only the metal hard mask of the remaining portion except for the upper metal wiring region; After depositing a thin film of an oxide hard mask on the resultant, planarization using a chemical mechanical polishing process to expose the metal hard mask to the outside; Exposing only the tungsten hard mask to the outside by exposing the interlayer dielectric layer in a region corresponding to the via hole region to the outside; Etching the interlayer dielectric layer to form a via hole; Etching and removing only the metal hard mask by a fifth etch; And etching the interlayer insulating layer to form a via hole and an upper metal wiring trench at the same time by etching the sixth interlayer insulating layer. The method of claim 1, The method of forming a dual damascene etching of a semiconductor device, characterized in that the thickness of the first photoresist film is applied to a thickness low enough to etch only the metal hard mask to facilitate fine patterning. The method of claim 1, Dual damascene etching of a semiconductor device, characterized in that the thickness of the second photoresist film is applied to a thickness such that only the metal hard mask can be sufficiently etched to adjust the size of the patterned metal hard mask, in particular, the critical dimension. Forming method. The method of claim 1, The metal hard mask is a material that is well etched by the plasma activated Cl ₂ + BCl ₃ + N ₂ gas, that is, one of the Ti, TiN, Ta, TaN method of forming a dual damascene etching of a semiconductor device. The method of claim 1, The dual damascene etching method of the semiconductor device, characterized in that using the plasma activated by the Cl ₂ + BCl ₃ + N ₂ gas during the first etching. The method of claim 1, The dual damascene etching method of the semiconductor device, characterized in that for using the plasma activating Cl ₂ + BCl ₃ + N ₂ gas during the second etching. The method of claim 1, The dual damascene etching method of the semiconductor device, characterized in that for using the plasma activated by the SF ₆ + Ar gas during the third etching. The method of claim 1, Forming dual damascene etching of a semiconductor device, wherein the plasma is activated by using C _a F _b + C _x H _y F _z + Ar (a, b, x, y, z: integer) Way. The method of claim 1, The method of forming dual damascene etching of a semiconductor device, characterized in that using the plasma activated by the Cl ₂ + BCl ₃ + N ₂ gas during the fifth etching. The method of claim 1, A method of forming dual damascene etching of a semiconductor device using a plasma activated with C _a F _b + C _x H _y F _z + Ar (a, b, x, y, z: integer) and the like during the sixth etching.