KR20030081596A - STRUCTURE AND MANUFACTURING METHOD FOR MONOLITHICALLY INTEGRATED ENHANCEMENT/DEPLETION MODE (p-)HEMT DEVICES - Google Patents

Abstract

PURPOSE: A single integrated enhancement and depletion mode (p-)HEMT(High Electron Mobility Transistor) device structure and a method for manufacturing the same are provided to be capable of controlling the threshold voltage of an enhancement mode (p-)HEMT by controlling the impurity concentration of a barrier instead of controlling the thickness of the barrier. CONSTITUTION: A single integrated enhancement and depletion mode (p-)HEMT device structure is provided with a semi-insulating compound semiconductor substrate(100), a channel layer(104) formed at the upper portion of the substrate, a dopant doped barrier(106) formed on the channel layer, source/drain ohmic layers(108) spaced apart from each other at the upper portion of the barrier, a source/drain electrode(110) formed on each source/drain ohmic layer, and a gate electrode(112) formed at the exposed portion of the barrier between the source/drain ohmic layers. At this time, the device structure further includes an impurity concentration reduced region(116) formed in the barrier corresponding to the lower portion of the gate electrode by implanting hydrogen ions.

Description

STRUCTURE AND MANUFACTURING METHOD FOR MONOLITHICALLY INTEGRATED ENHANCEMENT / DEPLETION MODE (p-) HEMT DEVICES}

The present invention relates to a process for the preparation of (p-) HEMT (meaning High Electron Mobility Transistor: HEMT or strained high electron mobility transistor: pseudomorphic-HEMT: p-HEMT). The mode (p-) HEMT and the depletion mode (p-) HEMT are related to the structure of a single integrated device and a manufacturing method thereof.

In general, (p-) HEMT, which is a compound semiconductor device, has excellent electron speed characteristics compared to an electronic device using silicon, and thus is widely applied to device applications in the microwave or millimeter wave (10 GHz to 100 GHz) band. In particular, it has the advantages of low ultra-high frequency noise characteristics, so it is a very important device technology applied to the development of high-performance millimeter wave band wireless communication circuits and components or optical communication circuits and components of several tens of Gbps or more.

The (p-) HEMT is classified into a depletion mode transistor in which a threshold voltage (V _T ) is a negative value and a transistor in an increase mode in a positive value. Depletion mode (p-) HEMT is generally used to fabricate MMIC (Monolithic Microwave Integrated Circuit).

1A and 1B show an example of a circuit in which (p-) HEMTs in the depletion mode are integrated and a vertical cross-sectional view thereof in the prior art. As shown in FIG. 1A, an integrated circuit using only the depletion mode (p-) HEMTs 10, 12 requires two power supplies with + and-values (+ V _DD and -V _G ). . For this reason, when manufacturing a module for wireless communication using an integrated circuit composed of only (p-) HEMT in the depletion mode, two voltage sources are required, resulting in an increase in the size of the entire module.

Accordingly, there is a need for a device technology capable of fabricating an integrated circuit that can be operated by a single voltage source when a light and small component is required, such as an application for a mobile communication terminal. In order to implement a circuit that can be operated by such a single voltage source, as shown in FIG. 2A, it is possible to use a combination of a depletion mode and an increase mode transistor.

2A and 2B show examples of a circuit in which the (p-) HEMT in the incremental mode and the (p-) HEMT in the depletion mode and the vertical cross-sectional view thereof are integrated in the prior art. As shown in FIG. 2A, when directly directing the (p-) HEMT 10 in the depletion mode and the (p-) HEMT 20 in the incremental mode, only one power source V _DD is required, thereby reducing the size of the entire circuit.

However, in order to implement a circuit in which the depletion mode and the increase mode are integrated in the prior art, the depletion mode (p-) HEMT 10 and the increase mode (p-) HEMT 20 are formed on one substrate as shown in FIG. 2B. Should be produced together.

The threshold voltage of the (p-) HEMT is usually determined by the impurity doping concentration of the barrier layer and its thickness as shown in Equation 1 below.

Where Φ _B is the Schottky potential barrier, ΔE _C is the conduction band discontinuity between the barrier layer and the channel layer, N _D is the activated donor concentration, and d is the barrier layer Is the thickness.

As illustrated in FIG. 1B, when the integrated circuit is implemented with the (p−) HEMTs 10 and 12 in the depletion mode, the threshold voltage of the depletion mode is negative, and thus, there is no need to adjust the thickness of the barrier layer 106. However, when implementing a single integrated circuit with (p-) HEMT in depletion mode and increase mode as shown in FIG. 2B, the barrier layer thickness d of the increase mode must be adjusted. As such, the thickness adjustment of the barrier layer that determines the operation mode of the (p-) HEMT is mainly performed through an etching process before forming the gate electrode.

Referring to FIG. 2B, a gate mask pattern (not shown) using a photoresist (not shown) is formed on the (p-) HEMT 10 in the depletion mode, and the source / drain ohmic layer 108 is formed by a selective etching method. After etching to expose the barrier layer 106 surface, the gate mask pattern is removed. At this time, the thickness of the barrier layer 106 is a thickness for obtaining a negative threshold voltage for operating in the depletion mode (p-) HEMT. A gate mask pattern (not shown) using photoresist is then formed for the (p-) HEMT in incremental mode and the source / drain ohmic layer 108 is etched by selective etching to expose the barrier layer 106 surface. After the barrier layer 106 is further etched to a predetermined depth 114, the thickness of the barrier layer 106 is reduced. As a result, the thickness of the barrier layer 106 further etched to a predetermined depth 114 is a thickness capable of obtaining a positive threshold voltage for operating with the (p-) HEMT in the incremental mode.

3 is a graph showing the relationship between the barrier layer thickness and the threshold voltage under the gate electrode in a circuit in which (p-) HEMTs of the conventional increase mode and the depletion mode are integrated.

Referring to the graph of FIG. 3, the change of the threshold voltage value according to the thickness of the barrier layer under the gate electrode is shown in (p−) HEMT of the general increase mode and the depletion mode. According to this, since the magnitude of the threshold voltage is adjusted according to the thickness of the barrier layer, it can be seen that the depletion mode and the increment mode (p-) HEMT can be integrated into a single chip by controlling the thickness of the barrier layer using an etching process.

However, in the integrated circuit, the barrier layer thickness of each mode (p-) HEMT must be uniform for the uniformity of device characteristics and the yield of the integrated circuit. In the case of the conventional depletion mode (p-) HEMT, since the source / drain ohmic layer and the barrier layer are different materials, when the selective etching method is used, the barrier layer has a high threshold voltage because the thickness of the barrier layer is formed at the epitaxial growth. Uniformity can be obtained. However, in the case of the increased mode (p-) HEMT, since the barrier layer made of the same material must be etched to a predetermined thickness, a selective etching method cannot be used, and there is a problem in that the uniformity and reproducibility of the barrier layer thickness to be etched are not high. As a result, the nonuniformity of the barrier layer thickness caused by the etching process is represented by the nonuniformity of the threshold voltage, and the nonuniformity of the threshold voltage of the incremental mode (p-) HEMT device is a cause of lowering the yield of the MMIC fabricated using such a device. Works.

An object of the present invention is to adjust the threshold voltage using the impurity concentration of the barrier layer rather than adjusting the threshold voltage of the increase mode (p-) HEMT to the thickness of the barrier layer by etching in order to solve the problems of the prior art as described above. By adjusting, a single integrated increment and depletion mode (p-) can be fabricated to produce a single integrated circuit consisting of high yield depletion and (p-) HEMT with high yield depletion and (p-) HEMT with uniform device characteristics. An HEMT device and a method of manufacturing the same are provided.

In order to achieve the above object, the present invention provides a channel layer which is formed on the semi-insulating compound semiconductor substrate and which is not doped with impurities, a barrier layer formed on the channel layer and doped with impurities, and spaced apart from each other on the barrier layer. Between the source / drain ohmic layer of mode and depletion mode (p-) HEMT, the source / drain electrode of incremental and depletion mode (p-) HEMT formed in contact with the source / drain ohmic layer, and the source / drain ohmic layer. In a single integrated increase mode and depletion mode (p-) HEMT consisting of gate electrodes of increase mode and depletion mode (p-) HEMT formed in the exposed space of the barrier layer, the gate of the increase mode (p-) HEMT device And an impurity concentration reducing region in which hydrogen ions are implanted into the barrier layer corresponding to the lower electrode to control the impurity concentration.

In order to achieve the above object, the present invention sequentially forms a channel layer without impurities and a barrier layer doped with impurities on the semi-insulating compound semiconductor substrate, and an increase mode and depletion spaced apart from each other on the barrier layer. Forming a source / drain ohmic layer of mode (p-) HEMT, forming a source / drain electrode of incremental and depletion mode (p-) HEMT in contact with the source / drain ohmic layer, and source / drain Exposing the barrier layer of the increase mode and depletion mode (p-) HEMT between the ohmic layers, performing a process for adjusting the barrier voltage of the increase mode (p-) HEMT, and the increase mode and depletion mode ( Fabrication of a single integrated device of incremental and depletion mode (p-) HEMTs comprising forming a gate electrode for an incremental and depletion mode (p-) HEMT in a space where a barrier layer of p-) HEMT is exposed Ha A method of controlling an impurity concentration through a hydrogen ion implantation process in a barrier layer corresponding to a lower gate electrode of an incremental mode (p-) HEMT device to control the barrier voltage of the incremental mode (p-) HEMT device. It further comprises.

1A and 1B show an example of a circuit in which (p-) HEMTs of the depletion mode are integrated in the prior art and a vertical cross-sectional view thereof,

2A and 2B are examples of a circuit in which the (p-) HEMT in the incremental mode and the (p-) HEMT in the depletion mode and the vertical cross-sectional view thereof are integrated in the prior art,

3 is a graph showing the relationship between the barrier layer thickness and the threshold voltage under the gate electrode in a circuit in which (p-) HEMTs of the conventional increase mode and the depletion mode are integrated;

4 is a vertical cross-sectional view of a device in which a depletion mode (p-) HEMT and a monolithic increase mode (p-) HEMT having a barrier layer implanted with hydrogen ions are integrated according to the present invention;

Fig. 5 shows the barrier layer impurity concentration and threshold voltage under the gate electrode in (p-) HEMT having a single integration of (p-) HEMT in increasing and depletion mode according to the present invention and having a barrier layer implanted with hydrogen ions in increasing mode. Graph showing the relationship between

6 is a graph illustrating a change in the threshold voltage of (p-) HEMT according to a hydrogen ion process and a heat treatment process condition using RIE when fabricating an increase mode (p-) HEMT device according to an embodiment of the present invention;

7A to 7E are process flow diagrams illustrating an example of an (p-) HEMT manufacturing process of an incremental mode in (p-) HEMT in which an incremental and depletion mode is integrated according to the present invention.

<Description of the code | symbol about the principal part of drawing>

10, 12: depletion mode (p-) HEMT 20: incremental mode (p-) HEMT

100: semi-insulating compound semiconductor substrate 102: buffer layer

104: channel layer 106: barrier layer

108: source / drain ohmic layer 110: source / drain electrode

111 mask pattern 112 gate electrode in depletion mode

112a: gate electrode in increasing mode 116: impurity concentration decreasing region

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a vertical cross-sectional view of a device in which a depletion mode (p-) HEMT and an incremental mode (p-) HEMT with a barrier layer implanted with hydrogen ions are integrated according to the present invention.

As shown in FIG. 4, the integrated circuit according to the present invention includes a buffer layer 102 formed on a semi-insulating compound semiconductor substrate 100 and a buffer layer 102 formed on the buffer layer 102 and doped with impurities. And a channel layer 104 and a barrier layer 106 formed on the channel layer 104 and doped with impurities.

In the integrated circuit of the present invention, the source / drain ohmic layer 108 and the source / drain ohmic layer of the depletion mode and the increase mode (p-) HEMT 10 and 20 formed on the barrier layer 106 are spaced apart from each other. 108 is a stacked depletion formed in the space where the barrier layer 106 is exposed between the source / drain electrode 110 of the depletion mode and the incremental mode (p-) HEMT formed in contact with the source 108 and the source / drain ohmic layer 108. Gate electrode 112 in mode and gate electrode 112a in 'T' shaped incremental mode.

In particular, in a single integrated circuit having (p-) HEMT in incremental and depletion mode according to the present invention, the barrier layer 106 of (p-) HEMT 20 in incremental mode is equal to (p-) HEMT in depletion mode. Barrier layer 106 has a thickness. In this case, the impurity doping concentration (Don concentration: N _D ) of the (p-) HEMT barrier layer 106 in the depletion mode is determined during crystal growth of the barrier layer 106. Therefore, the (p-) HEMT in the depletion mode is set to a negative threshold voltage (V _T ).

Meanwhile, the present invention forms an impurity concentration reducing region 116 under the hydrogen ion implantation process under the gate electrode in the (p-) HEMT in the increasing mode, and changes the impurity doping concentration (N _D ) of the barrier layer 106 in this region. Passivation with hydrogen ions neutralizes to reduce to N _D '. Because of this, the (p-) HEMT in incremental mode is set to a positive threshold voltage (V _T ).

FIG. 5 shows the barrier layer impurity concentration (N _D ) under the gate electrode in (p-) HEMT having a single integration of (p-) HEMT in increasing and depletion mode and implanted with hydrogen ions in increasing mode according to the present invention. ') Is a graph showing the relationship between the threshold voltage (V _T ).

As can be seen in the graph of FIG. 5, the impurity concentration N _D ′ of the barrier layer can be adjusted by adjusting the amount of hydrogen ions injected into the barrier layer according to the present invention, and thus the threshold voltage V _T is greater than zero. It is possible to fabricate (p-) HEMT devices in large incremental mode.

FIG. 6 is a graph illustrating a change in the threshold voltage of (p-) HEMT according to a hydrogen ion process and a heat treatment process condition using RIE when fabricating an increase mode (p-) HEMT device according to an embodiment of the present invention. Examples of conditions for the hydrogen ion process here are temperature = room temperature, hydrogen flow rate = 50 sccm, RIE chamber pressure = 50 mT, time = 0 minutes, 2 minutes and 4 minutes, RF power = 0 W, 30 W and 100 W. Examples of heat treatment conditions are temperature = 470 deg. C, time = 20 seconds.

Referring to the graph of FIG. 6, as the RF power of the RIE increases, the amount of hydrogen injection increases and the impurity concentration of the barrier layer further decreases, so that the threshold voltage of the (p−) HEMT is moved in the positive direction (+) to increase the mode. It is possible to manufacture (p-) HEMT.

7A to 7E are process flow diagrams illustrating an example of an (p-) HEMT manufacturing process of an incremental mode in (p-) HEMT in which an incremental and depletion mode is integrated according to the present invention. Referring to these, the (p-) HEMT manufacturing method of the increase mode of this invention is as follows. In the above process flowchart, only the incremental mode (p-) HEMT is shown for simplicity of explanation.

First, as shown in FIG. 7A, a buffer layer 102 and a channel layer 104 doped with impurities are formed on the semi-insulating compound semiconductor substrate 100. Here, the semi-insulating compound semiconductor substrate 100 is GaAs, InP, sapphire, etc., and the channel layer is GaAs-based HEMT, if one is not a non-impurity-doped GaAs, doped with an impurity for GaAs-based p-HEMT In _x Ga _{1- x} As (x> 0), In _0.53 Ga _0.47 As for InP HEMT, In _x Ga _1-x As (x> 0.53) for InP pHEHE, GaN and GaN p- for HEN GaMT The HEMT may be formed of In _x Ga _1-x N (x> 0).

The barrier layer 106 doped with impurities is formed on the channel layer 106. Here, the barrier layer 106 is generally made of a material having a greater bandgap energy than the channel layer 104, and is InGaP or AlGaAs for GaAs-based (p-) HEMT, InAlAs for InP-based (p-) HEMT, GaN-based (p-) HEMT is made of GaN or AlGaN. In addition, the barrier layer 106 is generally modulated doping to n-type, and may include a uniform doping structure, a delta doping structure, a mixed structure of uniform and delta doping according to a distribution profile of the doping. .

In addition, source / drain ohmic layers 108 of the incremental mode and depletion mode transistors are formed on the barrier layer 106 to be spaced apart from each other. Here, the source / drain ohmic layer 108 is made of a semiconductor having a small bandgap energy for forming a metal electrode having a low resistance value at the source and drain of the (p-) HEMT, for example, a GaAs series ( GaAs for p-) HEMT, In _0.53 Ga _0.47 As for InP series (p-) HEMT, GaN or In _x Ga _1-x N (x> 0) for GaN-based (p-) HEMT are used. It is doped with a high concentration n type.

The source / drain electrodes 110 of the incremental and depletion mode transistors are then formed in contact with the source / drain ohmic layer 108.

Subsequently, as shown in FIG. 7B, a mask is formed to perform the photolithography process on the resultant source / drain electrode 110 to define the gate electrode region of the incremental mode (p-) HEMT, and then to mask the hydrogen ion implantation. The pattern 111 is formed. The mask pattern 111 may be a photoresist, a polyimide, a silicon oxide film (SiO ₂ ), a silicon nitride film (Si ₃ N ₄ ), or the like. If the hydrogen is ion implanted into the front surface of the device without adopting the mask pattern 111, the resistance characteristics of the source and drain ohmic layers may be deteriorated, and the channel layer between the gate and the source and drain may be depleted, resulting in a series of sources and drains. Series resistance is increased to deteriorate device characteristics. Therefore, the mask pattern 111 must be covered to prevent hydrogen ion implantation in the remaining portions except for the gate region of the increment mode (p-) HEMT. Hydrogen ions (H +) are implanted into the barrier layer 106 of the increased mode (p−) HEMT exposed by the mask pattern 111.

The hydrogen ion (H +) implantation process may be performed by using an ion implanter or by using a reactive ion etching equipment (RIE) using hydrogen as a gas source. In the case of using an ion implanter, the energy and dosage of hydrogen affect the extent to which the impurity concentration in the barrier layer 106 is reduced. In the case of using the reactive ion etching equipment, process conditions such as the flow rate of hydrogen, the pressure of the chamber, the RF power, and the like affect the extent to which the impurity concentration in the barrier layer 106 is reduced.

After the ion implantation, a heat treatment step is further performed. As a result, as shown in FIG. 7C, the impurity concentration reducing region 116 into which the hydrogen ions are implanted is formed in the barrier layer 106 of the increase mode (p-) HEMT. After ion implantation, the hydrogen ions activated by the heat treatment process are present in a passivated state in combination with many n-type impurities in the barrier layer 106. Generally, the n-type impurity is positively charged after emitting electrons, but when passivated by hydrogen, the n-type impurity does not function as an ionized n-type impurity (N _D +). As a result, the effective n-type impurity concentration is reduced when some of the n-type impurities in the barrier layer 106 are neutralized by hydrogen passivation. Therefore, the present invention uses this principle to further form a region 116 in which the impurity concentration of the barrier layer is reduced by hydrogen ions, thereby increasing the incremental mode (p-) HEMT without going through a separate barrier layer etching process as in the prior art. Threshold voltage can be adjusted.

In addition, the amount of impurities in the impurity concentration reducing region 116 passivated by hydrogen varies depending on the type of material forming the barrier layer 106 but may be controlled by heat treatment. In other words, when the heat treatment after the hydrogen injection process, a portion of the hydrogen passivating impurities are removed and reduced to normal impurities. The amount of impurities normally reduced increases with increasing heat treatment temperature and time (in a temperature region lower than a temperature that may degrade the ohmic characteristics of the device or the surface state of the barrier layer). Therefore, the present invention can control the impurity concentration of the (p-) HEMT barrier layer in the incremental mode through the heat treatment process after hydrogen ion implantation, so that the reproducibility and uniformity of the impurity concentration control is much higher than that of the conventional barrier layer etching process. I can guarantee it.

7D and 7E, the gate electrode of the incremental mode (p-) HEMT self-aligned using a hydrogen injection mask pattern in a space where the impurity concentration reducing region 116 is exposed. 112a is formed and the mask pattern 111 is removed. At the same time, the gate electrode of the depletion mode (p-) HEMT is formed in the exposed barrier layer 106 even in the depletion mode (p-) HEMT not shown in the drawing.

As described above, according to the present invention, the barrier layer etching process is conventionally performed by injecting and heat-treating hydrogen ions into the barrier layer positioned below the gate of the increase mode in the depletion mode and the increase mode (p-) HEMT in a single integrated circuit. It is easy to adjust the threshold voltage in incremental mode without using it.

Therefore, the present invention manufactures the increase mode (p-) HEMT with uniform device characteristics because the threshold voltage is adjusted by adjusting the impurity concentration of the barrier layer rather than adjusting the threshold voltage of the increase mode (p-) HEMT to the thickness. It is effective to manufacture a single integrated circuit composed of (p-) HEMT in high yield depletion and increase mode.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (6)

A channel layer formed on the semi-insulating compound semiconductor substrate and not doped with impurities, a barrier layer formed on the channel layer and doped with impurities, and an increase mode and a depletion mode formed on the barrier layer and spaced apart from each other (p−). The barrier layer is exposed between the source / drain ohmic layer of HEMT, the source / drain electrode of the increase and depletion mode (p-) HEMT formed in contact with the source / drain ohmic layer, and the source / drain ohmic layer. In a single integrated incremental mode and depletion mode (p-) HEMT consisting of a gate electrode of an incremental mode and a depletion mode (p-) HEMT formed in a closed space, And a single integrated increase and depletion mode (p-), wherein the impurity concentration is reduced by implanting hydrogen ions into the barrier layer corresponding to the gate electrode of the HEMT device. -) Structure of HEMT device. Sequentially forming an impurity doped channel layer and an impurity doped barrier layer over the semi-insulating compound semiconductor substrate; Forming a source / drain ohmic layer in an incremental mode and a depletion mode (p-) HEMT spaced apart from each other on top of the barrier layer; Forming a source / drain electrode in incremental mode and depletion mode (p-) HEMT in contact with the source / drain ohmic layer; Exposing a barrier layer of increasing mode and depletion mode (p-) HEMT between the source / drain ohmic layers; Performing a process to adjust the barrier voltage of the increase mode (p-) HEMT; And Forming a gate electrode for an incremental mode and a depletion mode (p-) HEMT in a space where the barrier layer of the incremental mode and the depletion mode (p-) HEMT is exposed; In the method of manufacturing a single integrated device, Adjusting an impurity concentration through a hydrogen ion implantation process in a barrier layer corresponding to a lower gate electrode of the incremental mode (p-) HEMT device to control the barrier voltage of the incremental mode (p-) HEMT; A method of fabricating a single integrated incremental and depletion mode (p-) HEMT device. The method of claim 2, wherein in forming the impurity concentration reducing region, a mask for preventing hydrogen ion implantation is formed in a region other than the lower portion of the gate of the increasing mode. Method for manufacturing p-) HEMT device. 3. The single integrated increase and depletion mode (p-) HEMT of claim 2, wherein hydrogen ions are implanted using an ion implanter or reactive ion etching (RIE) equipment to form the impurity concentration reducing region. Method of manufacturing the device. The method of claim 2, wherein the forming of the impurity concentration reducing region comprises implanting hydrogen ions and performing a heat treatment to control the amount of passivated and neutralized impurities to form a single integrated increase and depletion mode (p). -) Method of manufacturing the HEMT device. 3. The single integrated increase of claim 2, wherein a self-aligned T-type gate electrode is formed using a mask for preventing hydrogen ion implantation when forming the gate electrode of the incremental mode (p-) HEMT. And depletion mode (p-) HEMT device manufacturing method.