KR20030078379A - Circuit for protecting Electro Static Discharge - Google Patents

Abstract

PURPOSE: An ESD(Electrostatic Discharge) protection circuit is provided to be capable of adapting silicide processing to an active region by reducing the size of chip. CONSTITUTION: An ESD protection circuit comprises a pad(50) having a desired inductance and a bypass part(51). The bypass part(51) is connected between the pad(50) and an inner circuit for bypassing the ESD from the inner circuit. The ESD protection circuit further includes a resistor(R) connected between the pad and the inner circuit. An inductor(L) having a core is used as the pad(50). Also, the inductor(L) without the core is used as the pad(50).

Description

Circuit for protecting Electro Static Discharge

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to an electrostatic discharge protection circuit of a semiconductor integrated circuit.

Static electricity refers to a phenomenon in which a large current flows instantaneously due to a very large voltage difference between two objects when two insulated objects come into contact with each other.

Therefore, if the current caused by static electricity flows through the internal circuit of the semiconductor, it may cause fatal damage to each circuit element. Therefore, it is necessary to provide a path through which the current caused by static electricity can flow without destroying the internal circuit of the semiconductor device. These static current paths must be able to effectively discharge the charge quickly, so as not to damage other circuit elements.

In the case of semiconductor devices, in order to prevent product destruction or product deterioration due to static electricity, an electrostatic protection circuit is installed between the chip internal circuit and the pad to which the external input / output pins are connected. The internal circuit is protected by discharging to the power terminal or ground terminal.

Until now, the electrostatic models known to damage semiconductor devices may be classified into a human body model (HBM), a machine model (MM), and a charged device model (CDM).

HBM stands for human static model, and MM stands for electrostatic model by equipment. In addition, CDM refers to an ESD model generated by +/- charge in a package during product assembly. CDM, which has recently emerged as an issue of the aforementioned electrostatic model, directly affects the yield of the product because the chip is destroyed by the charged charge during the assembly process.

Recently, as the gate oxide thickness decreases due to the reduction in power, the gate oxide film of the input buffer receiving the input signal becomes a problem that is susceptible to static electricity.

1 is a block diagram for electrostatic protection of a semiconductor device according to the prior art.

Referring to FIG. 1, the semiconductor device according to the related art includes an input static electricity protection circuit between an input pad PADI and an input buffer 20 for protecting static electricity, and between an output pad PADO and an output buffer 40. The output static electricity protection circuit is provided. The internal circuit unit 30 receives a signal from the input buffer 20 and outputs a signal to the output buffer 40.

The input static electricity protection circuit 10 includes a first diode D1 connecting the power supply voltage VDD and the input pad PADI, and a second diode D2 connecting the ground power supply VSS and the input pad PADI. It consists of.

The output static electricity protection circuit 50 includes a third diode D3 connecting the power supply voltage VDD and the output pad PADO, and a fourth diode D4 connecting the ground power supply VSS and the output pad PADO. It consists of.

Accordingly, the input pad PADI is connected to the gates of the transistors MP1 and MN1 constituting the input buffer 20, and the output pad PADO is connected to the gates of the transistors MP2 and MN2 constituting the output buffer 40. It is connected to the drain.

FIG. 2 is a circuit diagram showing one of the diodes D2 or D4 shown in FIG. 1, which is implemented by a diode Tr connected between a pad and a cell.

FIG. 3 is a plan view illustrating the layout of the transistor of FIG. 2, which includes a gate G, a gate contact GC / T, a source S, a source contact SC / T, a drain D, and a drain contact. (DC / T) are shown respectively.

4 is a plan view illustrating the pad metal and the top via contact, and shows the pad metal layer M and the via contact V-C / T, respectively.

On the other hand, the number of input / output terminals of semiconductors is increasing exponentially with the improvement of computer technology. As the layout and design rules of transistors of ESD protection circuits are large, silicide is applied to make them stable. Difficult problems arise.

An object of the present invention is to provide a static electricity protection circuit that can reduce the chip size by reducing the design rule of the static electricity protection circuit, and to which the silicide process can be applied to the active.

1 is a block diagram for electrostatic protection of a semiconductor device according to the prior art,

FIG. 2 is a circuit diagram showing either diode D2 or D4 shown in FIG. 1;

3 is a plan view showing the layout of the transistor of FIG.

4 is a plan view of the pad metal and the top via contact;

5 is a circuit diagram showing an electrostatic protection circuit according to an embodiment of the present invention;

6 is a plan view illustrating the transistor of FIG. 5;

7 is a plan view of FIG. 5;

8 is a top plan view of FIG. 7;

* Explanation of symbols on the main parts of the drawing.

50: pad

51: bypass section

L: Inductor

R: resistance

Tr: Transistor

The present invention for achieving the above object, the pad formed to have a predetermined inductance; And a bypass part connected between the pad and the internal circuit to bypass static electricity generated from the outside or generated from the internal circuit through the pad from the internal circuit.

According to the present invention, the pad terminal can be used as an inductor, thereby reducing the design rule of the input / output electrostatic protection circuit so that the silicide can be applied to the active of the electrostatic protection circuit by reducing the chip size to improve the characteristics of the chip. Characterized in that.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. 5 is a circuit diagram illustrating an electrostatic protection circuit according to an embodiment of the present invention, FIG. 6 is a plan view of the transistor of FIG. 5, FIG. 7 is a plan view of FIG. 5, and FIG. 8 is of FIG. 7. Top view of the.

Referring to FIG. 5, the static electricity protection circuit of the present invention may be connected between the pad 50 having a predetermined inductance and the pad 50 and the internal circuit and applied from the outside through the pad 50. And a bypass unit 51 for bypassing the static electricity generated therein from the internal circuit.

A resistor 50 is connected between the pad 50, that is, the inductor L and the internal circuit, to form a low pass filter, and the inductor L may further include a core. May not be included.

The pad 50 is preferably implemented through aluminum (Al) or copper (Cu) used as a metal wiring, and the resistor R is preferably implemented including polysilicon.

On the other hand, the bypass unit 51 is in the form of a diode connected in a reverse direction between the ground power terminal (VSS) and the pad 50, that is, the node 'X' as shown in the drawing, or the power supply voltage terminal (VDD) and the node ' The diode in the present invention includes a diode connected in a reverse direction between X ', and the diode of the present invention has a transistor Tr diode-connected with a source S as an example.

That is, as shown, the present invention has designed an ESD protection circuit using an inductor (L) to solve the conventional problems, and in implementing this, the pad (so as not to require an additional area for the inductor L) 50) The pad 50 is designed to use the terminal as the inductor L. The active design rule of the ESD protection circuit is the same as that of the cell, that is, the internal circuit, so that the silicided active region can be realized.

ESD occurs mainly when a high voltage is generated instantaneously by static electricity or lightning, and the higher the rate of voltage rise at a moment, the greater the amount of change in voltage, that is, dV / dt. Since it is proportional to the reactance of the inductor, that is, the inductance and dV / dt, an approximation equation of "resistance = constant x voltage" is established at the instantaneous voltage rise.

On the other hand, since "current = voltage / resistance, resistance = constant x voltage", the current at the time of the voltage surge to the circuit to which the inductor L is applied is a constant independent of the voltage, that is, "current = 1 / constant" as follows. Asymptotically approximated as

Since the inductor (L) is inserted into the circuit inlet of the cell and the inductor is not applied to the bypass unit 51, the bypass unit 51 operates when the instantaneous high voltage and the continuous high voltage occur, and the cell having the inductor L at the inlet Is safe at high voltages.

In the event of continuous high voltage, the cell is protected in such a way that a larger current flows in the bypass section 51. The operating voltage, that is, during operation, is higher than the source S / drain Pu punch generation voltage of the transistor Tr of the bypass unit 51 to maintain the turn-off state so that power consumption is hardly generated. .

Hereinafter, the operation of the above-described static electricity protection circuit will be described in detail.

First, when a normal voltage is applied, the gate length is greater than the gate length of the transistor Tr. The transistor Tr is turned off by connecting the gate of the transistor Tr to the ground voltage terminal VSS, and there is no current flowing between the drain D and the source S. Further, the reactance is close to " 0 " because dV / dt or dI / dt of the externally input signal is not large enough to increase the reactance of the inductor L. Therefore, the input current and the signal are delivered to the internal circuit, for example, the cell, along the pad 50 and the resistor R.

On the other hand, when the DC high voltage is applied, the punch generating voltage of the transistor Tr is designed to be higher than the punch generating voltage of the cell transistor. However, since there is an inductor L and a resistor R between the external circuit and the internal circuit, there is a timing delay. ) And punching occurs first in the transistor Tr to dissipate a high voltage current that can go into the internal circuit. Once the punching voltage is generated, since the resistance of the transistor Tr is significantly smaller than the resistance of the internal circuit, most current flows to the transistor Tr to protect the internal circuit. That is, punching occurs between the drain D and the source S of the transistor Tr, so that the current falls into the ground voltage terminal VSS.

In addition, when a high voltage pulse such as lightning or static electricity occurs, the reactance of the inductor L increases so that a current does not flow between the external circuit and the internal circuit, and a punching current flows along the transistor Tr.

FIG. 6 is a plan view illustrating the layout of the transistor of FIG. 5, which includes a gate G, a gate contact GC / T, a source S, a source contact SC / T, a drain D, and a drain contact. (DC / T) are shown respectively. It can be seen that the size can be significantly reduced compared to the conventional transistor of FIG. 3 described above.

In FIG. 7, it can be seen that the spiral inductor L is implemented through the first metal wire M1, and a separate core may be added to the inductor L, and a conventional wiring material such as aluminum or copper may be added. Can be used.

The illustrated 'C / T' represents each contact, R represents the resistance of FIG. 5 made of polysilicon or the like, and 'D' represents the drain of the transistor Tr.

FIG. 8 is a plan view illustrating the second metal wiring M2 and the upper via contact VC / T, and the second metal wiring M2 and the via contact VC / T are shown, respectively. Is the opposite of the aforementioned 'M1' and the Turn (Turn) direction.

Here, as described above, the size of the transistor Tr can be reduced, so that the silicide process can be easily applied to the active region, and consequently, the effect of reducing the contact resistance can be expected.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention as described above has the following effects.

1. Since the inductor used in the present invention acts as a low pass filter for buffering high voltage and high frequency pulse inputs, the gate contact design rules of the ESD transistor do not need to be made as large as in the prior art. Significant reduction can be achieved to improve the degree of integration.

2. In conventional ESD transistors, the active width is large, so that silicide formation on the junction cannot maintain the same size as the cell, and it is possible to manufacture an ESD transistor using silicided active.

3. Since the pad metal is modified in the inductor design, there is no additional area consumed by the addition of the inductor.

4. Since the input / output using silicide is used, the contact resistance can be reduced to improve the characteristics.

5. Except for the exception of using a non-silicide zone in a cell, the process for forming the non-silicide zone can be omitted, thereby lowering the process cost.

6. With the exception of the use of non-silicide regions in the cell, all regions are unified with silicides in the contact process, making process conditions easier and process margins wider.

7. Improved yield due to wider process margin.

8. Reduced device size reduces the effect of defect density and improves yield.

9. Increased production with more chips per wafer.

Claims (10)

A pad formed to have a predetermined inductance; And A bypass means connected between the pad and the internal circuit to bypass static electricity generated from the internal circuit or applied from the outside through the pad. Static protection circuit comprising a. The method of claim 1, The static electricity protection circuit further comprises a resistor connected between the pad and the internal circuit. The method of claim 2, And the resistor forms a low pass filter with the pad. The method of claim 1, And the pad implements an inductor with a core. The method of claim 1, Wherein the pad implements a coreless inductor. The method according to claim 4 or 5, The pad is an electrostatic protection circuit, characterized in that it comprises aluminum or copper. The method of claim 2, The resistance is static electricity protection circuit, characterized in that including polysilicon. The method of claim 1, The bypass means, And a first diode connected in a reverse direction between the ground voltage terminal and the pad. The method of claim 1, The bypass means, And a second diode connected in a reverse direction between a power supply voltage terminal and the pad. The method according to claim 8 or 9, And the first and second diodes comprise diode-connected transistors.