KR20030073586A - Rf filter circuit and laminated ceramic filter - Google Patents

Abstract

PURPOSE: A high frequency filter circuit and a stacked ceramic filter are provided to reduce insertion losses and achieve improved inhibit characteristics. CONSTITUTION: A high frequency filter circuit comprises a first capacitor(C1) and a second capacitor(C2) connected in serial between an input terminal(IN) and an output terminal(OUT); a first inductor(L1) connected in parallel to the serial circuit of the first and second capacitors; and a second inductor(L2) and a third capacitor(C3) connected in serial to the ground from the contact of the first and second capacitors.

Description

RF FILTER CIRCUIT AND LAMINATED CERAMIC FILTER}

The present invention relates to a high frequency filter circuit and a multilayer ceramic filter. In particular, by improving a high frequency filter applied to a high frequency composite component of a dual mode mobile communication terminal with a simple circuit, it is possible to miniaturize and reduce the insertion loss. It relates to a high frequency filter circuit and a multilayer ceramic filter to improve the stopping characteristics.

In general, the development of the mobile communication terminal in recent years to develop a process that can simultaneously handle a variety of modes, such as CDMA, GPS, PCS, accordingly, by separating the signal from the front-end of the terminal There is a need for development of a filter that can be applied.

1 is a schematic configuration diagram of a general dual-mode terminal, which includes an RF switch 11 for switching a PCS band of 1.85 GHz to 1.99 GHz, a GPS band of approximately 1.575 GHz, and a 859 MHz AMPS band, and the RF switch 11 The PCS band of 1.85 GHz to 1.99 GHz is provided to the PCS transceiver 21, and the GPS band of approximately 1.575 GHz and the 859 MHz AMPS band are again converted by the diplexer 12 to the GPS band of 1.575 GHz. It is provided to the receiver 22, and the 859 MHz AMPS band is provided to the AMPS transceiver 23.

FIG. 2 is a dual mode frequency characteristic diagram of FIG. 1. Referring to FIG. 2, the diplexer 12 operates as a low pass filter (LPF) to pass an AMPS band of 859 MHz. It operates as a high pass filter (HPF) to pass the GPS band.

However, in order to filter several signals at the same time, the number of modes increases and the frequency interval between the modes is getting closer, making it difficult to implement an excellent filter that passes only the desired signal while maintaining the insertion loss of the filter used in the conventional single mode. . In addition, in the case of GPS and US-PCS, it is difficult to manufacture a diplexer and a triplexer because the frequency interval is close to about 300 MHz, so that multiple parts are combined without using a single filter. Is proposed as an alternative. Among them, a low pass filter is required to block the PCS signal and pass only the GPS signal to the GPS signal stage. The signal separation is more difficult because the GPS signal and the PCS signal are close in frequency band.

3 is a conventional high frequency filter circuit diagram, and FIG. 4 is a frequency characteristic diagram of FIG. 3.

Referring to FIGS. 3 and 4, the conventional high frequency filter circuit includes three circuits (T1, T2 and T3) as shown in FIG. 3 and implemented as a filter, and the characteristics thereof are shown in FIG. 4. 4, the frequency passing characteristic from port 1 to port 2 is shown in frequency graph S12, and the frequency reflection characteristic reflected from port 2 to port 2 is shown in frequency graph S22. In this case, when looking at the GPS frequency of the 1.575GHz S12, the specification of the band lower than -3dB should be satisfied. However, since it shows about -4dB, there is a problem in that the frequency characteristic is not good.

As a result, more devices must be included to achieve the desired characteristics. Therefore, it is judged that a simpler and better filter can be obtained by using the circuit proposed in the patent.

As described above, in order to implement a device capable of filtering two signals at a frequency interval close to 300 MHz, the number of stages of the resonator may be increased, but in this case, the insertion loss may increase due to the increase in the number of devices. have.

Therefore, the present invention is to construct a circuit of a filter that can divide the signal of two bands while minimizing the insertion loss by configuring a circuit different from the conventional filter implementation method and implement it in a multilayer ceramic structure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and therefore, an object of the present invention is to improve the high frequency filter applied to the high frequency composite component of the dual mode mobile communication terminal with a simple circuit, thereby making it possible to miniaturize and insert it. The present invention provides a high frequency filter circuit and a multilayer ceramic filter which can reduce losses and improve the stopping characteristics.

1 is a schematic configuration diagram of a general dual-mode terminal.

FIG. 2 is a dual mode frequency characteristic diagram of FIG. 1.

3 is a conventional high frequency filter circuit diagram.

4 is a frequency characteristic diagram of FIG. 3.

5 is a high frequency filter circuit diagram according to the first embodiment of the present invention.

6A and 6B are frequency characteristic diagrams of FIG. 5.

7 is a high frequency filter circuit diagram according to a second embodiment of the present invention.

8 is an exploded perspective view of a multilayer ceramic filter according to the present invention.

9A and 9B are plan and side views of the multilayer ceramic filter of FIG. 8.

Explanation of symbols on the main parts of the drawings

C1, C2, C3: Capacitor L1, L2: Inductor

C11, C12: Capacitor L11, L12, L13: Inductor

As a technical means for achieving the above object of the present invention, the high frequency filter circuit of the present invention comprises: first and second capacitors connected in series between an input terminal and an output terminal; A first inductor connected in parallel to the series circuit of the first and second capacitors; And a second inductor and a third capacitor connected in series from the contact points of the first and second capacitors to the ground.

In addition, as another technical means for achieving the object of the present invention, the multilayer ceramic filter of the present invention comprises: a first layer on which a first conductor pattern, which is a ground pattern, is formed on a first ceramic substrate; A second layer in which a second ceramic substrate is stacked on the first layer, and a second conductor pattern is formed on the second ceramic substrate; A third layer in which a third ceramic substrate is stacked on the second layer, and a third conductor pattern including a thirty-first inductor pattern and a thirty-second inductor pattern is formed on the third ceramic substrate; A fourth ceramic substrate is stacked on the third layer, and a fourth conductor pattern including a forty-first inductor pattern and a forty-second inductor pattern is formed on the fourth ceramic substrate. A fourth layer electrically connected to an inductor pattern and electrically connected to the forty-second inductor pattern with the thirty-second inductor pattern; A fifth layer in which a fifth ceramic substrate is stacked on the fourth layer, and a fifth conductor pattern is formed on the fifth ceramic substrate to electrically connect the fifth conductor pattern to the forty-first inductor pattern; A sixth layer stacked on the fifth layer, and having a sixth conductor pattern formed on the sixth ceramic substrate and connected to the thirty-first inductor pattern; A seventh layer formed on the sixth layer by stacking a seventh ceramic substrate, and forming a seventh conductor pattern on the seventh ceramic substrate to be connected to an input terminal and electrically connected to the thirty-second inductor pattern; An eighth layer laminated on an eighth ceramic substrate on the seventh layer, and having an eighth conductor pattern formed on the eighth ceramic substrate to be electrically connected to the sixth conductor pattern P6; A ninth layer in which a ninth ceramic substrate is stacked on the eighth layer, and a ninth conductor pattern is formed on the ninth ceramic substrate and connected to an output terminal; And a tenth layer stacked over the ninth layer, and having a tenth conductor pattern formed on the tenth ceramic substrate to be connected to the eighth conductor pattern.

Hereinafter, the configuration and operation of the high frequency filter circuit and the multilayer ceramic filter according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings referred to in the present invention, components having substantially the same configuration and function will use the same reference numerals.

5 is a high frequency filter circuit diagram according to a first embodiment according to the present invention, and FIGS. 6A and 6B are frequency characteristic diagrams of FIG. 5.

Referring to FIG. 5, a high frequency filter circuit according to a first embodiment of the present invention includes first and second capacitors C1 and C2 connected in series between an input terminal and an output terminal, and the first and second capacitors. A first inductor L1 connected in parallel to a series circuit of (C1, C2), a second inductor l2 connected in series from the contact point of the first and second capacitors C1, C2 to ground, and a second It consists of three capacitors (C3).

The high frequency filter circuit is implemented as a high pass filter or a low pass filter according to the setting of inductance and capacitance, for example, among dual modes including a GPS frequency band of 1.575 GHz and a US PCS frequency band of 1.92 GHz, FIG. 6B. As shown in Fig. 1, inductance and capacitance can be set with a high pass filter for passing the US PCS frequency band of 1.92 GHz, or in the dual mode, as shown in Fig. 6A, the GPS frequency band of 1.575 GHz is used. The low pass filter allows the inductance and capacitance to be set.

Referring to FIG. 6A, the frequency passing characteristic from the port 1 to the port 2 is illustrated by the frequency graph S12, and the frequency reflecting characteristic reflected from the port 2 to the port 2 is the frequency graph S22. As can be seen, the 1.575 GHz GPS frequency, which is the passband for S12, should satisfy the specification lower than the band -3 dB, which is almost 0 dB much lower than the -3 dB in FIG. It turns out that it is favorable compared with the conventional filter circuit.

In addition, referring to FIG. 6B, the frequency passing characteristic from the port 1 to the port 2 is illustrated by the frequency graph S12, and the frequency reflecting characteristic reflected from the port 2 to the port 2 is the frequency graph S22. As shown in FIG. 6A, the passband 1.82 GHz to 1.99 GHz PCS frequency for S12 should satisfy the specification lower than the band -3 dB. In FIG. 6 a, it is almost 0 dB much lower than about -3 dB. It can be seen that the frequency characteristic is as good as that of the conventional filter circuit.

As described above, the high frequency filter circuit according to the first embodiment of the present invention is a simple circuit having a steep frequency characteristic near a cutoff frequency. In order to have such characteristics in a conventional filter circuit, a high pass filter or The low-pass filter circuit should be composed of several stages, but such a conventional filter circuit has a problem that the circuit becomes complicated, but according to the high frequency filter circuit of the present invention, it has excellent frequency characteristics with a simple filter circuit.

7 is a high frequency filter circuit diagram according to a second embodiment according to the present invention. Referring to FIG. 7, a high frequency filter circuit according to the second embodiment according to the present invention is connected in series between an input terminal and an output terminal. The first and second inductors L11 and L12, the first capacitor C11 connected in parallel to the series circuits of the first and second inductors L11 and L12, and the first and second inductors L11, A second capacitor C12 and a third inductor L13 connected in series from the contact point with L12 to the ground.

In addition, as described above in the first embodiment of the present invention, the high frequency filter circuit corresponding to the second embodiment of the present invention is implemented as a high pass filter or a low pass filter according to the setting of inductance and capacitance. In the dual mode including the GPS frequency band of 1.575 GHz and the US PCS frequency band of 1.92 GHz, as shown in FIG. 6B, inductance and capacitance are set as a high pass filter for passing the US PCS frequency band of 1.92 GHz. Alternatively, in the dual mode, as shown in FIG. 6A, inductance and capacitance can be set as a low pass filter for passing a GPS frequency band of 1.575 GHz.

In the high frequency filter circuit of the present invention shown in the first and second embodiments of the present invention described above, the basis of the present invention is to further add a resonant circuit inside the existing resonant circuit, as shown in FIG. It connects the input port and the output port with parallel resonant circuit, and connects the series resonant circuit connected to the ground inside the parallel resonant circuit. Can be produced by connecting.

As described above, the circuit corresponding to the first embodiment of the present invention can be implemented with a multilayer ceramic filter as shown in FIG. 8, which will be described below.

8 is an exploded perspective view of a multilayer ceramic filter according to the present invention, and FIGS. 9A and 9B are plan and side views of the multilayer ceramic filter of FIG. 8.

8, 9A, and 9B, the multilayer ceramic filter according to the present invention includes a first layer LP1 having a first conductor pattern P1 formed as a ground pattern on a first ceramic substrate, and the first layer LP1. A second ceramic substrate is laminated on the layer LP1, and a second conductive layer P2 is formed on the second ceramic substrate, and a third layer is formed on the second layer LP2. A third layer LP3 having a ceramic substrate stacked and forming third conductor patterns P31 and P32 including a thirty-first inductor pattern and a thirty-second inductor pattern on the third ceramic substrate, and the third layer ( A fourth ceramic substrate is stacked on the LP3), and fourth conductor patterns P41 and P42 including the forty-first inductor pattern and the forty-second inductor pattern are formed on the fourth ceramic substrate, and the forty-first inductor pattern ( A fourth layer LP4 electrically connecting P41 to the thirty-first inductor pattern P31, and electrically connecting the forty-second inductor pattern P42 to the thirty-second inductor pattern P32; A fifth ceramic substrate is stacked on the fourth layer LP4, and a fifth conductor pattern P5 is formed on the fifth ceramic substrate to form the fifth conductor pattern P5 in the forty-first inductor pattern P41. A fifth layer LP5 electrically connected to the fifth layer LP, and a sixth ceramic substrate stacked on the fifth layer LP5, and a sixth conductor pattern P6 is formed on the sixth ceramic substrate to form the sixth ceramic pattern P6. The sixth layer LP6 connected to the inductor pattern P31 and the seventh ceramic substrate are stacked on the sixth layer LP6, and the seventh conductor pattern P7 is formed on the seventh ceramic substrate. A seventh layer LP7 connected to an input IN terminal and electrically connected to the thirty-second inductor pattern P32, and an eighth ceramic substrate stacked on the seventh layer LP7. An eighth layer LP8 formed by forming an eighth conductor pattern P8 on the substrate and electrically connected to the sixth conductor pattern P6, and a ninth ceramic substrate stacked on the eighth layer LP8. , This ninth year A ninth layer LP9 having a ninth conductor pattern P9 formed on the mixed substrate and connected to an output OUT terminal, and a tenth ceramic substrate stacked on the ninth layer LP9, The tenth conductor pattern P10 is formed on the substrate to form a tenth layer LP10 connected to the eighth conductor pattern P8.

A third capacitor is formed between the first conductor pattern P1 of the first layer LP1 and the second conductor pattern P2 of the second layer LP2, and a thirty-first inductor pattern of the third layer, The fourth inductor pattern of the fourth layer and the fifth conductor pattern of the fifth layer are electrically connected to each other through a via hole to form a second inductor, and the thirty-second inductor pattern of the third layer and the forty-second inductor pattern of the fourth layer Are electrically connected through the via holes to form a first inductor. The sixth conductor pattern P6 of the sixth layer LP6, the seventh conductor pattern P7 of the seventh layer LP7, and the eighth conductor pattern P8 of the eighth layer LP8 are first. A capacitor is formed and an eighth conductor pattern P8 of the eighth layer LP8, a ninth conductor pattern P9 of the ninth layer LP9, and a tenth conductor pattern P10 of the tenth layer LP10. To form a second capacitor.

8, 9A and 9B show a terminal arrangement when the high frequency filter circuit shown in FIG. 5 is implemented as a multilayer ceramic filter. Such a multilayer ceramic filter can be formed as a single chip by forming each device at the same time inside the chip, thereby increasing the degree of integration, miniaturizing the product and improving the characteristics.

The laminated structure and arrangement of the multilayer ceramic filter of the present invention shown in Figs. 8, 9A, and 9B are merely one embodiment for equivalently implementing the filter circuit shown in Fig. 5 and the filter circuit shown in Fig. 6. Therefore, the multilayer ceramic filter of the present invention is not limited to the structure and arrangement of FIG. 8, and various modifications and modifications are possible as long as the filter circuits of FIGS. 5 and 6 are equivalently satisfied.

The high frequency filter circuit to which the present invention as described above is applied may include a high pass filter or a low pass filter, and the present invention is not only a diplexer but also a duplexer or the like. It can be applied to a communication device or system for selecting a frequency band.

According to the present invention as described above, by improving the high-frequency filter applied to the high-frequency composite components of the dual-mode mobile communication terminal with a simple circuit, it is possible to miniaturize and reduce the insertion loss, to improve the blocking characteristics There is a special effect.

In addition, the insertion loss in the GPS band can be reduced and the stopping characteristic can be increased in the PCS band. In this case, the value of each device can be implemented with a multilayer ceramic, which can be manufactured directly with a multilayer chip, and without modifying the circuit. If only the value is changed, it can be manufactured with low pass filter or high pass filter.

The above description is only a description of specific embodiments of the present invention, and the present invention is not limited to these specific embodiments, and various changes and modifications of the configuration are possible from the above-described specific embodiments of the present invention. It will be apparent to those skilled in the art to which the present invention pertains.

Claims (12)

In the high frequency filter, First and second capacitors C1 and C2 connected in series between an input terminal and an output terminal; A first inductor L1 connected in parallel to the series circuits of the first and second capacitors C1 and C2; And a third inductor (l2) and a third capacitor (C3) connected in series from the contact points of the first and second capacitors (C1, C2) to ground. The method of claim 1, wherein the high frequency filter circuit A high frequency filter circuit for setting inductance and capacitance with a high pass filter. The method of claim 1, wherein the high frequency filter circuit A high frequency filter circuit for setting inductance and capacitance with a low pass filter. In the high frequency filter, First and second inductors L11 and L12 connected in series between an input terminal and an output terminal; A first capacitor C11 connected in parallel to the series circuits of the first and second inductors L11 and L12; And a third capacitor (C12) and a third inductor (L13) connected in series from the contact points of the first and second inductors (L11, L12) to ground. The method of claim 4, wherein the high frequency filter circuit A high frequency filter circuit for setting inductance and capacitance with a high pass filter. The method of claim 4, wherein the high frequency filter circuit A high frequency filter circuit for setting inductance and capacitance with a low pass filter. A first layer LP1 having a first conductor pattern P1 formed as a ground pattern on the first ceramic substrate; A second layer LP2 having a second ceramic substrate stacked on the first layer LP1 and having a second conductor pattern P2 formed on the second ceramic substrate; A third ceramic layer stacked on the second layer LP2 and having third conductor patterns P31 and P32 including a thirty-first inductor pattern and a thirty-second inductor pattern formed thereon; Layer LP3; A fourth ceramic substrate is stacked on the third layer LP3, and fourth conductor patterns P41 and P42 including the forty-first inductor pattern and the forty-second inductor pattern are formed on the fourth ceramic substrate. Fourth layer LP4 electrically connecting the forty-first inductor pattern P41 to the thirty-first inductor pattern P31, and electrically connecting the forty-second inductor pattern P42 to the thirty-second inductor pattern P32. ; A fifth ceramic substrate is stacked on the fourth layer LP4, and a fifth conductor pattern P5 is formed on the fifth ceramic substrate to form the fifth conductor pattern P5 in the forty-first inductor pattern P41. ) A fifth layer (LP5) electrically connected; The sixth layer LP6, in which a sixth ceramic substrate is stacked on the fifth layer LP5, and a sixth conductor pattern P6 is formed on the sixth ceramic substrate to be connected to the thirty-first inductor pattern P31. ); A seventh ceramic substrate is stacked on the sixth layer LP6, and a seventh conductor pattern P7 is formed on the seventh ceramic substrate to be connected to the input IN, and the thirty-second inductor pattern P32 is formed. A seventh layer LP7 electrically connected with the seventh layer LP7; An eighth ceramic layer stacked on the seventh layer LP7, and an eighth conductor pattern P8 is formed on the eighth ceramic substrate to be electrically connected to the sixth conductor pattern P6. (LP8); A ninth layer LP9 having a ninth ceramic substrate stacked on the eighth layer LP8 and having a ninth conductive pattern P9 formed on the ninth ceramic substrate and connected to an output terminal; And A tenth ceramic layer (LP10) on which a tenth ceramic substrate is stacked on the ninth layer (LP9), and a tenth conductor pattern (P10) is formed on the tenth ceramic substrate and connected to the eighth conductor pattern (P8). A multilayer ceramic filter comprising: The method of claim 7, wherein The multilayer ceramic filter of claim 1, wherein a third capacitor is formed between the first conductor pattern P1 of the first layer LP1 and the second conductor pattern P2 of the second layer LP2. The method of claim 7, wherein And the thirty-first inductor pattern of the third layer, the forty-first inductor pattern of the fourth layer, and the fifth conductor pattern of the fifth layer are electrically connected to each other to form a second inductor. The method of claim 7, wherein And a thirty-second inductor pattern of the third layer and a forty-second inductor pattern of a fourth layer to electrically connect the via-holes to form a first inductor. The method of claim 7, wherein A first capacitor is connected to the sixth conductive pattern P6 of the sixth layer LP6, the seventh conductive pattern P7 of the seventh layer LP7, and the eighth conductive pattern P8 of the eighth layer LP8. Multilayer ceramic filter, characterized in that it is formed. The method of claim 7, wherein A second capacitor is connected to the eighth conductive pattern P8 of the eighth layer LP8, the ninth conductive pattern P9 of the ninth layer LP9, and the tenth conductive pattern P10 of the tenth layer LP10. A multilayer ceramic filter, characterized in that the forming.